WO1996006460A1 - Dispositif semi-conducteur - Google Patents

Dispositif semi-conducteur Download PDF

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Publication number
WO1996006460A1
WO1996006460A1 PCT/JP1995/000966 JP9500966W WO9606460A1 WO 1996006460 A1 WO1996006460 A1 WO 1996006460A1 JP 9500966 W JP9500966 W JP 9500966W WO 9606460 A1 WO9606460 A1 WO 9606460A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor
semiconductor device
substrate
semiconductor chip
analog
Prior art date
Application number
PCT/JP1995/000966
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English (en)
Japanese (ja)
Inventor
Yasuaki Kagotoshi
Kenji Maio
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Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Publication of WO1996006460A1 publication Critical patent/WO1996006460A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

Definitions

  • the present invention relates to a semiconductor device, and in particular, is effectively applied to an analog / digital hybrid semiconductor device in which an analog module (analog circuit) and a digital module (digital circuit) are integrated on the same semiconductor chip.
  • an analog module analog circuit
  • a digital module digital circuit
  • JP-A-58-70565 and JP-A-59-193046 describe that noise generated in a digital circuit section is mixed into an analog circuit section,
  • the document states that the power supply wiring for each of the digital circuit and the analog circuit is provided independently to prevent the malfunction of the circuit from malfunctioning.
  • Ma Japanese Patent Application Laid-Open No. 2-271567 discloses a digital circuit unit and an analog circuit unit using a substrate having an SOI (Silicon On Insulator) structure and a separation groove reaching an insulating layer of the substrate. And a technique for insulating and separating the same.
  • SOI Silicon On Insulator
  • the present inventor has found the following problems as a result of studying the electrical reliability of the analog-Z digital mixed-type semiconductor integrated circuit device.
  • the power supply wiring and the ground (GND) self-line formed on the main surface of the semiconductor chip are formed independently of the analog circuit and the digital circuit. Therefore, the noise from the power supply wiring and the noise from the ground (GND) wiring rarely interact with each other.
  • the ground (GND) wiring of each of the analog circuit and the digital circuit is the same as that of the encapsulant (LSI package). Externally, it is connected to the common ground (GND) wiring on the mounting board, but the common ground (GND) wiring on the mounting board is much higher than the ground (GND) wiring formed on the semiconductor chip. The effect of noise is small because the impedance is low.
  • the above-mentioned conventional technology does not consider noise transmitted through the inside of a half chip, and furthermore, noise transmitted through a metal lead frame on which a semiconductor chip is mounted. Can not be effectively reduced and prevented.
  • the semiconductor chip 1 is usually mounted on a metal lead frame, and a conductive adhesive 3 such as silver (Ag) paste is used to support the chip supporting portion (die pad portion) of the lead frame. It is fixed to 2 (in the figure, the lead portion of the lead frame and a sealing material such as resin are omitted for convenience of explanation).
  • the chip supporting portion (die pad portion) 2 on which the semiconductor chip 1 is mounted is a conductor having a very low resistance over the entire surface.
  • the noise generated by the digital module 5 was easily transmitted to the analog module via a path via the chip supporting section (die pad section) 2, and it became clear that the performance of the analog module was degraded and a malfunction was caused.
  • the resistance of the path 6 that propagates in the silicon substrate 1 in the lateral direction is about 16.5 ⁇ .
  • the noise generated by the digital module 5 is once transmitted to the vertical metal chip supporting portion (die pad portion) 2 and further through the chip supporting portion (die pad portion) 2 to the lower part of the analog module 4.
  • the resistance of the path 7, which reenters the silicon substrate 1 in the vertical direction from the part and is transmitted to the analog module, is sufficient for the resistance of the metal chip support part (die pad part) 2 to be greater than the resistance of the silicon substrate 1. Because it is small, it becomes about 15 ⁇ .
  • the metal chip support (die pad) is sealed in an electrically floating state inside the sealing body (LSI package), it is transmitted from the digital module to the chip support (die pad).
  • the ground noise (GND) wiring formed on the surface of the silicon substrate is electrically connected to the low-impedance common ground wiring formed on the mounting board outside the sealing body (LSI package). The probability of returning to the silicon substrate is high. As a result, there is a problem that the electrical reliability of the analog / digital hybrid semiconductor integrated circuit device is further reduced. Occurs.
  • the thickness of an insulating film such as a silicon oxide film used in a semiconductor substrate or in a semiconductor manufacturing process is about 1, so if the area of the insulating film portion is 4.6 ran2 or more, for example,
  • the SOI substrate cannot supply ground potential (GND) from the back side of the substrate due to its structure, it is disadvantageous in terms of noise absorption efficiency and stabilization of the substrate potential.
  • GND ground potential
  • An object of the present invention is to improve the electrical reliability of an analog / digital hybrid semiconductor integrated circuit device.
  • Another object of the present invention is to improve the electrical reliability of a semiconductor device including an analog / digital mixed semiconductor integrated circuit device.
  • Another object of the present invention is to reduce the cost of a semiconductor device including a mixed analog / digital semiconductor integrated circuit device.
  • a semiconductor device including an analog / digital hybrid semiconductor device includes a chip support portion made of a conductive layer to which a ground potential is supplied, a semiconductor substrate (semiconductor chip) mounted on the chip support portion, and A digital module formed in a first region of the main surface of the semiconductor substrate; and an analog module formed in a second region of the main surface of the semiconductor substrate different from the first region.
  • the semiconductor substrate is electrically connected only at a lower portion of the first region, and is not electrically connected at a lower portion of the second region. Further, an insulating layer is formed below the second region, between the chip supporting portion and the semiconductor substrate.
  • a semiconductor device including an analog-Z digital mixed-type semiconductor integrated circuit device includes a chip supporting portion made of a conductive layer to which a ground potential is supplied, a semiconductor substrate (semiconductor chip) mounted on the chip supporting portion, A digital module formed in a first region of the main surface of the semiconductor substrate, and an analog module formed in a second region of the main surface of the semiconductor substrate different from the first region;
  • the chip support portion is provided only at the lower portion, and the chip support portion and the semiconductor substrate are electrically connected at a lower portion of the first region.
  • the chip support and the semiconductor substrate are electrically connected only at the lower part of the digital module, or because the chip support does not exist at the lower part of the analog module, noise generated in the digital module is reduced. Since the path for transmitting to the analog module via the chip supporting portion composed of the analog module can be cut off, the influence of noise on the analog module can be reduced. Also, by making the chip support below the digital module a conductive layer, noise generated by the digital module can be reduced via the chip support to a mounting board with low-impedance common ground wiring. Since it is possible to escape to the outside of the device, the effect of noise on the analog module can be reduced. In addition, since the ground potential can be positively applied to the semiconductor substrate via the chip supporting portion, the potential of the semiconductor substrate can be stabilized. Accordingly, it is possible to improve the electrical reliability of the semiconductor device including the analog / Z-digital hybrid type semiconductor integrated circuit device.
  • the above-described configuration is such that the semiconductor substrate and the chip supporting portion below the analog module are provided. This can be achieved by a simple process of forming an insulating layer having a desired thickness between the two or removing the chip supporting portion under the analog module. The electrical reliability of the semiconductor device can be improved, and the cost can be reduced.
  • FIG. 1 is a simulation diagram of a semiconductor device including an analog / digital hybrid type semiconductor integrated circuit device studied in the course of forming the present invention by the inventor
  • FIG. 2 is an analog Z / digital hybrid type hybrid device according to a first embodiment of the present invention
  • FIG. 3 is a plan view of a semiconductor device including a semiconductor integrated circuit device
  • FIG. 3 is a cross-sectional view corresponding to a dashed line AA in FIG. 2
  • FIG. 4 is an analog diagram showing an example of a semiconductor chip mounted on the semiconductor device of the present invention.
  • FIG. 5 is a cross-sectional view showing an example of a semiconductor element included in the analog-Z digital hybrid-type semiconductor integrated circuit device of FIG. 2, and FIG. FIG.
  • FIG. 7 is a plan view of a semiconductor device including an analog / digital mixed semiconductor integrated circuit device according to a second embodiment
  • FIG. 7 is a cross-sectional view corresponding to a dashed line A′—A ′ in FIG. 6
  • FIG. 9 is a cross-sectional view showing an example of a semiconductor element constituting the analog-digital hybrid embedded semiconductor integrated circuit device of FIG. 6.
  • FIG. 9 is a semiconductor device including an analog Z digital hybrid embedded semiconductor integrated circuit device according to a third embodiment of the present invention.
  • FIG. 10 is a cross-sectional view corresponding to the dashed-dotted line BB of FIG. 9
  • FIG. 11 is a cross-sectional view showing a state sealed by a cap
  • FIG. 12 is a fourth view of the present invention.
  • FIG. 10 is a cross-sectional view corresponding to the dashed-dotted line BB of FIG. 9
  • FIG. 11 is a cross-sectional view showing a state sealed by a cap
  • FIG. 12
  • FIG. 13 is a plan view of a semiconductor device including an analog / digital hybrid type semiconductor integrated circuit device according to an embodiment
  • FIG. 13 is a cross-sectional view corresponding to a dashed-dotted line C-C of FIG. 12
  • FIG. FIG. 15 is a cross-sectional view showing an example of a semiconductor element included in an analog / digital mixed-type semiconductor integrated circuit device.
  • FIG. 15 is a modified example of the analog / digital mixed-type semiconductor integrated circuit of the fourth embodiment of the present invention.
  • FIG. 16 is a sectional view of a main part of a semiconductor device including a circuit device. It is a fragmentary cross-sectional view of a semiconductor device including an analog / digital hybrid semiconductor IC device which is a modification of the light.
  • FIGS. 2 and 3 show a semiconductor device according to a first embodiment of the present invention.
  • FIG. 3 is a cross-sectional view taken along a dashed line AA in FIG.
  • the semiconductor device 100 is a QFP (Quad Flat Package), which is a resin-sealed package using metal lead frames 2, 8a, and 8b.
  • QFP Quad Flat Package
  • an analog module 4 and a digital module 5 are mounted on a semiconductor chip (semiconductor substrate) 1.
  • the semiconductor chip 1 is mounted on the upper surface of a chip supporting portion (die pad portion or tab) 2 of a metal lead frame.
  • the semiconductor chip 1 and the chip supporting portion (die pad portion or tab) 2 are made of silver (Ag) paste. It is fixed with a conductive adhesive 3 such as.
  • a conductive adhesive 3 such as.
  • the semiconductor chip 1 for example, a single crystal silicon substrate is used, and for the metal lead frame, for example, an iron-nickel alloy (42 alloy) is used.
  • a plurality of external terminals (bonding pads) 9 for supplying power and for inputting and outputting electric signals to and from external devices are formed in a peripheral portion of the main surface of the semiconductor chip 1.
  • the lead 8a of the frame is electrically connected to a metal wire 10 such as gold (Au).
  • the structure in which the semiconductor chip 1 is mounted on the metal lead frame is sealed with an epoxy resin 11. Note that, in FIG. 2, a part of the lead 8a is omitted by a broken line to make the drawing easy to understand, and only the outline of the epoxy resin 11 is shown.
  • the lead for supplying the ground potential from the front side of the semiconductor chip 1 to the analog module 4 is indicated by AGND, and the digital module 5 is connected to the ground potential from the front side of the semiconductor chip 1 by the lead portion 8a.
  • the lead for supplying the is indicated by DGND.
  • a lead portion 8b integrally formed at a corner portion of the chip supporting portion 2 is a lead for supplying a ground potential from the surface side of the semiconductor chip 1, and is indicated by a supporting substrate GND. .
  • the above-mentioned AGND, DGND, and support substrate GND are connected to a common ground wiring (mounting ⁇ ⁇ GND) of a mounting substrate (not shown) outside the semiconductor device 100.
  • This common ground wiring is formed on the semiconductor chip 1 by ordinary photolithography and etching techniques. This is a low-impedance wiring formed in a sufficiently large area than the ground wiring formed by the technique. Therefore, even when the above-mentioned AGND and DGND are connected in common, the influence of the noise generated in the digital module 5 on the analog module 4 is small.
  • the chip supporting portion 2 located under the analog module 4 is removed, and the chip supporting portion to which the semiconductor chip 1 and the ground potential are supplied is provided only under the digital module 5. It has been electrically connected to part 2.
  • the semiconductor chip 1 is electrically connected to the chip supporting portion 2 to which the ground potential is supplied by using a metal lead frame having no chip supporting portion 2 below the analog module 4.
  • the chip supporting portion 2 since the chip supporting portion 2 does not exist below the analog module 4, noise is transmitted from the digital module to the analog module via the metal lead frame shown in FIG. Route 7 can be cut off. That is, the noise generated by the digital module is interrupted from being transmitted to the analog module via the metal lead frame, and the analog module is not affected by the noise.
  • the semiconductor chip 1 is mounted under the digital module 5 by electrically connecting the semiconductor chip 1 to the common ground wiring of the low-impedance mounting board.
  • the substrate potential of the semiconductor chip 1 can be stabilized.
  • noise generated from the digital module can be released to the common ground wiring of the mounting board outside the semiconductor device 100 via the chip supporting portion 2 and the lead 8b. Therefore, the electrical reliability of the semiconductor device including the analog / digital hybrid type semiconductor integrated circuit device can be improved.
  • the configuration of the first embodiment described above can be achieved by partially changing the shape of the metal lead frame, which is advantageous for cost reduction.
  • an analog module 4 and a digital module 5 are formed in different areas on a main surface of a semiconductor chip 1 made of single crystal silicon. Have been.
  • the analog module 4 includes an analog Z digital converter (Analog to Digital Converter) A DC. This analog Z-to-digital converter ADC samples data at clock timing. Also, depending on the specifications, the analog module 4 may be equipped with an amplifier, a digital Z-to-analog converter, and a switched capacitor.
  • the digital module 5 includes a read only memory (Read Only Memory) ROM, a random access memory (Random Access Memory) RAM, a central processing unit (Central Processing Unit) CPU, a timer and a serial It includes a CPU peripheral module equipped with a communication interface, etc., and a logic circuit composed of a gate array. That is, the semiconductor chip 1 is composed of application-specific IC (AS IC).
  • AS IC application-specific IC
  • the power supply wiring 12 and the ground wiring 13 for the analog module 4 and the power supply wiring 14 and the ground wiring 15 for the digital module 5 are formed independently of each other. Mutual interference between modules is reduced. For example, +3.3 V is supplied to the power supply wirings 12 and 14, and 0 V is supplied to the ground wirings 13 and 15, for example.
  • the power supply wiring and the ground wiring may be laid out in the area 16 between the analog module and the digital module in order to reduce crosstalk in the surface area of the semiconductor chip 1.
  • a penetration region N—WELL composed of an N-type semiconductor region and a pell region P—WELL composed of a P-type semiconductor region are formed on the main surface of the P-type single-crystal silicon substrate P—Sub, which is the semiconductor chip 1, a penetration region N—WELL composed of an N-type semiconductor region and a pell region P—WELL composed of a P-type semiconductor region are formed. ing.
  • a P-channel MOSFET (PMOS 1, PM0S 2) is formed on the principal surface of the N-WELL on the principal surface of the cell region surrounded by the field insulating film 17 made of a silicon oxide film, and a Pell region surrounded by the field insulating film 17.
  • N-channel MOS FETs (NMOS 1 and NMOS 2) are formed on the main surface of the P-WELL.
  • PMOS 1 consists of a gate oxide film 19 formed on the surface of the N-WELL and this gate.
  • the NMOS 1 has a gate oxide film 19 formed on the surface of the P-WELL, a gate electrode 18 formed on the gate oxide film 19, and P-WELL on both sides of the gate electrode 18b. It includes a source region 20b and a drain region 20b formed of an N + type semiconductor region.
  • the power supply AVcc for the analog module is supplied to the source connector 20a comprising the source region 20a of the PMOS 1 and the N + type semiconductor region, and the source connector 20a comprising the source region 20b of the NMOS 1 and the P + type semiconductor region.
  • the contact 21 is supplied with the ground potential AGND for the analog module.
  • the analog module 4 includes semiconductor elements such as the PMOS 1 and the NMOS 1 described above. For example, the gates 18a and 181) of the PMOS 1 and the NMOS 1 are input 1? ⁇ , CMOS (Complementary MOS FET) Inverter circuit with drain regions 20a and 20b as output OUT.
  • CMOS Complementary MOS FET
  • the PMOS 2 includes a gate oxide film 19 formed on the surface of the N-WELL, a gate electrode 18 d formed on the gate oxide film 19, and N-WELLs on both sides of the gate electrode 18 d. It includes a source region 20 d and a drain region 20 d formed of the formed P + type semiconductor region.
  • the NMOS 2 is formed on the gate oxide film 19 formed on the surface of the P-WELL, the gate electrode 18c formed on the gate oxide film 19, and the P-WELL on both sides of the gate electrode 18c. And a source region 20c and a drain region 20c made of an N + type semiconductor region.
  • the power supply DV cc for the digital module is supplied to the diode connection 2 Id comprising the source region 20 d of the PMOS 2 and the N + type semiconductor region, and comprises the source region 20 c of the NMOS 2 and the P + type semiconductor region.
  • ⁇ L contact 21c is supplied with the ground potential DGND for the digital module.
  • the digital module 4 includes semiconductor elements such as the PMOS 2 and the NMOS 2 described above.
  • the gate electrodes 18 d and 18 (; of the PMOS 2 and the NMOS 2 are input 11 ⁇ , and the drain regions 20 d and 20 c A CMOS (complementary MOS FET) inverter circuit with the output OUT.
  • CMOS complementary MOS FET
  • the gate electrodes 18a to 18d of the MOS FET are made of, for example, polycrystalline silicon containing N-type impurities, and are wires for supplying power to the respective semiconductor devices and wires for connecting the respective semiconductor devices. Is made of, for example, aluminum or an aluminum alloy obtained by adding copper and silicon to aluminum.
  • the chip supporting portion 3 of the metal lead frame is connected to the P-type single crystal silicon substrate P-
  • the pattern of the chip supporting section 3 shown in FIG. 5 corresponds to the pattern of the chip supporting section 3 shown in FIGS. 2 and 3, and the chip supporting section 3 is not provided at the lower part of the analog module. I have.
  • FIG. 7 is a cross-sectional view taken along a dashed line A′-A ′ in FIG.
  • the chip supporting part 2 of the metal lead frame is also located at the lower part of the analog module 4, but at the lower part of the analog module 4, between the semiconductor chip 1 and the chip supporting part 2.
  • An insulating film indicated by a broken line 22 in FIG. 6 is formed.
  • the insulating film 22 for example, a plastic film having a thickness of 0.1 lram or more is used.
  • the metal lead frame shown in FIG. The path through which noise enters the analog module from the digital module via the digital module can be cut off. That is, the noise generated from the digital module is blocked from being transmitted to the analog module on the path through the metal lead frame, and the analog module is not affected by this noise.
  • an insulation film is formed only on the lower part of the analog module of the metal lead frame chip part 2, and on the lower part of the digital module 5, the semiconductor chip 1 is electrically connected to the common ground wiring of the low-impedance mounting board.
  • the substrate potential of the semiconductor chip 1 is reduced by positively connecting to the Stabilization can be achieved.
  • noise generated from the digital module can be released to the common ground wiring of the mounting board outside the semiconductor device 100 via the chip support 2 and the leads 8b. Therefore, the electrical reliability of the semiconductor device including the analog / digital hybrid type semiconductor integrated circuit device can be improved.
  • the configuration of the second embodiment described above can be achieved by a simple operation of attaching an insulating film or attaching an insulating material, which is advantageous for cost reduction.
  • the pattern of the chip support 2 shown in FIG. 8 corresponds to the pattern of the chip support 3 shown in FIGS. 6 and 7, and the chip support 2 is also formed below the analog module 4. However, below the analog module 4, the semiconductor chip 1 and the chip support 2 have a structure that is not electrically connected by the insulating film 22.
  • a gap may be provided between the semiconductor chip 1 and the chip supporting portion 2 below the analog module 4 without forming the insulating film 22. Good.
  • the adhesion between the semiconductor chip 1 and the chip supporting portion 2 and the The wire bonding reliability between the external electrode 9 formed around and the lead 8a is slightly reduced.
  • FIG. 10 is a cross-sectional view taken along dashed line BB in FIG.
  • the semiconductor device 300 is a QFN (Quad Flat Non-leaded Package) or LCC (Leadless Tip Carrier), and is a stacked ceramic type package using metallized layers 2, 8a, and 8b.
  • an analog module 4 and a digital module 5 are mounted on a semiconductor chip (semiconductor substrate) 1 in a mixed manner.
  • the semiconductor chip 1 is mounted on an upper surface of a chip supporting portion 2 of a metallized layer formed on a ceramic substrate 23.
  • the semiconductor chip 1 and the chip support 2 are fixed by a conductive adhesive 3 such as a silver paste.
  • a ceramic frame 25 is laminated on the ceramic substrate 23, and a metallized lead is formed on the surface of the frame 25. 8a is formed.
  • the metallized layer is formed by, for example, plating of nickel, gold, copper, or the like, or screen printing technology.
  • the periphery of the main surface of the semiconductor chip 1 is connected to a power supply or an external device.
  • a plurality of external terminals (bonding pads) 9 for inputting / outputting electric signals are formed, and the external terminals 9 and the metallized lead portions 8a are electrically connected by metal wires 10 such as gold (Au). I have.
  • the structure in which the semiconductor chip 1 is mounted on the ceramic substrate 23 via the metallization layer is sealed by a ceramic frame 26 and a cap 27, as shown in FIG.
  • the frames 25 and 26 and the cap 27 are bonded to each other by, for example, low-melting glass.
  • the metal wire 10, the frame 26, and the cap 27 are omitted for easy understanding of the drawing.
  • the lead for supplying the ground potential from the surface of the semiconductor chip 1 to the analog module 4 is indicated by AGND
  • the lead to the digital module 5 from the surface of the semiconductor chip 1 is ground potential.
  • the lead to supply the IGBT is indicated by DGND.
  • a metallized lead portion 8b integrally formed at a corner of the chip supporting portion 2 is a lead for supplying a ground potential from the back surface of the half chip 1, and is indicated by a supporting substrate GND.
  • the AGND, DGND, and support substrate GND are connected to a common ground wiring (mounting substrate GND) of a mounting substrate (not shown) outside the semiconductor device 300, similarly to the first and second embodiments described above.
  • the common ground wiring is a low-impedance wiring formed in a sufficiently larger area than the ground wiring formed on the semiconductor chip 1 by ordinary photolithography and etching techniques. Therefore, even when the above-mentioned AGND and DGND are commonly connected, the influence of the noise generated in the digital module 5 on the analog module 4 is small.
  • the metallization layer located below the analog module 4 is removed as shown by the pattern of the broken line 24 in FIG. Chip 1 and ground potential This is because the metallized layer (chip support 2) is electrically connected.
  • a metallized layer pattern without a metallized layer (chip supporting portion 2) under the analog module 4 is used to electrically connect the semiconductor chip 1 and the metallized layer (chip supporting portion 2) supplied with the ground potential. Have connected.
  • the digital module is provided via the metallization layer corresponding to the metal lead frame shown in FIG. It is possible to cut off the route 7 where noise enters the ana-gumo module from Yule. That is, the noise generated from the digital module is blocked from being transmitted to the analog module in the path through the metallization layer, so that the analog module is not affected by the noise.
  • the configuration of the present invention can be achieved by partially changing the pattern of the metallized layer, which is advantageous in reducing costs.
  • an insulating film may be formed below the analog module 4 between the semiconductor chip 1 and the ceramic substrate 23 as in the second embodiment described above.
  • the insulating film may be formed in the pattern indicated by the broken line 24 in FIG.
  • the metallized lead 8a has a structure in which the metallized lead 8a is drawn out to the outside from the side surfaces of the frame 25 and the ceramic substrate 23 as in this example. You may draw it out.
  • a substrate and a frame such as glass epoxy may be used instead of the ceramic substrate 23 and the frames 25 and 26, a substrate and a frame such as glass epoxy may be used.
  • the metallized layers 2, 8a and 8b are formed on the insulating substrate and the frame. For example, it may be formed by a plating method such as copper or a screen printing technique.
  • FIG. FIG. 13 is a cross-sectional view taken along dashed-dotted line C-C in FIG.
  • the chip supporting portion (die pad portion) 2 of the metal lead frame has a circular pattern whose outer shape is smaller than that of the semiconductor chip 1.
  • the lead portion 8b of the metal lead frame is formed integrally with the circular chip support portion 2 to form a so-called small tab lead frame configuration.
  • the circular chip support portion 2 is electrically connected to the back surface of the semiconductor chip 1 via a conductive adhesive 3 at a lower portion of the digital module 5 and supplies a ground potential (support substrate GND).
  • a conductive adhesive 3 at a lower portion of the digital module 5 and supplies a ground potential (support substrate GND).
  • the metal lead frame portion 8b is also located below the analog module 4, an insulating film 28 is formed below the analog module 4 between the semiconductor chip 1 and the metal lead frame portion 8b. Have been.
  • the insulating film 28 for example, an insulating film having a thickness of about 0.1 mm or an oxide film having a thickness of about 10 Hm applied to the back surface of the semiconductor chip 1 is used.
  • a part of the lead frame 8a is located at the lower part of the analog module 4, but since the overlapping area of the analog module 4 and the lead frame 8a is small, The capacity between the semiconductor chip Z lead frame at the bottom of module 4 is small.
  • the overlapping area at this time is approximately 0.5 mm 2 or less, so the capacity of the overlapping portion is 0.17 to 1.7 pF or less, and the impedance is 100 MHz. It is about lk to 10 kQ with respect to noise. Therefore, also in this case, the transmission of the noise generated from the digital module 5 to the analog module 4 is interrupted on the path through the gold lead frame.
  • the area of the chip supporting portion 2 below the digital module 5 is set to 4.6 mm 2 or more, even if an oxide film having a thickness of about 10 m is formed on the back surface of the semiconductor chip 1, the impedance becomes 1 It becomes less than 100 ⁇ , and noise can be transmitted to the lead frame.
  • ⁇ even in the lower part of the digital module 5, An insulating film 28 is formed between the semiconductor chip 1 and the metal lead frame 8b, but at least at the lower part of the analog module 4 between the semiconductor chip 1 and the gold lead frame portion 8b. What is necessary is that the film 28 is formed.
  • the chip supporting portion 2 does not have to be circular, but may be polygonal such as triangular or quadrangular. Further, since the chip supporting portion 2 is formed smaller than the semiconductor chip 1, there is an advantage that a reflow crack at the time of resin molding can be prevented. Further, since there is no limitation on the size of the semiconductor chip 1 mounted on the lead frame, it is advantageous for the packaging of application specific ICs (ASICs) using a plurality of types of semiconductor chips.
  • ASICs application specific ICs
  • the analog module 4 since an insulator is formed between the semiconductor chip 1 and the chip supporting portion 2 (metal lead frame portion 8b) below the analog module 4,
  • the path 7 through which noise enters the analog module 4 from the digital module 5 can be cut off via the metal lead frame shown in FIG. That is, since the noise generated from the digital module 5 is blocked from being transmitted to the analog module 4 in the path through the metal lead frame, the analog module 4 is not affected by this noise.
  • an insulator is formed under the analog module in the chip support portion 2 (metal lead frame portion 8b) of the metal lead frame, and is formed under the digital module 5
  • the semiconductor chip 1 is positively connected to the chip support 2 electrically connected to the common ground wiring of the low-impedance mounting board, thereby stabilizing the substrate potential of the semiconductor chip 1. be able to. Further, noise generated from the digital module can be released to the common ground wiring of the mounting board outside the semiconductor device 400 via the chip supporting portion 2 and the leads 8b. Accordingly, it is possible to improve the electrical reliability of the semiconductor device including the analog / digital hybrid semiconductor integrated circuit device S. Further, the configuration of the fourth embodiment can be achieved by a simple operation of attaching an insulating film or attaching an insulating material, which is advantageous for cost reduction.
  • the pattern of the chip supporting portion 2 and the lead portion 8b shown in FIG. 14 corresponds to the pattern of the chip supporting portion 2 and the lead portion 8b shown in FIG. 12 and FIG.
  • the semiconductor chip 1 and the lead part 8b are not electrically connected by the insulating film 28. It has a structure.
  • the lead portion 8b and the chip support portion 2 It is only necessary to use a lead frame having a step with a step, or to apply a thick adhesive layer 3 on the upper surface of the chip supporting portion 2. Further, the lead portion 8b located at the lower part of the analog module 4 may be removed.
  • a lead frame that does not have a lead portion 8b for supplying a ground potential (support substrate GND) directly from the back of the semiconductor chip (a configuration in which the chip support portion of the lead frame is independent of external leads)
  • the chip support (die pad) 2 and the lead 8a are connected (wire-bonded) with the metal wire 10a, and the chip support 2 is electrically connected to the chip support 2.
  • the connected lead 8a may be a dedicated lead for supplying the ground potential (support substrate GND).
  • the semiconductor device including the analog / digital mixed semiconductor integrated circuit device of the present invention has high electrical reliability, the semiconductor device built in a small electronic device such as a mobile radio or a video camera. It is suitable for use in

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  • Semiconductor Integrated Circuits (AREA)

Abstract

Dispositif semi-conducteur comprenant un circuit intégré semi-conducteur combiné analogique/numérique et pourvu d'une partie de support (2) de microcircuit constituée d'une couche conductrice reliée à la masse, d'un substrat semi-conducteur (microcircuit semi-conducteur) (1) monté sur la partie (2), d'un module numérique (5) formé sur une première zone de la surface principale du substrat (1), et d'un module analogique (4) formé sur une deuxième zone, différente de la première, de la surface principale du substrat (1). La partie (2) est reliée électriquement au substrat (1), non pas par la deuxième zone mais par la première zone seulement.
PCT/JP1995/000966 1994-08-19 1995-05-19 Dispositif semi-conducteur WO1996006460A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP6/195120 1994-08-19
JP19512094 1994-08-19

Publications (1)

Publication Number Publication Date
WO1996006460A1 true WO1996006460A1 (fr) 1996-02-29

Family

ID=16335830

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP1995/000966 WO1996006460A1 (fr) 1994-08-19 1995-05-19 Dispositif semi-conducteur

Country Status (1)

Country Link
WO (1) WO1996006460A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998012750A1 (fr) * 1996-09-20 1998-03-26 Hitachi, Ltd. Composant de circuit integre a semi-conducteur
WO2002089204A1 (fr) * 2001-04-16 2002-11-07 Niigata Seimitsu Co., Ltd. Dispositif semiconducteur
KR100561952B1 (ko) * 2002-09-13 2006-03-21 주식회사 한화 미진동 파쇄제 조성물

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51138390A (en) * 1975-05-26 1976-11-29 Hitachi Ltd Semiconductor device
JPH05198746A (ja) * 1991-11-19 1993-08-06 Matsushita Electric Ind Co Ltd 半導体装置
JPH05235266A (ja) * 1992-02-24 1993-09-10 Nec Ic Microcomput Syst Ltd 半導体集積回路装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51138390A (en) * 1975-05-26 1976-11-29 Hitachi Ltd Semiconductor device
JPH05198746A (ja) * 1991-11-19 1993-08-06 Matsushita Electric Ind Co Ltd 半導体装置
JPH05235266A (ja) * 1992-02-24 1993-09-10 Nec Ic Microcomput Syst Ltd 半導体集積回路装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998012750A1 (fr) * 1996-09-20 1998-03-26 Hitachi, Ltd. Composant de circuit integre a semi-conducteur
WO2002089204A1 (fr) * 2001-04-16 2002-11-07 Niigata Seimitsu Co., Ltd. Dispositif semiconducteur
KR100561952B1 (ko) * 2002-09-13 2006-03-21 주식회사 한화 미진동 파쇄제 조성물

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