Classifications

• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
  • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
  • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
  • B41J2/435—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of radiation to a printing material or impression-transfer material
  • B41J2/447—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of radiation to a printing material or impression-transfer material using arrays of radiation sources
  • B41J2/45—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of radiation to a printing material or impression-transfer material using arrays of radiation sources using light-emitting diode [LED] or laser arrays
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
  • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
  • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
  • B41J2/435—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of radiation to a printing material or impression-transfer material
  • B41J2/44—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of radiation to a printing material or impression-transfer material using single radiation source per colour, e.g. lighting beams or shutter arrangements
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
  • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
  • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
  • B41J2/435—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of radiation to a printing material or impression-transfer material
  • B41J2/447—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of radiation to a printing material or impression-transfer material using arrays of radiation sources
  • B41J2/455—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of radiation to a printing material or impression-transfer material using arrays of radiation sources using laser arrays, the laser array being smaller than the medium to be recorded
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
  • H04N1/024—Details of scanning heads ; Means for illuminating the original
  • H04N1/032—Details of scanning heads ; Means for illuminating the original for picture information reproduction
  • H04N1/036—Details of scanning heads ; Means for illuminating the original for picture information reproduction for optical reproduction
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
  • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
  • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
  • B41J2/435—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of radiation to a printing material or impression-transfer material
  • B41J2/447—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of radiation to a printing material or impression-transfer material using arrays of radiation sources
  • B41J2/45—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of radiation to a printing material or impression-transfer material using arrays of radiation sources using light-emitting diode [LED] or laser arrays
  • B41J2002/453—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of radiation to a printing material or impression-transfer material using arrays of radiation sources using light-emitting diode [LED] or laser arrays self-scanning

Definitions

• the present invention relates to an optical writing head, and more particularly to an optical writing head using a self-scanning light emitting element array.
• the optical printer head that is, the optical writing head, includes a light emitting element array in which light emitting elements are arranged in a line.
• a light emitting diode (LED) array is used to form an optical printer head as a light emitting element array, printing is performed on A3 size paper of 600 dpi (dots per inch).
• LED light emitting diode
• the optical writing head about 720 LEDs are arranged in a line.
• an electrode is extracted from each LED and electrically connected to the driving IC electrode. Wire bonding is typically used for the connection.
• an IC that drives n LEDs converts n serial data into n serial data, and then converts the data into parallel data based on the parallel data. Control the blinking of n LEDs.
• the number of signal lines extracted from the optical writing head is equal to the number of driving ICs, excluding the signal lines for power supply and timing related pulses.
• the number of signal lines is too large, by placing a specific driver IC that distributes data (serial-to-real-time conversion) to m driver ICs, In addition, the number of signal lines to be extracted can be reduced to 1 / m.
• the specific driving IC is taken out by serial-parallel conversion in the vicinity. Reduce the number of signal lines Otherwise, the interface with the outside could not be taken, so that a specific driver IC would be placed on the same substrate as the LED array, and the There was a problem that the width (width in the direction perpendicular to the LED array direction) became wide. In addition, there is a problem in that a specific drive IC dedicated to serial-parallel conversion must be built in the head, which is costly.
• the present inventors have focused on a light emitting device having a pnpn structure as a component of a light emitting device array, and have already applied for a patent (Japanese Patent Application Laid-Open No. Heisei 1 (1999)) to realize self-scanning of light emitting points.
• Japanese Patent Application Laid-Open No. 2-389662 Japanese Unexamined Patent Application Publication No. Hei 2 — 148584, Japanese Unexamined Patent Application Publication No. Hei 9-250650, Japanese Unexamined Patent Application Publication No. It has been shown that it is easy to mount as a light source for light sources, that the light emitting element pitch can be made fine, and that a compact light emitting element array can be manufactured.
• An object of the present invention is to provide an optical writing head capable of reducing the number of signal bus lines to be taken out by using a self-scanning light emitting element array. And there.
• the one-point lighting type self-scanning light emitting element array chip used in the optical writing head of the present invention has the following basic structure.
• the single-point lighting type self-scanning light-emitting element array chip has a three-dimensional transfer element having a control electrode for controlling a threshold voltage or a threshold current.
• the control electrodes of adjacent transfer elements are connected to each other by an electrically unidirectional element, Is connected to each control electrode of the transfer element via each load resistor, and one of the remaining two terminals of each transfer element is connected to an n-phase (n is an integer of 2 or more) clock.
• a transfer element array formed by sequentially connecting a pulse line to every n transfer elements.
• a large number of three-terminal light-emitting elements having control electrodes for controlling the threshold voltage or the threshold current are arranged one-dimensionally, and each control electrode of the transfer element is connected to a corresponding control electrode of the light-emitting element.
• a light-emitting element array formed by connecting a line to which a write signal is applied is connected to one of the remaining two terminals of each light-emitting element.
• a plurality of single-point self-running apricot-type light emitting element array chips having the above-described configuration are arranged one-dimensionally.
• Each chip is connected to a common start pulse 'no' and 'sine', each chip is connected to a two-phase clock pulse 'no' line and each chip is connected are connected to separate write signal bus lines.
• the first writing head is provided.
• a current-limiting resistor connected to the lusnoline, n-phase clock line, bus line, and write signal bus line is built into the chip.
• the phase limiting resistor is connected to an n-phase clock pulse bus line; It is built into the chip.
• the knocker IC is inserted into each of the n-phase clock noise and the noise line. Have been.
• a two-point lighting type self-scanning light emitting element chip is used.
• each chip is connected to a common single-pulse 'bus line', and each chip is connected to a common n-phase clock -no 'no' line.
• Each chip has Two separate write signal lines are connected, and the two write bus lines are connected to every other light emitting element in each chip.
• a self-scanning light emitting element array chip of a plurality of lighting types is used.
• a large number of three-terminal transfer elements with control electrodes for controlling the threshold voltage or threshold current are arranged one-dimensionally, and the control electrodes of adjacent transfer elements are electrically unidirectional.
• the power supply line is connected to each control electrode of the transfer element via each load resistor, and one of the remaining two terminals of each transfer element is connected to the n-phase (n A clock pulse line of integers of 2 or more) and a transfer element array formed by connecting the clock pulse lines in sequence for every n transfer elements via a current limiting resistor.
• a large number of three-terminal light emitting elements having control electrodes for controlling the threshold voltage or the threshold current are arranged one-dimensionally, and each control electrode of the light emitting element corresponds to every n transfer elements.
• a light-emitting element array formed by connecting a control signal to one of the remaining two terminals of each light-emitting element, and applying a signal for applying an input signal through a resistor;
• a separate start pulse bus line is connected to each chip, and each chip is connected to a separate start pulse bus line.
• a common n-phase clock pulse / nosline is connected, and a common current application nosline is connected to each chip.
• a seventh embodiment of the present invention is directed to an optical writing head using a one-point lighting type self-scanning light emitting element array chip, wherein each chip has m (m is an integer of 2 or more). ) Are connected in turn, and each chip is connected to a common n-phase clock noise 'no line, and the adjacent m chips are connected to each other.
• a separate write signal bus line is connected to each Resistors connected to the knoreless “no” line and the write signal bus line are built into the chip.
• an optical writing head using a single-point lighting type self-scanning light-emitting element array chip 3 ⁇ 4 several chips are adjacent to each other (m (m is an integer of 2 or more) into groups of chips.
• m is an integer of 2 or more
• the end-bonding pad of one chip is replaced by the chip of the next stage.
• the first chip in each group is connected to a common start pulse and nosline, and each chip is connected to a common n-phase.
• the bus lines are connected to each other, and separate write signal bus lines are connected to all the chips in the A group, respectively.
• a separate stripe pulse bus line is connected to every m adjacent chips (m is an integer of 2 or more), and the adjacent m M chips are connected to each other.
• the clock pulse 'no line' of the m-tree of a certain thread is connected in turn, and each chip is connected to the clock pulse 'no line of the other common phase.
• a window signal bus line is connected to each of the chips.
• FIG. 1 is a diagram showing the basic structure of a three-terminal light emitting device.
• FIG. 2 is an equivalent circuit diagram of the self-scanning light-emitting element array.
• FIG. 3 is a diagram illustrating an optical writing head according to the first embodiment of the present invention.
• FIGS. 4A and 4B are diagrams illustrating a single-point-lit SLED chip used in the first embodiment. You.
• FIG. 5 is a diagram showing an optical writing head which is Embodiment 2a of the present invention.
• FIGS. 6A and 6B are diagrams showing an SLED chip with a built-in resistor used in Example 2a.
• FIGS. 7A and 7B are diagrams showing an SLED chip with a built-in resistor used in Example 2b.
• FIG. 8 is a diagram showing an optical writing head that is Embodiment 2c of the present invention.
• FIG. 9 is a diagram showing an optical writing head according to the third embodiment of the present invention.
• FIGS. 10A and 10B show two-point lighting type S L used in the third embodiment.
• FIG. 11 is a diagram illustrating an optical writing head according to a fourth embodiment of the present invention.
• FIG. 12 is a diagram showing a multiple lighting type SLED chip used in the fourth embodiment.
• FIG. 13 is a diagram showing an optical writing head that is Embodiment 5 of the present invention.
• FIG. 14 is a diagram illustrating an example of a driving waveform according to the fifth embodiment.
• FIG. 15 is a diagram showing an optical writing head that is Embodiment 6 of the present invention.
• Figures 16A and 16B show the single-point lighting type S L used in Example 6.
• FIG. 17 is a diagram illustrating an example of a drive waveform according to the sixth embodiment.
• FIG. 18 is a diagram showing an optical writing head that is Embodiment 7 of the present invention.
• the self-scanning light-emitting element array uses a three-terminal light-emitting thyristor.
• Figure 1 shows the basic structure of a three-terminal light-emitting thyristor.
• a PNPN structure 12 is formed on a P-type GaAs substrate 10.
• the gate 14 of this three-terminal light emitting thyristor has the function of controlling the turn-on voltage and is added to the power source 16.
• the resulting turn-on voltage is the sum of the gate voltage plus the diffusion potential of the PN junction and the gate voltage. After turning on in the evening, the gate voltage becomes almost equal to the anode voltage. Thus, if node 18 is grounded, the gate voltage will be zero volts.
• FIG. 2 shows an equivalent circuit of the self-scanning light-emitting element array disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 2-266636, using such a three-terminal light emitting device.
• the self-scanning light-emitting element array includes ⁇ transfer element, T 2, T 3, ... array, and write light-emitting element L i of, L 2, L, a ... the array.
• These transfer elements and light-emitting elements are composed of three-terminal light-emitting thyristors.
• the gate electrodes of adjacent transfer elements are connected using diodes D 2 , D 3 , D 4 ,.
• the clock pulses ⁇ 1 and ⁇ 2 are alternately supplied to each force source electrode of the transfer element.
• VGA is a power supply (normally ⁇ 5 V), and is connected to the gate electrodes G 1, G 2 , G 2 ,... Of each transfer element via a load resistance RL.
• a shift register 8 is composed of these transfer elements T t, T 2 , T 3 ,..., Diodes D, D 2 , D 3,.
• the gate electrode of the transfer element is also connected to the gate electrode of the corresponding light emitting element.
• the first column of the transfer elements T gate one gate electrode of a star preparative pulse [Phi s is applied.
• a writing signal ⁇ is applied to the force source electrode of the writing light emitting element.
• gate electrodes G about - 5 volt der is, gate electrodes G 3 are about a 1 volt and ing. Therefore, the write voltage of the light emitting element L i is about 16 volts, and the write voltage of the light emitting element L 3 is about 12 volts. You. Now, voltage of the light-emitting element L 2 only write the write signal, - a 1 2 volt range. Emitting element L 2 is turned on and enters the ie emission state, intends voltage of the write signal E La y emission is fixed in about a 1 volt Bok striped Still other light emitting element emits light is selected It is not.
• the light emission intensity of the light emitting element is determined by the amount of current flowing in the write signal, and an image can be written at an arbitrary intensity. Also, in order to transfer the light emitting state to the next light emitting element, it is necessary to temporarily lower the voltage of the write signal line to zero, and to turn off the light emitting element at once. There is.
• the self-scanning light-emitting element is formed as a semiconductor chip in which a certain number of transfer elements and light-emitting elements are integrated.
• An element array chip is formed, and the self-scanning light-emitting element array is arranged, for example, in a line to form a self-scanning light-emitting element array of a predetermined size.
• FIG. 3 a 600 dpi / 128 emission point / single point lighting type (one light emitting element lights up at the same time) self-scanning light emitting element array (abbreviated as SLED) chip
• SLED self-scanning light emitting element array
• FIG. 4 SLED Chi-up shown in B is 1 2 8 transfer elements ⁇ ⁇ ⁇ ⁇ 128, 1 2 8 pieces of writing light emitting elements L ⁇ L 128 or et ing.
• the shift register configuration uses a diode connection for the connection between the gates of adjacent transfer elements.
• VGA is a power supply and is connected to the gate electrode of each transfer element via a load resistor. Further, the gate electrode of the transfer element is also connected to the gate electrode of the corresponding light emitting element.
• Transfer element T ! A start pulse ⁇ s is applied to the gate electrode of each of the electrodes, and a clock pulse ⁇ 1, ⁇ 2 for transfer is alternately applied to the force source electrode of the transfer element, and the power source of the write light emitting element is applied.
• a write signal ⁇ is applied to the electrodes.
• V GA, ⁇ s, ⁇ , Bondi use Nguno head 3 0, 3 2, 3 4,
• the ⁇ , bonding pad 38 of each SLED chip is supplied with a write signal ⁇ , (1) to ⁇ , (5) via an external current limiting resistor R, which is provided externally. It is connected to the corresponding ⁇ , (1) to ⁇ , (56) terminals of the connector 20 through the bus line for 6).
• each SLED chip starts the transfer operation at the same time because the same start pulse ⁇ s is given.
• the light emission intensity of one light emitting element lit by each SLED chip is determined by the write signals ⁇ , (1) to ⁇ , (56) given to each SLED chip, respectively. .
• the optical writing head with the above configuration is taken out from the chip and distributed.
• the number of lines is SSIS 'VGA'! (1) to ⁇ , (56), plus the wiring for the grounding pad (not shown), and a total of 61 wires. It is.
• the number of wirings is extremely small as compared with the wiring of conventional optical writing heads using LED arrays.
• the current limit resistor Rl, R2, Rs, R which is externally attached to the optical write head of FIG. Is.
• FIGS. 6A and 6B show the SLED chip used in this embodiment.
• the SLED chip has built-in current limiting resistors R1, R2, Rs, and R. These resistors, [Phi 1 La Lee down 4 0, [Phi 2 La Lee emissions 4 2, [Phi 3 La y down 4 6, are ⁇ , respectively it La Lee emissions 4 8.
• the number of bonding pads of one chip is the same as in Example 1 as shown in FIG.
• an optical write head using only SLED chips can be realized as an electrical component, and a narrower optical write head can be realized. Is realized.
• an SLED chip including only current limiting resistors Rl and R2 is used instead of the SLED chip of the embodiment 2a.
• Figures 7A and 7B show the SLED chips used in this example.
• resistors R 1 and R 2 are inserted into ⁇ 1 line 40 and ⁇ 2 line 42 respectively; 3 lines 46, ⁇ and line 48 have current No limiting resistor is inserted.
• the ⁇ , (1) to ⁇ , (56) terminals of the connector 20 are driven by the current source.
• the anode-to-cathode voltage of the on-state thyristor is almost equal to the forward voltage of the PN junction, regardless of the current.
• FIG. 8 shows the optical writing head of this embodiment.
• Nos. IC 61 and 62 are inserted in the ⁇ 1, ⁇ 2 and 'lines of the optical writing head of the embodiment 2b.
• the reason why the insert of the insert IC is performed is as follows. That is, when a current of about 5 mA flows through each of the ⁇ 1 and ⁇ 2 lines of the SLED chip, the ⁇ 1 nosline 26 and ⁇ 2 nosla The current flowing through each of the pins 24 is as high as 300 mA. If a large current is interrupted, unwanted radiation may occur, causing electromagnetic interference. By inserting the knocker IC into the noise line, it is possible to prevent the generation of undesired radiation due to the interruption of a large current.
• a voltage higher or lower than the threshold of the notch IC can be applied to the ⁇ 1 and ⁇ 2 terminals of the connector 20.
• This example is composed of a series of 56 self-scanning light emitting element arrays of 600 dpi / 128 light emitting points with built-in resistors and two lighting points (two light emitting elements are turned on at the same time). This is an A3 size optical writing head.
• FIG. 9 shows the configuration of the optical writing head
• FIGS. 10A and 10B show the SLED chips used in this embodiment.
• the SLED chips shown in FIGS. 10A and 10B further have a write signal ⁇ ,; in addition to the write signal ⁇ , in the SLED chip of FIG.
• a current limiting resistor R j is inserted in the ⁇ j line 49.
• the write signals ⁇ ,, ⁇ _; are connected alternately to the light-emitting elements. As a result, two light-emitting elements can be turned on simultaneously within one chip, and the duty ratio of the write signal increases, thereby increasing the effective light amount.
• the number of transfer clock bus lines may be three or more, and the number of write signal bus lines may be three or more.
• This embodiment is for A3 size, which is composed of 56 self-scanning light emitting element array chips of 600 dpi / 128 light emitting points / multiple lighting type (several light emitting elements are lit at the same time). Write head.
• FIG. 11 shows a configuration of a write head
• FIG. 12 shows an SLED chip used in this embodiment.
• the source electrodes of the transfer element T are connected to the ⁇ 1, ⁇ 2 lines 40, 42 via the current limiting resistors 70, 72.
• the light emitting element L Each force source electrode is connected to ⁇ , line 48 via a current limiting resistor 74.
• These current limiting resistors 71, 72, and 73 are integrated in the chip.
• Each gate electrode of the light emitting element L is connected to a gate electrode of the transfer element T to which the clock pulse ⁇ 1 is input.
• transfer click lock bus line is rather good even three or more phases, also [Phi s Basurai emissions may also be provided three or more.
• FIG. 13 shows the optical writing head of this embodiment.
• the storage time is reduced to ⁇ 3 (1) as shown in FIG. Roh scan La Lee down 2 8 (1) and ⁇ s (2) Bruno scan La Lee down 2 8 2 (2) is provided, ⁇ s (1) Basurai down 2 8 (1) the SLED 1, SLED 3, Connect to SLED 5 '"and connect the ⁇ 8 (2) nosline to SLED 2, SLED 4,....
• the number of write signals ⁇ , in the optical write head of FIG. 5 is halved, that is, ⁇ , (1) to ⁇ , (28), and the same write signal is set for every two adjacent chips. To give.
• the number of bus lines to be taken out is ⁇ 8 (1), ⁇ 3 (2), ⁇ 1, ⁇ 2, VGA , ⁇ , (1) to ⁇ ! Add a ground bus line (not shown) to the (28) bus line. The total was 34.
• FIG. 14 shows an example of a signal waveform of the write head of FIG. Odd numbered SLED Chi Tsu Punisu evening one preparative Roh pulse ⁇ ⁇ (1) is even-numbered SLED chip Punisu terpolymers Toparusu [Phi 3 (2) is given, 2 adjacent pieces of SLED Chi Tsu each flop It can be seen that the write signals ⁇ , (1),, (2), ⁇ , (3).
• the number of transfer clock / noslines may be three or more, and three or more ⁇ s bus lines may be provided.
• FIG. 15 shows the optical writing head of this embodiment.
• Example 2 a of SLED Chi-up (Fig. 5) the final coupling die Hauts de D 128 forces saw de the et down de Bondy down Diagnostics head of ( end )
• the chip taken out as 37 the ⁇ end bonding pad 37 of the (2N-1) th chip is replaced by the ⁇ s bonding pad of the 2Nth chip.
• the start pulse ⁇ s is connected to the (2N-1) th SLED chip.
• Shi number is, ⁇ 3, ⁇ 1, ⁇ 2, V GA, ⁇ , (1) ⁇ ⁇ , to the bus La Lee emissions of (2 8), Roh slide down (Figure for Gras down de (Not shown)), for a total of 33.
• FIG. 16A and FIG. 16B show a bonding pad and a circuit of such an SLED chip. Rereru the manner in which the power source de final of the coupling die Hauts de D 128 was out Ri taken as a ⁇ end Bondi Ngupa head 3 7 shows.
• FIG. 17 shows an example of a signal waveform of the optical writing head of FIG. As is clear from comparison with the signal waveform of FIG. 14, the light emitting operation of the light emitting element is the same as that of the fifth embodiment.
• the transfer clock bus line may have three or more phases, and connect ⁇ end bonding pad 37 and ⁇ s bonding pad 36. A set of three or more chips may be used.
• the ⁇ 1 nosline increases to two ⁇ 1 (1) bus lines and a ⁇ 1 (2) bus line, and the start pulse line is s (1) bus line to ⁇ s (2 8) It is reduced to 28 noslines. It was but connexion, Basurai emissions that are issued can pull from SLED chip is, ⁇ 1 (1): ⁇ 1 (2), ⁇ 2, V GA, ⁇ ,, ⁇ 3 (1) ⁇ ⁇ 3 (2 8) A total of 34 buses were added to the bus lines, plus the ground bus lines.
• the transfer clock bus line may have three or more phases, and the ⁇ 1 nosle line may have three or more lines.
• optical writing head of this embodiment data indicating the light-emitting elements to be turned on at the same time is written in advance in the shift register, and turned on simultaneously by a write signal.
• an optical writing head capable of reducing the number of signal lines taken out of an SLED chip by using a self-scanning light emitting element array. Can be done.

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• Physics & Mathematics (AREA)
• Optics & Photonics (AREA)
• Health & Medical Sciences (AREA)
• General Health & Medical Sciences (AREA)
• Toxicology (AREA)
• Engineering & Computer Science (AREA)
• Multimedia (AREA)
• Signal Processing (AREA)
• Led Devices (AREA)
• Printers Or Recording Devices Using Electromagnetic And Radiation Means (AREA)

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• 2000
  • 2000-05-24 JP JP2000152913A patent/JP4362946B2/ja not_active Expired - Lifetime
  • 2000-12-26 EP EP00985870A patent/EP1199180A4/en not_active Withdrawn
  • 2000-12-26 US US09/936,118 patent/US6747940B2/en not_active Expired - Lifetime
  • 2000-12-26 CA CA002366990A patent/CA2366990A1/en not_active Abandoned
  • 2000-12-26 CN CNB008026300A patent/CN1299367C/zh not_active Expired - Fee Related
  • 2000-12-26 WO PCT/JP2000/009207 patent/WO2001049502A1/ja not_active Ceased
  • 2000-12-26 KR KR1020017011337A patent/KR100804436B1/ko not_active Expired - Lifetime
• 2001
  • 2001-01-03 TW TW090100124A patent/TW474037B/zh not_active IP Right Cessation

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