WO2000044042A1 - Procede pour la formation galvanique de structures conductrices en cuivre de grande purete lors de la fabrication de circuits integres - Google Patents

Procede pour la formation galvanique de structures conductrices en cuivre de grande purete lors de la fabrication de circuits integres Download PDF

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Publication number
WO2000044042A1
WO2000044042A1 PCT/DE2000/000133 DE0000133W WO0044042A1 WO 2000044042 A1 WO2000044042 A1 WO 2000044042A1 DE 0000133 W DE0000133 W DE 0000133W WO 0044042 A1 WO0044042 A1 WO 0044042A1
Authority
WO
WIPO (PCT)
Prior art keywords
copper
compounds
bath
semiconductor substrates
deposition
Prior art date
Application number
PCT/DE2000/000133
Other languages
German (de)
English (en)
Inventor
Heinrich Meyer
Andreas Thies
Original Assignee
Atotech Deutschland Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE19915146A external-priority patent/DE19915146C1/de
Priority to AU31435/00A priority Critical patent/AU3143500A/en
Priority to EP00908927A priority patent/EP1153430B1/fr
Priority to US09/831,763 priority patent/US6793795B1/en
Priority to AT00908927T priority patent/ATE282248T1/de
Priority to JP2000595378A priority patent/JP3374130B2/ja
Application filed by Atotech Deutschland Gmbh filed Critical Atotech Deutschland Gmbh
Priority to KR10-2001-7009124A priority patent/KR100399796B1/ko
Priority to BR0007639-2A priority patent/BR0007639A/pt
Priority to DE50008594T priority patent/DE50008594D1/de
Priority to CA002359473A priority patent/CA2359473A1/fr
Publication of WO2000044042A1 publication Critical patent/WO2000044042A1/fr
Priority to HK02100957.9A priority patent/HK1039683B/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition

Definitions

  • the invention relates to a method for the galvanic formation of conductor structures made of high-purity copper, for example of conductor tracks, through holes, connection contacts and connection points, on recessed surfaces of semiconductor substrates (wafers) in the production of integrated circuits, in particular in cases in which the recesses have a high aspect ratio.
  • So-called silicon planar technology in which epitaxy and doping processes are used, is used to manufacture integrated circuits.
  • single-crystalline silicon wafers so-called wafers, are processed with physical methods in order to form differently conductive areas on the silicon surface in the micrometer and for some time now also in the sub-micrometer range (currently 0.25 ⁇ m).
  • the manufacturing process can be divided into three stages:
  • the transistors are generally contacted by multilayer metallization and connected to one another, the dielectric silicon dioxide being usually used to isolate the conductor tracks formed for this purpose.
  • connection contact holes and the connection locations a generally 1 ⁇ m thick aluminum layer has long been applied using physical methods, for example a vapor deposition (electron beam evaporation) or a sputtering process. This is subsequently structured using suitable etching processes using a photoresist.
  • a vapor deposition electron beam evaporation
  • a sputtering process This is subsequently structured using suitable etching processes using a photoresist.
  • Aluminum is described in the older literature as the cheapest alternative of the available materials for producing the conductor tracks, connection contacts and connection locations. For example, requirements for this layer are given in "Integrated Bipolar Circuits" by H.-M.Rein and R.Ranfft, Springer-Verlag, Berlin, 1980. The problems mentioned there are minimized by certain process optimizations, but cannot be completely avoided.
  • the depressions ie the holes and trenches
  • a diffusion barrier usually titanium nitride, tantalum or tantalum nitride
  • a conductive layer mostly sputtered copper
  • the depressions are galvanically filled with the so-called trench-filling process. Since the copper is deposited over the entire surface, the excess must be subsequently removed again at the undesired points. This is done with the so-called CMP process (chemical mechanical polishing). Repetition of the process, ie repeated application of the dielectric (for example silicon dioxide) and formation of the depressions by etching, can produce multilayer circuits.
  • the dielectric for example silicon dioxide
  • each anode change leads to contamination of the bath by detaching impurities from the anodes (anode sludge). This also means that a longer training period after refilling the anode is required.
  • the present invention is therefore based on the problem of avoiding the disadvantages of the known methods and, in particular, of minimizing the increased contamination of the copper coatings obtained using the cheaper, insoluble anodes.
  • the problems that arise from the addition of the copper salts in the deposition solution are to be solved. Avoiding the dishing problem is also very important.
  • the method according to the invention for the galvanic formation of conductor structures from high-purity copper on the semiconductor substrates (wafers) in the manufacture Provision of integrated circuits comprises the following essential process steps:
  • the copper plating bath contains at least one copper ion source, at least one additive compound for controlling the physical-mechanical properties of the copper layers and Fe (II) and / or Fe (III) compounds, and ii. wherein an electrical voltage is applied between the wafers and dimensionally stable, insoluble in the bath and brought into contact with it, so that an electrical between the wafers and the counter electrodes
  • the depressions generally have a width or a diameter of 0.15 ⁇ m to 0.5 ⁇ m. Their depth is usually about 1 ⁇ m.
  • the copper layers obtained by production using the method according to the invention are in the case of depressions with larger lateral dimensions Contrary to the known methods at the leading edges to the wells to be metallized just as thick as on the side walls and at the bottom of the wells.
  • the copper layer largely follows the surface contour of the wafer surface. This avoids the disadvantage that the cross section of the depressions at the upper edge is already completely filled with copper, while there is still a deposition solution in the lower region of the depressions.
  • the problems associated with such electrolyte inclusion for example explosive escape of the enclosed liquid when the circuit is heated, diffusion of impurities through the copper, are thereby completely avoided.
  • a metal structure evenly filled with copper is obtained, which meets the usual requirements that exist in the manufacture of integrated circuits.
  • a pulse current or pulse voltage method is preferably used.
  • the current between the workpieces polarized as the cathode and the anodes is set galvanostatically and modulated in time using suitable means.
  • a voltage between the wafers and the counter electrodes (anodes) is set potentiostatically and the voltage is modulated over time, so that a current that changes over time is set.
  • the method known from the art as a reverse pulse method is preferably used with bipolar pulses.
  • the bipolar pulses consist of a sequence of cathodic pulses lasting 20 milliseconds to 100 milliseconds and anodic pulses lasting 0.3 milliseconds to 10 milliseconds.
  • the peak current of the anodic pulses is set to at least the same value as the peak current of the cathodic pulses.
  • the peak current of the anodic pulses is preferably set two to three times as high as the peak current of the cathodic pulses.
  • a method for producing a full-surface, high-purity copper layer on semiconductor substrates (wafers) provided with depressions is also provided, in which the above method steps a. and b. be performed.
  • a structuring of the copper layer according to process step c. does not apply in this case.
  • the aforementioned advantages also apply to the production of a full-surface copper layer, since conductor structures can be produced from it without any problems using known methods.
  • the bath used for copper deposition also contains at least one substance for increasing the electrical conductivity of the bath, for example sulfuric acid, methanesulfonic acid, pyrophosphoric acid , Fluoroboric acid or amidosulfuric acid.
  • at least one substance for increasing the electrical conductivity of the bath for example sulfuric acid, methanesulfonic acid, pyrophosphoric acid , Fluoroboric acid or amidosulfuric acid.
  • Sulfuric acid conc. 50 - 350 g / 1, preferably 180 - 280 g / 1 or 50 - 90 g / 1.
  • a chloride for example sodium chloride or hydrochloric acid, may also be present in the deposition solution. Their typical concentrations are given below:
  • Chloride ions (added, for example, as NaCl) 0.01-0.18 g / 1, preferably 0.03-0.10 g / 1.
  • the bath according to the invention contains at least one additive compound for controlling the physical-mechanical properties of the copper layers.
  • Suitable additive compounds are, for example, polymeric oxygen-containing compounds, organic sulfur compounds, thiourea compounds and polymeric phenazonium compounds.
  • the additive compounds are contained in the deposition solution within the following concentration ranges:
  • Typical polymeric oxygen-containing compounds 0.005-20 g / 1, preferably 0.01-5 g / 1, conventional water-soluble organic sulfur compounds 0.0005-0.4 g / 1, preferably 0.001-0.15 g / 1.
  • Octanol polyalkylene glycol ether Oleic acid polyglycol ester polyethylene propylene glycol polyethylene glycol polyethylene glycol dimethyl ether polyoxypropylene glycol polypropylene glycol polyvinyl alcohol stearic acid polyglycol ester stearyl alcohol polyglycol ether ß-naphthol polyglycol ether
  • Table 2 shows various sulfur compounds with suitable functional groups for generating water solubility.
  • Ethylene dithiodipropyl sulfonic acid sodium salt bis (p-sulfophenyl) disulfide, disodium salt
  • Thiourea compounds and polymeric phenazonium compounds as additive compounds are used in the following concentrations: 0.0001-0.50 g / l, preferably 0.0005-0.04 g / l.
  • Fe (II) and / or Fe (III) compounds are additionally present in the bath.
  • concentration of these substances is given below:
  • Suitable iron salts are iron (II) sulfate heptahydrate and iron (III) sulfate nonahydrate, from which the effective Fe 2 7Fe 3+ redox system is formed after a short operating time. These salts are ideally suited for aqueous, acidic copper baths. Other water-soluble iron salts can also be used, for example iron perchlorate. Salts which do not contain any biodegradable or hard-to-decompose (hard) complexing agents are advantageous, since these can cause problems in the rinsing water disposal (for example iron ammonium alum).
  • No soluble copper anodes are used as anodes, but dimensionally stable, insoluble anodes.
  • a constant distance between the anodes and the wafers can be set.
  • the geometric shape of the anodes can be easily adapted to the wafers and, in contrast to soluble anodes, practically does not change their external geometrical dimensions.
  • the distance between the anodes and the wafers which influences the layer thickness distribution on the surface of the wafers remains constant.
  • materials that are resistant to the electrolyte such as stainless steel or lead, are used.
  • Anodes are preferably used which contain titanium or tantalum as the base material, which is preferably coated with noble metals or oxides of the noble metals. Platinum, iridium or ruthenium and the oxides or mixed oxides of these metals are used, for example, as the coating. In addition to platinum, iridium and ruthenium, rhodium, palladium, osmium, silver and gold or their oxides and mixed oxides can in principle also be used for the coating. A particularly high resistance to the electrolysis conditions could be observed, for example, on a titanium anode with an iridium oxide surface, which was irradiated with fine particles, for example spherical bodies, and thereby compacted without pores.
  • anodes which consist of noble metals, for example platinum, gold or rhodium or alloys of these metals.
  • other inert, electrically conductive materials such as carbon (graphite) can also be used.
  • a voltage is applied between the semiconductor substrate and the anode, the voltage being chosen so that an electrical current of 0.05 A to 20 A, preferably 0.2 A to 10 A and in particular 0.5 A to 5 A, flows per dm 2 semiconductor substrate surface.
  • the copper ions consumed during the deposition from the deposition solution cannot be supplied directly by dissolution by the anodes, they are supplemented by chemical dissolution of corresponding copper parts or shaped articles containing copper. Due to the oxidizing effect of the Fe (III) compounds contained in the deposition solution, copper ions are formed from the copper parts or shaped bodies in a redox reaction. To supplement the copper ions consumed by deposition, a copper ion generator is therefore used which contains parts made of copper. In order to regenerate the deposition solution, which is depleted due to the consumption of copper ions, it is led past the anodes, with Fe (III) compounds forming from the Fe (II) compounds. The solution is then passed through the copper ion generator and brought into contact with the copper parts.
  • the Fe (III) compounds react with the copper parts to form copper ions, ie the copper parts dissolve. At the same time, the Fe (III) compounds are converted into the Fe (Il) compounds.
  • the total concentration of the copper ions contained in the deposition solution is kept constant. From the copper ion generator, the deposition solution returns to the electrolyte space that is in contact with the wafers and the anodes.
  • the wafers are usually held horizontally for copper deposition. Care is taken to ensure that the back of the wafer does not come into contact with the deposition solution.
  • Anodes in the deposition bath also held horizontally, are arranged directly opposite the wafers.
  • the method according to the invention is particularly suitable for forming conductor tracks, connection contacts and connection locations in depressions lying on the surfaces of wafers.
  • the former In order to be able to galvanically deposit a copper layer on the dielectric surface of the silicon dioxide layer, the former must first be made electrically conductive. Suitable precautions must also be taken to prevent the diffusion of copper atoms into the underlying silicon.
  • a nitride layer for example tantalum nitride layer
  • a sputtering process for example a nitride layer (for example tantalum nitride layer) is therefore formed using a sputtering process.
  • the base metal layer is then produced, which forms an electrically conductive basis for the subsequent galvanic metallization.
  • a preferably 0.02 ⁇ m to 0.3 ⁇ m thick, full-area layer is produced as the base metal layer, preferably using a physical metal deposition process and / or a CVD process and / or a PECVD process.
  • an electroplating process for example a metal deposition process without external current, can also be used.
  • a base metal layer made of copper can be deposited.
  • Other conductive layers, preferably metal layers, are also suitable.
  • the approximately 1 ⁇ m thick copper layer is then electrodeposited using the method described above.
  • this layer can also be thinner or thicker, for example from 0.2 ⁇ m to 5 ⁇ m.
  • the structure of the conductor tracks, connection contacts and connection slots is transferred.
  • Conventional structuring methods can be used for this.
  • the copper layer formed can be coated with a resist layer and subsequently exposed again by removing the resist layer at those points where no conductor tracks, connection contacts or connection locations are to be formed. Finally, the copper layer in the exposed areas is removed.
  • Damascene copper metallization copper is deposited in particular in the trench-like or hole-like depressions and is deposited on the surface of the wafer outside the Deposited copper is selectively removed using a polishing process based on mechanical and chemical methods (CMP process).
  • CMP process mechanical and chemical methods
  • a wafer provided with trenches (vias) was first covered with a diffusion barrier made of tantalum nitride and then with an approximately 0.1 ⁇ m thick copper layer, both of which were formed using a sputtering process.
  • a copper deposition bath with the following composition was used:
  • the copper was deposited under the following conditions:
  • the coating result is shown by means of cross sections through the wafer 1 in FIG. 1, which has depressions 2 filled with copper 3 with different widths D before a CMP process is carried out.
  • the surfaces of the raised areas on the wafer 1 are also coated with the copper layer 3.
  • the copper layer thickness d over the depressions 2 is surprisingly larger than over the raised areas on the wafer 1. It is therefore not very expensive to achieve a flat surface of the wafer 1 using the CMP method.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electroplating And Plating Baths Therefor (AREA)
  • Chemically Coating (AREA)

Abstract

L'invention concerne un procédé pour la formation galvanique de structures conductrices en cuivre de grande pureté sur des surfaces de substrats semi-conducteurs (plaquettes) (1) pourvues de creux (2) lors de la fabrication de circuits intégrés. Le procédé selon l'invention comporte les étapes suivantes: a. application sur les surfaces pourvues de creux (2) des substrats semi-conducteurs (1) d'une couche métallique de base sur toute la surface afin d'obtenir une conduction suffisante pour le dépôt galvanique; b. dépôt de surface de couches de cuivre (3) à épaisseur homogène sur la couche métallique de base au moyen d'un procédé de dépôt métallique galvanique par mise en contact des substrats semi-conducteurs avec un bain de dépôt cuivreux, le bain de dépôt cuivreux contenant au moins une source d'ions de cuivre, au moins un composé d'addition servant à commander les propriétés physico-mécaniques des couches de cuivre ainsi que des composés Fe(II) ou Fe(III), et une tension électrique étant appliquée entre les substrats semi-conducteurs et des contre-électrodes à dimension stable, non solubles dans le bain et mises en contact avec lui de sorte qu'un courant électrique circule entre les substrats semi-conducteurs (1) et les contre-électrodes; c. structuration de la couche de cuivre (3).
PCT/DE2000/000133 1999-01-21 2000-01-11 Procede pour la formation galvanique de structures conductrices en cuivre de grande purete lors de la fabrication de circuits integres WO2000044042A1 (fr)

Priority Applications (10)

Application Number Priority Date Filing Date Title
CA002359473A CA2359473A1 (fr) 1999-01-21 2000-01-11 Procede de constitution par electrolyse de structures de conducteurs a partir de cuivre tres pur, lors de la fabrication de circuits integres
EP00908927A EP1153430B1 (fr) 1999-01-21 2000-01-11 Procede pour la formation galvanique de structures conductrices en cuivre de grande purete lors de la fabrication de circuits integres
US09/831,763 US6793795B1 (en) 1999-01-21 2000-01-11 Method for galvanically forming conductor structures of high-purity copper in the production of integrated circuits
AT00908927T ATE282248T1 (de) 1999-01-21 2000-01-11 Verfahren zum galvanischen bilden von leiterstrukturen aus hochreinem kupfer bei der herstellung von integrierten schaltungen
JP2000595378A JP3374130B2 (ja) 1999-01-21 2000-01-11 集積回路製造に際し高純度銅から成る導体構造を電解形成するための方法
AU31435/00A AU3143500A (en) 1999-01-21 2000-01-11 Method for galvanically forming conductor structures of high-purity copper in the production of integrated circuits
KR10-2001-7009124A KR100399796B1 (ko) 1999-01-21 2000-01-11 집적회로 제조시 고순도 구리의 도체 구조를 전해적으로형성시키는 방법
BR0007639-2A BR0007639A (pt) 1999-01-21 2000-01-11 Processo para formação galvânica de estruturas condutoras de cobre de alta pureza na produção de circuitos integrados
DE50008594T DE50008594D1 (de) 1999-01-21 2000-01-11 Verfahren zum galvanischen bilden von leiterstrukturen aus hochreinem kupfer bei der herstellung von integrierten schaltungen
HK02100957.9A HK1039683B (zh) 1999-01-21 2002-02-07 在集成電路的製造中電化學形成高純度銅導體的方法

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
DE19903178 1999-01-21
DE19903178.9 1999-01-21
DE19915146.6 1999-03-26
DE19915146A DE19915146C1 (de) 1999-01-21 1999-03-26 Verfahren zum galvanischen Bilden von Leiterstrukturen aus hochreinem Kupfer bei der Herstellung von integrierten Schaltungen

Publications (1)

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WO2000044042A1 true WO2000044042A1 (fr) 2000-07-27

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PCT/DE2000/000133 WO2000044042A1 (fr) 1999-01-21 2000-01-11 Procede pour la formation galvanique de structures conductrices en cuivre de grande purete lors de la fabrication de circuits integres

Country Status (11)

Country Link
US (1) US6793795B1 (fr)
EP (1) EP1153430B1 (fr)
JP (1) JP3374130B2 (fr)
CN (1) CN1137511C (fr)
AT (1) ATE282248T1 (fr)
AU (1) AU3143500A (fr)
BR (1) BR0007639A (fr)
CA (1) CA2359473A1 (fr)
HK (1) HK1039683B (fr)
TW (1) TW464989B (fr)
WO (1) WO2000044042A1 (fr)

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CN100431106C (zh) * 2005-09-26 2008-11-05 财团法人工业技术研究院 形成纳米碳管与金属复合材料的电镀互连导线的方法
KR101335480B1 (ko) * 2006-03-30 2013-12-02 아토테크 도이칠란드 게엠베하 홀 및 캐비티를 금속으로 충전하기 위한 전기분해 방법
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US20110056838A1 (en) * 2009-09-04 2011-03-10 Ibiden, Co., Ltd. Method of manufacturing printed wiring board
EP2392694A1 (fr) 2010-06-02 2011-12-07 ATOTECH Deutschland GmbH Procédé de gravure de cuivre et alliages de cuivre
US8973538B2 (en) * 2010-06-18 2015-03-10 Caterpillar Inc. Inline engine having side-mounted heat exchangers
US20120024713A1 (en) 2010-07-29 2012-02-02 Preisser Robert F Process for electrodeposition of copper chip to chip, chip to wafer and wafer to wafer interconnects in through-silicon vias (tsv) with heated substrate and cooled electrolyte
WO2012103357A1 (fr) 2011-01-26 2012-08-02 Enthone Inc. Procédé permettant de combler des trous d'interconnexion en microélectronique
US8970043B2 (en) * 2011-02-01 2015-03-03 Maxim Integrated Products, Inc. Bonded stacked wafers and methods of electroplating bonded stacked wafers
CN103179806B (zh) * 2011-12-21 2019-05-28 奥特斯有限公司 组合的通孔镀覆和孔填充的方法
CN103290438B (zh) * 2013-06-25 2015-12-02 深圳市创智成功科技有限公司 用于晶圆级封装的电镀铜溶液及电镀方法
CN103668356B (zh) * 2013-12-17 2016-04-13 上海交通大学 在铜互连硫酸铜镀液中添加Fe2+和Fe3+的电镀方法

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Publication number Priority date Publication date Assignee Title
EP1325972A1 (fr) * 2000-10-10 2003-07-09 LEARONAL JAPAN Inc. Cuivrage electrolytique a anode insoluble
EP1325972A4 (fr) * 2000-10-10 2007-01-24 Shipley Co Llc Cuivrage electrolytique a anode insoluble
JP2003183875A (ja) * 2001-10-02 2003-07-03 Shipley Co Llc 基体上に金属層を堆積させるためのメッキ浴および方法
JP2009149995A (ja) * 2001-10-02 2009-07-09 Rohm & Haas Electronic Materials Llc 基体上に金属層を堆積させるためのメッキ浴および方法
JP4651906B2 (ja) * 2001-10-02 2011-03-16 ローム・アンド・ハース・エレクトロニック・マテリアルズ，エル．エル．シー． 基体上に金属層を堆積させるためのメッキ浴および方法
EP1475463A2 (fr) * 2002-12-20 2004-11-10 Shipley Company, L.L.C. Composition et méthode pour placage électrolytique utilisant de courant pulsé inversé
EP1475463A3 (fr) * 2002-12-20 2006-04-12 Shipley Company, L.L.C. Composition et méthode pour placage électrolytique utilisant de courant pulsé inversé

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JP3374130B2 (ja) 2003-02-04
EP1153430B1 (fr) 2004-11-10
CA2359473A1 (fr) 2000-07-27
CN1337064A (zh) 2002-02-20
US6793795B1 (en) 2004-09-21
HK1039683B (zh) 2005-05-06
BR0007639A (pt) 2001-11-06
TW464989B (en) 2001-11-21
JP2002535494A (ja) 2002-10-22
AU3143500A (en) 2000-08-07
EP1153430A1 (fr) 2001-11-14
ATE282248T1 (de) 2004-11-15
CN1137511C (zh) 2004-02-04
HK1039683A1 (en) 2002-05-03

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