Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/3017—Runtime instruction translation, e.g. macros
  • G06F9/30178—Runtime instruction translation, e.g. macros of compressed or encrypted instructions
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F9/3802—Instruction prefetching
  • G06F9/3814—Implementation provisions of instruction buffers, e.g. prefetch buffer; banks

Definitions

• the invention relates to a method for controlling functional units in a processor, in which in a configuration a sequence of primary instruction words originating from a translation of a program code is compressed from several instruction word parts and stored as a sequence of associated program words. In a subsequent execution phase, successive secondary instruction words from several instruction word parts are generated from the sequence of program words in the full instruction word width required to control all functional units.
• the invention also relates to a processor arrangement for carrying out the method with functional units, an instruction word memory assigned to these functional units and an instruction word buffer for storing instruction words which have already been generated and which have a width which is at least equal to the bit width of the secondary instruction word.
• Processor arrangements of the type mentioned at the beginning contain functional units which work in parallel with one another and which are controlled by an instruction word for each cycle.
• the respective instruction word is obtained from a program word which is taken from a program memory.
• the instruction words in turn consist of several instruction word parts, one instruction word part serving to control one functional unit each.
• the program words are compiled from structuring primary words in such a way that secondary instruction words can subsequently be created from them by writing a once generated secondary instruction word (VLIW) into an instruction word memory and contributing to the generation of the next secondary instruction word only the instruction word parts that differ from the stored secondary instruction word to the secondary instruction word to be generated are exchanged for the stored secondary instruction word.
• VLIW secondary instruction word
• the program word only needs to contain the information as to which instruction word part differs and with what content it differs. This makes it possible to make the program words very narrow and thus save storage space.
• the width of the program word must be increased if these larger differences occur frequently, which has the disadvantage of a larger storage space, or the differences are to be distributed over several program words.
• the secondary instruction word consists of several program words over several bars to manufacture. This creates the disadvantage of a greater expenditure of time.
• the invention is therefore based on the object of increasing the operating speed in an application-specific manner while maintaining a small program word width.
• a program word is a first identifier of a primary instruction word from a first group of previous primary instruction words, which has the greatest correspondence with the primary instruction word associated with the program word, and instruction word parts which contain the primary instruction word belonging to the program word distinguishing primary instruction word belonging to the identifier contains.
• a second group of secondary instruction words corresponding to the number of the first group is stored, each provided with a second identifier.
• a secondary instruction word corresponding to the associated primary instruction word from the second group is determined via the associated second identifier and the secondary instruction word corresponding to the program word is generated by exchanging the instruction word parts contained in the program word in the secondary instruction word .
• the program words can be constructed in such a way that they contain only the least possible information for the later generation of a secondary instruction word in the execution phase. This is achieved by using the previous primary instruction words that have the greatest match with the primary instruction word to be configured. Since the secondary instruction words are to be generated in the same width and in the same order as the primary instruction words in the execution phase, the implementation phase practically reverse order to the configuration phase and in each case an already generated secondary instruction word, which corresponds to the primary instruction word that is most similar in the configuration phase to a current primary instruction word, is used to generate a new secondary instruction word. Since the instruction word with the greatest similarity or the greatest match is always used, the amount of information required to generate a new secondary instruction word can be kept as small as possible. The memory requirement of a program memory can thus be minimized.
• the first group consists of a first number of primary instruction words immediately preceding the respective primary instruction word.
• the second group consists of a second number of secondary instruction words which is at least equal to the first number, with each secondary instruction word being added last to the group before the generation of the next secondary instruction word and the secondary instruction word added above the second number being removed from the second group.
• the group thus always consists of the immediately preceding instruction words, one of which has the greatest possible similarity if the instruction words differ within a group in terms of content.
• Another possible embodiment of the method is that the newly generated secondary instruction word is added to the second group by storing it instead of the secondary instruction word used to generate it.
• Another possibility is that the newly created one Secondary instruction word is not saved. Each time a secondary instruction word is generated, the same supply of instruction words that have been generated is always used, which is expedient if these stored instruction words are suitable as sample words for generating other secondary instruction words, in which case storage processes can be avoided.
• One embodiment of the method provides that the first identifier is formed as the distance between the primary instruction word belonging to the respective program word and the primary instruction word with the greatest match.
• a further embodiment of the method provides that the second identifier consists of an address of a preceding secondary instruction word corresponding to the first identifier in a memory which serves to store the second group.
• a reduction in the program word width and associated reduction in the width of the program memory can be achieved in that the program word consists of a number of instruction word parts, which corresponds to the number of instruction word parts to be distinguished most frequently within the configuration, and that for the composition of secondary instruction words, the If the secondary instruction word used for the generation requires more than the number of instruction words stored in a program word, several program words are used.
• the width of the program memory is sufficient for the most common applications, and there is also no delay in the creation of the secondary instruction word. Only in the relatively few cases in which the number of instruction word parts to be changed exceeds the width of a program word, two or more program words are words required in two or more measures to produce the secondary instruction word.
• a further reduction in the program word width can be achieved by compressing the instruction word parts in one program word. This is done by reducing the bit width to the extent that a representation of the most frequently occurring instruction word parts is possible, and by using several program words when instruction word parts occur which require a larger bit width to be displayed.
• the width of the instruction word parts in the program word is halved and one or two program words are provided to represent the instruction word parts.
• the program word normally has a width of 8 bits, 256 combinations are available. However, a large part of these combinations is only used extremely rarely or not at all. Accordingly, the program word can be provided with a width of 4 bits, which is sufficient for the 16 most common combinations for display. If a combination other than this is to be displayed, two or more program words are used for this. However, since this occurs only very rarely, the storage space saved for the program memory is greater than the possible time required to generate rare combinations.
• the task is also solved according to the invention by a processor arrangement, which is characterized in that the instruction word buffer consists of a memory with optional line-by-line access.
• the instruction word buffer consists of a memory with optional line-by-line access.
• Fig. 1 is a flow diagram of the method according to the invention.
• a sequence of primary instruction words 5 from a plurality of instruction word parts 6 is generated from a program code 3 by means of a translation 4 in a configuration phase.
• This sequence of primary instruction words 5 is compressed and stored in a program memory 8 as a sequence of associated program words 7.
• the program words 7 consist of a number of instruction word parts 6, which corresponds to the number of instruction word parts 6 that occurs most frequently within the configuration.
• the composition of secondary instruction words 9 may require more than the number of instruction word parts 6 stored in a program word 7. Several program words 7 are then used for this.
• sequence of program words 7 In a subsequent execution phase, the sequence of program words 7 generates successive secondary instruction words 9 from a plurality of instruction word parts 6 in the full instruction word width required to control all functional units 1.
• a program word 7 has an First identifier 10 of a primary instruction word 5 from a first group 11 of previous primary instruction words 5, which has the greatest match with the primary instruction word 5 associated with the program word 7, and instruction word parts 6, which contain the primary instruction word 5 belonging to the program word 7 from the primary instruction word 5 belonging to the identifier distinctive, contains.
• the first identifier 10 is formed as the distance of the primary instruction word 5 belonging to the respective program word 7 from the primary instruction word 5 with the greatest match.
• a second group 12 of secondary instruction words 9 corresponding in number to the first group 11 is stored, each provided with a second identifier 13.
• the second identifier 13 is formed from a line number of a memory 14 which serves to store the second group 12.
• a secondary instruction word 9 corresponding to the associated primary instruction word 5 is determined from the second group 12 via the associated second identifier 13.
• the secondary instruction word 9 corresponding to the program word is generated by exchanging the instruction word parts 6 contained in the program word 7 in the secondary instruction word 9 from the second group 12.
• the first group 11 consists of a first number of the primary instruction words 5 preceding the respective primary instruction word 5.
• the second group 12 consists of a second number of secondary instruction words 9, which is at least equal to the first number, each secondary instruction word 9 before the generation of the next one Second instruction word 9 of the second group 12 can be added last.
• the second instruction word 9 added above the second number is removed from the second group 12.

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• Engineering & Computer Science (AREA)
• Software Systems (AREA)
• Theoretical Computer Science (AREA)
• Physics & Mathematics (AREA)
• General Engineering & Computer Science (AREA)
• General Physics & Mathematics (AREA)
• Executing Machine-Instructions (AREA)
• Advance Control (AREA)

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• 1998
  • 1998-12-22 DE DE19859389A patent/DE19859389C1/de not_active Expired - Fee Related
• 1999
  • 1999-12-21 EP EP99963284A patent/EP1145113B1/de not_active Expired - Lifetime
  • 1999-12-21 AU AU19648/00A patent/AU1964800A/en not_active Abandoned
  • 1999-12-21 JP JP2000590041A patent/JP4486754B2/ja not_active Expired - Lifetime
  • 1999-12-21 DE DE19982820T patent/DE19982820D2/de not_active Expired - Lifetime
  • 1999-12-21 WO PCT/DE1999/004050 patent/WO2000038049A1/de not_active Ceased
  • 1999-12-21 US US09/868,797 patent/US7080235B1/en not_active Expired - Lifetime

Patent Citations (3)

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