Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
  • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
  • H10K10/40—Organic transistors
  • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
  • H10K10/462—Insulated gate field-effect transistors [IGFETs]
  • H10K10/468—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
  • H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
  • H10K85/10—Organic polymers or oligomers
  • H10K85/111—Organic polymers or oligomers comprising aromatic, heteroaromatic, or aryl chains, e.g. polyaniline, polyphenylene or polyphenylene vinylene
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
  • H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
  • H10K85/10—Organic polymers or oligomers
  • H10K85/111—Organic polymers or oligomers comprising aromatic, heteroaromatic, or aryl chains, e.g. polyaniline, polyphenylene or polyphenylene vinylene
  • H10K85/113—Heteroaromatic compounds comprising sulfur or selene, e.g. polythiophene
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
  • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
  • H10K10/40—Organic transistors
  • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
  • H10K10/462—Insulated gate field-effect transistors [IGFETs]
  • H10K10/464—Lateral top-gate IGFETs comprising only a single gate
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
  • H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
  • H10K85/10—Organic polymers or oligomers

Definitions

• a method of manufacturing a field-effect transistor substantially consisting of organic materials is a method of manufacturing a field-effect transistor substantially consisting of organic materials.
• the invention relates to a method of manufacturing a field-effect transistor substantially consisting of organic materials.
• the invention also relates to a field-effect transistor substantially consisting of organic materials.
• the invention further relates to an integrated circuit (IC) comprising such a field-effect transistor (FET).
• IC integrated circuit
• FET field-effect transistor
• An integrated circuit comprising field-effect transistors substantially consisting of organic materials, in short organic field-effect transistors, is well suited for those electronic applications where using an integrated circuit manufactured using silicon technology would be prohibitively expensive. Examples include electronic bar codes.
• each individual field-effect transistor must be operated in a saturated regime, which is the regime where the channel transconductance exceeds the channel conductance.
• a method of the type mentioned in the opening paragraph, which provides an organic FET satisfying said condition for voltage amplification is known from an article by Gamier et al. published in Science, vol. 265 (1994), pp. 1684-1686.
• a 1.5 ⁇ m thick polyester film is framed and is printed on both sides with a graphite- filled polymer ink, so as to form a 10 ⁇ m thick gate electrode on the one side and a source and drain electrode on the other side.
• a 40 nm semiconducting sexithiophene layer is then deposited using flash evaporation.
• a disadvantage of the known method is that the organic FETs provided by the method satisfy the condition for voltage amplification only at rather high (negative) source drain voltages. Typically, the difference is 30 V or higher. For many electronic applications, such as battery operated applications, such a voltage is too high. Also, the method is not very practical, not least because it involves framing and printing on a layer of only 1.5 ⁇ m. Such a thin film is very fragile and easily ruptures while being handled, leading to a defective device.
• An object of the invention is, inter alia, to provide a novel method of manufacturing a field-effect transistor substantially consisting of organic materials. The novel method should enable, in a practical manner, the manufacture of an organic FET satisfying the condition of voltage amplification at a source drain voltage difference significantly less than 30 V, in particular less than 10 V.
• the object of the invention is achieved by a method of manufacturing a field-effect transistor substantially consisting of organic materials on a substrate surface, said method comprising the steps of: - providing an electrically insulating substrate surface,
• the invention is based on the insight that a very thin electrically insulating layer, that is a layer having a thickness of 0.3 ⁇ m or less, is required if an organic FET is to satisfy the condition of voltage amplification at a source drain voltage difference of less than 10 V. It is further based on the insight that such a thin insulating layer can only be obtained in a practical manner if (in contrast to the known method in which the insulating layer is used as a substrate for depositing the electrodes) the thin insulating layer is supported by a substrate throughout the manufacture of the FET. Most conveniently, the insulating layer is applied to a surface which is substantially planar.
• the first electrode layer in the form of a patchwork pattern of electrically insulating and conducting areas provides a substantially planar surface (the difference in thickness between the insulating and conducting areas being 0.05 ⁇ m or less).
• the method in accordance with the invention is simple and cost effective.
• the first and second electrode layer, as well as the insulating and semiconducting layer, can be, and preferably are, all applied from solution using coating techniques known per se, such as spin-coating, dip-coating, spray-coating, curtain-coating, silkscreen-printing. offset-printing, Langmuir Blodgett and the doctor blade technique.
• the field-effect transistor obtained by employing the method in accordance with the invention operates in the usual manner.
• the semiconducting layer comprises an area, the channel, which interconnects the source and the drain electrode.
• the gate electrode is electrically insulated from the channel by means of the insulating layer and overlaps the channel. If a voltage is applied between the source and drain electrode, a current, i.e.
• the source drain current will flow through the channel.
• a gate voltage By applying a gate voltage, an electric field is established across the semiconducting layer which will, depending on the polarity of both the gate voltage and the charge carriers, modify the free charge carrier distribution in the channel, thereby changing the resistivity of the channel and the source drain current. If the source drain voltage is increased while the gate voltage is kept constant, the source drain current will begin to saturate and at some point the condition of voltage amplification, i.e. the channel transconductance exceeding the channel conductance, is satisfied.
• the first electrode layer comprises electrically insulating and conducting areas, which may be of any convenient shape.
• the source and drain electrode are accommodated by separate conducting areas. In order to increase the channel width, thus allowing more current between source and drain, the source and drain electrode are preferably interdigitated.
• the sheet resistance of the insulating areas needs to be as high as possible.
• a suitable sheet resistance exceeds 10 10 ⁇ /square, or better 10 12 ⁇ /square or better still 10 13 ⁇ /square.
• the specific conductivity of the conducting areas of the electrode layer is chosen such that the source drain current is substantially determined by the resistivity of the channel.
• a suitable specific conductivity of the conducting areas is 0.1 S/cm or better 1 S/cm or better still more than 10 S/cm.
• Applying the patchwork patterned first electrode layer is for example done by applying a semiconducting polymer in an insulating state from solution, applying and patterning a photoresist layer photolithographically and introducing conducting areas by selective indiffusion of a dopant which converts locally the polymer from its insulating to a conducting state.
• the patchwork patterned first electrode layer is applied without using the elaborate technique of photolithography.
• the organic first electrode is applied by performing the method steps of
• a radiation-sensitive layer comprising an electrically conducting polyaniline and a photochemical radical initiator.
• a layer may be rendered radiation insensitive by a simple heat treatment at for example 110 °C. This property is very advantageous if an IC is to be manufactured, especially if multi level interconnects are required, for it allows the second (and any further) electrode layer to be patchwork patterned employing the same radiation-sensitive composition and method steps without the pattern of the first electrode layer being affected by the radiation employed in providing said second electrode layer.
• Suitable semiconducting layers comprise organic compounds having an extensive conjugated system of double and/or triple bonds such as conjugated polymers (in the context of the invention, the term polymer includes oligomer) and fused (heterosubstituted) polycyclic hydrocarbons. Examples include polypyrroles, polyphenylenes, polythiophenes, polyphenylenevinylenes, poly(di)acetylenes, polyfuranes and polyanilines. As known by those skilled in the art, such compounds may be rendered semiconducting by doping with an oxidizing agent, reducing agent and/or (Bronsted) acid. It may happen that the method of preparing the semiconducting compound is such that the compound is obtained in the semiconducting state without explicitly adding a dopant, in which case the compound is said to be unintentionally doped.
• the semiconducting layer may swell or even dissolve into the subsequent layer before the solvent is removed, thus ruining the definition of the interface.
• an insoluble semiconducting compound obtainable from a soluble precursor compound. Examples of such compounds, viz. a polythienylenevinylene and a pentacene, are described in a publication by Brown et al. in Science, vol. 270, (1995), pp. 972-974.
• an organic electrically insulating layer is applied which electrically insulates the gate electrode from the semiconducting layer.
• the electrically insulating layer preferably has a high capacitance so as to induce a large current between source and drain using a low gate voltage which is accomplished by using a material with a large dielectric constant and/or a small layer thickness.
• the thickness of the insulating layer is preferably more than 0.05 ⁇ m.
• a preferred embodiment of the method in accordance with the invention is therefore characterized in that the organic electrically insulating layer comprises a cross-linked polymer.
• a cross-linkable polymer which has been found very effective is a polyvinylphenol. It can be cross-linked by adding a cross-linking agent such as hexamethoxymethylenemelamine and heating.
• the organic FET is completed by applying a second electrode layer accommodating a gate electrode.
• the insulating layer already being in place, the (variation in) layer thickness and the deposition process is less critical.
• the second electrode layer can be suitably applied using the method disclosed in the article by Garnier et al. cited hereinabove, that is, printing of a graphite filled polymer ink.
• a method of manufacturing the organic FET which is more economical and allows a higher resolution, results if the second electrode is applied in the same manner as the first electrode layer.
• the method involves providing an electrically insulating substrate surface.
• the surface should be planar and smooth.
• Suitable substrates are ceramics, glass, silica or, preferably, (laminated) polymer foils such as polystyrene, polyamide, polyamide and polyester foils. If a first electrode layer comprising conductive polyaniline and a photochemical radical initiator is applied, the substrate surface preferably comprises (cross- linked) polyvinylphenol or polyvinylalcohol.
• a preferred embodiment of the method in accordance with the invention is the method according to Claim 5.
• This method has been found particularly suitable in that each time a subsequent layer is applied from solution, swelling or dissolution of the preceding layer does not occur.
• the method moreover allows FETs having a channel length as small as 1 to 2 ⁇ m to be produced in a reliable and practical manner.
• a field-effect transistor manufactured using the method in accordance the invention is operated for a long time (for minutes to hours) at high source drain voltage differences, there is a risk that the performance of the FET deteriorates to the extent that it does no longer satisfy the condition for voltage amplification at voltages below 10 V.
• a preferred embodiment of the method in accordance with the invention is characterized in that before the semiconducting layer is applied, the electrically insulating areas of the first electrode layer are removed, thereby forming a first electrode layer demonstrating a relief pattern of conducting areas.
• the first electrode layer comprises polyaniline
• removal can be achieved, for example, by dissolving selectively the electrically insulating areas in N- methylpyrrolidone.
• the presence of a relief pattern does not lead to a dramatic increase in leakage current or short circuits between the source (drain) and gate electrode. At least this is found to be the case if the thickness of the first electrode layer is chosen to be smaller than the thickness of the insulating layer.
• a relief pattern satisfying this criterion provides a surface which is more or less planar from the viewpoint of the capability of said surface to serve as a substrate surface onto which a very thin insulating layer can be applied in a practical manner.
• the FET obtained by employing (preferred embodiments of) the method in accordance with the invention is a top gate field-effect transistor.
• the method in accordance with the invention is simply modified in that the gate electrode is accommodated by the first and the source and drain electrodes are accommodated by the second electrode layer, and the semiconducting and electrically insulating layer are applied in reverse order.
• Yet another bottom gate FET is obtained if the method of manufacturing the bottom gate FET is modified in that the second electrode and semiconducting layer are applied in reverse order.
• the invention also relates to a field-effect transistor substantially consisting of organic materials, that is a field-effect transistor comprising a stack of: an organic first electrode layer accommodating a source and drain electrode and demonstrating a relief pattern of electrically conducting areas, an organic semiconducting layer, an organic electrically insulating layer, and an organic second electrode layer accommodating a gate electrode.
• the field-effect transistor is therefore characterized in that the thickness of the electrically insulating layer is greater than the thickness of the first and/or second electrode layer and less than 0.3 ⁇ m. It is clear that applying a 0.3 ⁇ m layer on a 0.3 ⁇ m topography results in an insulating layer which is neither planar nor planarized. Surprisingly, the use of planarised insulating layers appears to be superfluous.
• Short circuits are substantially absent if the surface defined by the first and/or second electrode layer has a topography smaller than the layer thickness of the insulating layer to be applied to that surface.
• the insulating layer should have a thickness less than 0.3 ⁇ m. Since the insulating layer may be far from planar, the layer thickness is defined as the thickness that would have been obtained if, using the same method, it had been applied onto a planar surface.
• JP-A- 1-259563 a field-effect transistor substantially consisting of organic materials is disclosed.
• Said document does not disclose a method of manufacturing such a device, let alone a practical method producing a field-effect transistor which satisfies the condition for voltage amplification below a source drain voltage of 10 V.
• the known field-effect transistor does not have a patchwork patterned electrode layer and the thickness of the planarized insulating layer is not specified.
• the invention also relates to an integrated circuit comprising a field-effect transistor in accordance with the invention or a field-effect transistor obtainable by a method in accordance with the invention.
• Changing the pattern of the first and second electrode layer is all that needs to be done if not just one but a plurality of organic FETs is to be produced on a single substrate surface.
• Fig. 1 schematically shows a transparent plan view of a field-effect transistor manufactured using the method in accordance with the invention
• Fig. 2 schematically shows a cross-sectional view taken on the line I-I in Fig. 1, and
• Fig. 3 shows a graph of the relationship between the source drain voltage V sd (in V) and the source drain current I sd (in nA) at specified gate voltages V (in V) of a field-effect transistor manufactured using the method in accordance with the invention when subjected to a source drain voltage sweep from 0 to -10 V and back.
• Fig. 1 schematically shows (not drawn to scale) a transparent plan view of a (part of a) field-effect transistor 1 manufactured using the method in accordance with the invention.
• Fig. 2 schematically shows (not drawn to scale) the field-effect transistor 1 in a cross-sectional view taken on the line I-I in Fig. 1.
• the field-effect transistor 1 comprises an electrically insulating substrate 2 on which is provided an organic first electrode layer 3 demonstrating a patchwork pattern of electrically insulating areas 31 and conducting areas 32 and 33.
• the conductive area 32 accommodates the source and the area 33 the drain electrode.
• the organic semiconducting layer 4 comprises a channel 41 (drawn so as to indicate the definition of channel length and width), of which the channel length L is indicated by reference number 411 and the channel width W by reference number 412. Covering the layer 4 and thus the channel 41 is the organic electrically insulating layer 5. It electrically insulates the gate electrode from the channel 41 , said gate electrode being accommodated by the electrically conducting area 62 of the second electrode layer 6.
• the layer 6 is a layer demonstrating a patchwork pattern of electrically insulating areas 61 and conducting areas 62.
• the field- effect transistor 1 may be manufactured as follows: A) preparation of a conducting polyaniline solution
• Emeraldine base polyaniline (Neste) (0.7 g, 7.7 mmol) and camphor sulphonic acid (Janssen) (0.8 g, 3.4 mmol) are ground together with a mortar and pestle in a nitrogen-filled glove box.
• the mixture is split in two and placed in two 30 ml polyethylene bottles each containing 30 g m-cresol and three agate balls (0.9 mm diameter). These are placed in a shaker (Retsch MM2) operating at full speed for 14 to 18 hours.
• the contents of the bottles are combined and then sonified for 5 minutes.
• the mixture is cooled to room temperature and then the sonification process is repeated. This mixture is then centrifuged at 12500 rpm for 2 hours.
• the conducting polyaniline solution thus obtained is pipetted off leaving any solids at the bottom of the centrifuge tubes.
• a quantity of 10.0 g (0.028 mol) 2.5-thienylenedimethylene- bis(tetrahydrothiophenium chloride) (supplier Syncom BV, Groningen, The Netherlands) is dissolved in 100 ml of a 2/1 v/v mixture of methanol and demineralised water and cooled to -22 T in a nitrogen environment. Pentane (120 ml) is added and then sodium hydroxide (1.07 g, 0.0268 mol) dissolved in 100 ml of a 2/1 v/v mixture of methanol and demineralised water and cooled to -22 °C is added instantaneously to the stirred monomer solution kept at -22 °C.
• a 65 ⁇ polyamide foil (supplier Sellotape) is secured on a 3 inch silicon wafer.
• the photochemical radical initiator 1-hydroxycyclohexyl phenyl ketone (tradename Irgacure 184, Ciba Geigy) is added 6 g of the conducting polyaniline solution prepared under A. After mixing well and sonifying twice for 1 min and cooling in between, the radiation-sensitive solution thus obtained is cooled and filtered (Millex FA, 1 ⁇ m). A radiation-sensitive layer is then formed by spin-coating (3 s/500 rpm, 7 s/2000 rpm) 1 ml of the radiation-sensitive solution on the polyvinylphenol coated surface of the substrate 2, and drying on a hotplate (2 min at 90 °C).
• the wafer is placed in a Karl Suss MJB3 aligner equipped with a 500 W Xe lamp and flushed with nitrogen for 3 min.
• the radiation-sensitive layer is irradiated via the mask with deep UV light (60 s, 20 mW/cm 2 at 240 nm), thereby forming a first electrode layer 3 demonstrating a patchwork pattern of irradiated areas 31 and non- irradiated areas 32 and 33.
• the wafer is then heated on a hotplate (3 min at 110°C, 1 min at 150°C) so as to remove the unreacted photochemical radical initiator.
• the layer 3 is now insensitive to the deep UV light used in the irradiation and substantially planar, the thickness of the irradiated areas being 0.25 ⁇ m, and of the non-irradiated areas 0.22 ⁇ m.
• the sheet resistance of the area 31 is 4 x 10 13 ⁇ /square (conductivity 10 "9 S/cm), of the areas 32 and 33 it is 760 ⁇ /square (conductivity 60 S/cm).
• 3 ml precursor polythienylenevinylene solution prepared under B is spin-coated (3 s/500 rpm, 7 s/1000 rpm) on the layer 3.
• This precursor layer is then heated on a hot plate at 150 °C for 10 min in a nitrogen atmosphere containing HCl gas at a partial pressure of 2.3 x 10 "3 bar, thus converting the precursor layer into a 50 nm thick semiconducting layer 4 comprising a polythienylenevinylene.
• a cross-linkable composition consisting of 4.0 g (0.034 mol) polyvinylphenol (Polysciences Inc. , cat #6527) and 0.65 g (1.66 mmol) hexamethoxymethylenemelamine (Cymel 300 from Cyanamid) dissolved in 36 g propylene glycol methyl ether acetate (Aldrich), is spin-coated (3 s/500 rpm, 27 s/2500rpm) on the layer 4 and dried at 110 °C for 1 min on a hotplate.
• Cross-linking at 125 °C in a nitrogen atmosphere containing 5 % v/v HCl for 5 min affords a 0.27 ⁇ m cross-linked polyvinylphenol electrically insulating layer 5.
• the dielectric constant of the cross-linked polyvinylphenol is 4.78 and its conductivity (at 1 kHz) 4.4 x 10 "1 1 S/cm.
• a second electrode layer 6 is applied on the layer 5.
• the second electrode layer 6 demonstrates a patchwork pattern of irradiated electrically insulating areas 61 and non-irradiated electrically conducting areas 62 (only one area shown), the latter areas accommodating the gate electrodes.
• FET 1 is covered by a 0.5 ⁇ m encapsulation layer obtained by spin-coating (3 s/500 rpm, 7 s/2000 rpm) a filtered (Millex LS 5 ⁇ m) solution of 1.5 g (0.028 mol) polyacrylonitrile (Polysciences Inc. , cat# 3914) in 38.5 g N-methylpyrrolidone and drying at 110 °C for 1 min.
• a solution of 25 g polyvinylidenefluoride (Polysciences Inc, cat #15190) in 25 g N-methylpyrrolidone may be used.
• Fig. 3 shows a graph of the relationship between the source drain voltage V sd (in V) and the source drain current I sd (in nA) at specified gate voltages V g (in V) of a field-effect transistor 1 , manufactured using the method of exemplary embodiment 1 , when subjected to a source drain voltage sweep from 0 to -10 V and back.
• the channel length L equals 2 ⁇ m and the channel width W equals 1 mm.
• the channel transconductance exceeds the channel conductance, thus satisfying the condition for voltage amplification.
• the voltage sweep shows a substantially negligible hysteresis.
• the FET mobility is 10 "4 cm 2 /Vs.
• the method of exemplary embodiment 1 is repeated, with this difference that the patchwork patterned first electrode layer 3 is replaced by an electrode layer demonstrating a relief pattern.
• the relief pattern consists of 0.25 ⁇ m thick gold areas obtained by means of vacuum deposition using a shadow mask. The gold areas which accommodate the source and drain electrode are located such that the channel width is 10 mm and the channel length is 10 ⁇ m.
• the field-effect transistor obtained in this embodiment does not substantially consist of organic materials, and as such is not a FET in accordance with the invention, it does demonstrate that, in accordance with the invention, a FET may satisfy the condition for voltage amplification below 10 V if a relief pattern is used which has a topography (in casu 0.25 ⁇ m) less than the thickness of the insulating layer (in casu 0.27 ⁇ m).

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• 1998
  • 1998-07-27 EP EP98932464A patent/EP0968537B1/en not_active Expired - Lifetime
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