USRE45885E1 - Laser ablation of electronic devices - Google Patents
Laser ablation of electronic devices Download PDFInfo
- Publication number
- USRE45885E1 USRE45885E1 US14/260,240 US200614260240A USRE45885E US RE45885 E1 USRE45885 E1 US RE45885E1 US 200614260240 A US200614260240 A US 200614260240A US RE45885 E USRE45885 E US RE45885E
- Authority
- US
- United States
- Prior art keywords
- layer
- laser
- conductive layer
- substrate
- underlying layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related, expires
Links
- 238000000608 laser ablation Methods 0.000 title claims abstract description 48
- 238000000034 method Methods 0.000 claims abstract description 107
- 239000000758 substrate Substances 0.000 claims abstract description 78
- 238000000059 patterning Methods 0.000 claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 claims abstract description 11
- 238000002679 ablation Methods 0.000 claims description 43
- 239000000463 material Substances 0.000 claims description 31
- 239000004020 conductor Substances 0.000 claims description 8
- 239000010409 thin film Substances 0.000 claims description 8
- 239000011159 matrix material Substances 0.000 claims description 7
- 230000003287 optical effect Effects 0.000 claims description 7
- 230000032798 delamination Effects 0.000 claims description 2
- 238000005442 molecular electronic Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 132
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 40
- 239000010931 gold Substances 0.000 description 39
- 229910052737 gold Inorganic materials 0.000 description 39
- 229910052751 metal Inorganic materials 0.000 description 23
- 239000002184 metal Substances 0.000 description 23
- 238000004630 atomic force microscopy Methods 0.000 description 8
- 238000013461 design Methods 0.000 description 7
- 238000007639 printing Methods 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 7
- 239000007769 metal material Substances 0.000 description 6
- 229920000139 polyethylene terephthalate Polymers 0.000 description 6
- 239000005020 polyethylene terephthalate Substances 0.000 description 6
- 238000000151 deposition Methods 0.000 description 5
- 230000008021 deposition Effects 0.000 description 5
- 239000003989 dielectric material Substances 0.000 description 5
- 238000002955 isolation Methods 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 238000006731 degradation reaction Methods 0.000 description 4
- 238000007641 inkjet printing Methods 0.000 description 4
- 238000007645 offset printing Methods 0.000 description 4
- 230000037361 pathway Effects 0.000 description 4
- 229920000642 polymer Polymers 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 230000005855 radiation Effects 0.000 description 4
- 238000007650 screen-printing Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000003384 imaging method Methods 0.000 description 3
- 238000005507 spraying Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 238000012937 correction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 238000007646 gravure printing Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000004033 plastic Substances 0.000 description 2
- 229920003023 plastic Polymers 0.000 description 2
- 229920003229 poly(methyl methacrylate) Polymers 0.000 description 2
- 239000011112 polyethylene naphthalate Substances 0.000 description 2
- 239000004926 polymethyl methacrylate Substances 0.000 description 2
- 238000010129 solution processing Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 208000031481 Pathologic Constriction Diseases 0.000 description 1
- 229920001609 Poly(3,4-ethylenedioxythiophene) Polymers 0.000 description 1
- 229920001665 Poly-4-vinylphenol Polymers 0.000 description 1
- 229920002367 Polyisobutene Polymers 0.000 description 1
- 239000004793 Polystyrene Substances 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- UHYPYGJEEGLRJD-UHFFFAOYSA-N cadmium(2+);selenium(2-) Chemical compound [Se-2].[Cd+2] UHYPYGJEEGLRJD-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000002322 conducting polymer Substances 0.000 description 1
- 229920001940 conductive polymer Polymers 0.000 description 1
- 238000007766 curtain coating Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000003618 dip coating Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000007765 extrusion coating Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 230000005499 meniscus Effects 0.000 description 1
- 239000002082 metal nanoparticle Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000037230 mobility Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000012768 molten material Substances 0.000 description 1
- 239000002105 nanoparticle Substances 0.000 description 1
- 239000002070 nanowire Substances 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 229920003207 poly(ethylene-2,6-naphthalate) Polymers 0.000 description 1
- 229920002098 polyfluorene Polymers 0.000 description 1
- 229920006254 polymer film Polymers 0.000 description 1
- 229920002223 polystyrene Polymers 0.000 description 1
- 229920000123 polythiophene Polymers 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 239000011253 protective coating Substances 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000002407 reforming Methods 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 238000007764 slot die coating Methods 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 239000000725 suspension Substances 0.000 description 1
- 238000010023 transfer printing Methods 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
Images
Classifications
-
- H01L51/0023—
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
- H10K10/80—Constructional details
- H10K10/82—Electrodes
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K26/00—Working by laser beam, e.g. welding, cutting or boring
- B23K26/02—Positioning or observing the workpiece, e.g. with respect to the point of impact; Aligning, aiming or focusing the laser beam
- B23K26/06—Shaping the laser beam, e.g. by masks or multi-focusing
- B23K26/062—Shaping the laser beam, e.g. by masks or multi-focusing by direct control of the laser beam
- B23K26/0622—Shaping the laser beam, e.g. by masks or multi-focusing by direct control of the laser beam by shaping pulses
-
- B23K26/063—
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K26/00—Working by laser beam, e.g. welding, cutting or boring
- B23K26/02—Positioning or observing the workpiece, e.g. with respect to the point of impact; Aligning, aiming or focusing the laser beam
- B23K26/06—Shaping the laser beam, e.g. by masks or multi-focusing
- B23K26/064—Shaping the laser beam, e.g. by masks or multi-focusing by means of optical elements, e.g. lenses, mirrors or prisms
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K26/00—Working by laser beam, e.g. welding, cutting or boring
- B23K26/36—Removing material
- B23K26/40—Removing material taking account of the properties of the material involved
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K26/00—Working by laser beam, e.g. welding, cutting or boring
- B23K26/36—Removing material
- B23K26/40—Removing material taking account of the properties of the material involved
- B23K26/402—Removing material taking account of the properties of the material involved involving non-metallic material, e.g. isolators
-
- B23K26/4075—
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76892—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances modifying the pattern
- H01L21/76894—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances modifying the pattern using a laser, e.g. laser cutting, laser direct writing, laser repair
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/027—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed by irradiation, e.g. by photons, alpha or beta particles
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
- H10K71/621—Providing a shape to conductive layers, e.g. patterning or selective deposition
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K2101/00—Articles made by soldering, welding or cutting
- B23K2101/36—Electric or electronic devices
- B23K2101/40—Semiconductor devices
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K2103/00—Materials to be soldered, welded or cut
- B23K2103/16—Composite materials, e.g. fibre reinforced
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K2103/00—Materials to be soldered, welded or cut
- B23K2103/16—Composite materials, e.g. fibre reinforced
- B23K2103/166—Multilayered materials
- B23K2103/172—Multilayered materials wherein at least one of the layers is non-metallic
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K2103/00—Materials to be soldered, welded or cut
- B23K2103/50—Inorganic material, e.g. metals, not provided for in B23K2103/02 – B23K2103/26
-
- B23K2201/40—
-
- B23K2203/16—
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78681—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09672—Superposed layout, i.e. in different planes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/466—Lateral bottom-gate IGFETs comprising only a single gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/481—Insulated gate field-effect transistors [IGFETs] characterised by the gate conductors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
- H10K71/20—Changing the shape of the active layer in the devices, e.g. patterning
- H10K71/231—Changing the shape of the active layer in the devices, e.g. patterning by etching of existing layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
- H10K71/60—Forming conductive regions or layers, e.g. electrodes
Definitions
- the present invention relates to methods of fabricating electronic devices using laser ablation and to devices fabricated thereby.
- Embodiments of the methods are particularly suitable for defining electrodes within thin film transistor (TFT) structures using laser ablation in a step-and-repeat mode.
- TFT thin film transistor
- a route for achieving cost-effective electronics such as large-area displays and RFID circuits at higher throughputs than are available using conventional inorganic semiconductor wafer processing is required within organic electronics.
- conduction pathways in the form of electrodes and interconnects are required on more than one level within the device stack.
- metallic conductive layers are often necessary.
- a known method of patterning layers of a device is the use of pulsed lasers to ablate regions of a deposited layer, or to delaminate one thin layer of material from the surface of a usually thicker, second layer of a different material.
- pulsed lasers to ablate regions of a deposited layer, or to delaminate one thin layer of material from the surface of a usually thicker, second layer of a different material.
- a nano-second pulse-length laser such as a pulsed Excimer laser is used.
- Embodiments of the invention aim to provide a method of fabricating thin film transistor (TFT) structures by forming gate and other electrodes and interconnect lines by laser ablation in a step-and-repeat fashion.
- TFT thin film transistor
- a region of the substrate is exposed to the laser radiation, for example with a pattern defined by an optical mask, and the layer to be patterned is ablated.
- the sample is moved to another location with respect to the mask pattern projected onto the sample, and another ablation exposure occurs to pattern the layer in an adjacent region.
- this method to completely pattern the layer on the substrate it is necessary to define overlap regions where the substrate is exposed to the laser radiation in more than one step. This overlap region typically has lateral dimensions on the order of several 1-10 ⁇ m.
- the masks of neighbouring imaging regions must be slightly overlapped along the axis of the gate line interconnects, so that no thin traces of metal remain connecting parallel running interconnect lines after laser ablation.
- Mien defining the gate pattern which needs to overlap accurately with the source-drain pattern, it is possible to correct for this distortion by measuring the position of the source-drain pattern on the substrate and adjusting the position of the substrate with respect to the laser-exposed area, and the width of the overlap region with a previous shot, to correct for this substrate distortion, and ablate the gate pattern in good registration with respect to the source-drain pattern.
- Such a distortion compensation scheme typically increases the width of the overlap region which is required, since it preferably should be wide enough to accommodate the maximum possible distortion which is possible on the length scale of the size of substrate area exposed in a single laser shot.
- An electronic device typically contains a multilayer structure of conducting, semiconducting and dielectric layers.
- TFTs thin film transistor
- a method of fabricating an electronic device comprising a plurality of layers on a substrate, the layers including an upper conductive layer and at least one patterned underlying layer between said conductive layer and said substrate, the method comprising: patterning said underlying layer; and patterning said upper conductive layer by laser ablation using a stepwise process in which successive areas of said upper conductive layer are ablated by successively applied laser patterns; wherein said successively applied laser patterns overlap one another in an overlap region; and wherein said method further comprises configuring a said laser pattern and said patterned underlying layer with respect to one another such that in a said overlap region said patterned underlying layer is substantially undamaged by said stepwise laser ablation.
- the upper conductive layer is patterned so that in the overlap region, material of the underlying layer is substantially absent. In this way, although there may be some damage due to double exposure in the overlap region, the burring edge effect, of for example an underlying metal layer, can be avoided.
- the electronic device has a plurality of layers and the underlying layer is also conductive, separated from the upper conductive layer by at least one dielectric layer.
- the upper conductive layer will not be the topmost layer of the device since, for example, other overlying dielectric and/or protective layers or coating will also be present.
- the device comprises a display device and the underlying conductive layer is used to define a plurality of electrode lines, each with an adjacent stripe substantially free of conductive material (at the underlying layer level). This facilitates using a laser ablation in a step-and-repeat mode, in which the same pattern is stepped across the device for each laser ablation exposure.
- At least one of the two overlapping laser patterns is configured to leave the upper conductive layer substantially unablated in parts of the overlap region, beneath which material of the patterned underlying layer is present.
- both of the overlapping laser patterns may be configured to leave parts of the overlap region covering the patterned underlying layer material, substantially in tact.
- a region of the upper conductive layer is left over the parts of the underlying layer that remain after patterning and these upper conductive layer regions can be thought of as “sacrificial” regions.
- the two overlapping patterns in general comprise different patterns, each of which may be defined by a respective sub-field mask.
- Some preferred versions of the above-described embodiments further comprise compensating for distortion of the substrate by adjusting positions of the successively applied laser ablation patterns and/or of the substrate. Details of some techniques, which may be employed to map the substrate distortion for use in a distortion compensation scheme, are described in the Applicant's co-pending UK Patent Application No. GB0506613.9 filed 1 Apr. 2005 and claiming priority from GB30426126.9 filed 29 Nov. 2004, the relevant contents of which are hereby incorporated by reference in their entirety.
- the device comprises a thin film transistor (TFT), and one of the underlying layer and upper conductive layer comprises a source-drain layer of the TFT, the other a gate layer of the TFT (either a top-gate or a bottom-gate configuration may be employed).
- TFT thin film transistor
- the device comprises an organic or molecular electronic device.
- Embodiments of the method are particularly suitable for fabricating such a device on a flexible substrate such as a plastic substrate, for example a thin sheet of polyethyleneterephthalate (PET) or polyethylenenaphthalate (PEN).
- the laser ablation comprises single-shot laser ablation, for example using an ultraviolet laser such as an Excimer laser (248 nm).
- the pulse length of a typical Excimer laser is in the region of 30 ns, but in some embodiments of the method the use of shorter duration laser pulses can achieve improved results, for example pulses of less than 10 ns or less than Ins duration.
- the upper conductive layer has an optical density (at a wavelength of the laser ablation) of at least 0.5, preferably at least 1.0.
- the invention further provides a thin film transistor (TFT) active matrix display sensing device and logic circuit fabricated by a method as described above, in particular by any of the preferred embodiments of the described method.
- TFT thin film transistor
- a method for designing a circuit pattern for a step-and-repeat laser ablation process on an upper level of the device, wherein the pattern of conducting or semiconducting structures on a lower level of the device is designed in such a way that in the region of overlap between subsequent laser exposures, no conducting electrode or interconnect structure is present in the underlying layers. In this way the removal of underlying metal structure by laser ablation in the region of overlap is prevented.
- the pixel TFT circuits in such a way that on the lower substrate level containing the data lines (top-gate configuration) or addressing lines (bottom gate configuration) there is a narrow stripe running parallel to the data and addressing lines, respectively, which can be free of metal pattern.
- the overlap region between subsequent exposure steps for the laser ablation on an upper electrode level can be positioned to lie within this metal-free region of the underlying substrate pattern.
- the thickness of the upper conductive layer is chosen to be below 150-200 nm in order to allow ablation in a single shot, but sufficiently thick such that the optical density of the upper conductive layer is sufficiently high to shield any of the radiation sensitive layers in lower layers from the laser light, and to keep the energy density absorbed in any of the lower layers below their respective ablation thresholds.
- the upper conductive layer is thicker than 10 nm, and its optical density at the wavelength of the laser is preferably higher than 0.5 and most preferably higher than 1.
- the pulse fluence is selected to be above the ablation threshold for the upper layer, but below the damage threshold of any of the lower layers.
- a 50 nm upper layer of Gold which has an optical density of about 4.
- a 100 mJ cm ⁇ 2 spatially uniform (within 10%) laser pulse is then fired at the gold layer (248 nm, 30 ns laser pulse) from an Excimer laser. This is well above the ablation threshold (delamination threshold) for the gold. Up to the point in time of ablation of the gold layer, nearly all of the laser energy is absorbed in the upper gold layer, since the optical density is so high (in the order of 4).
- the underlying dielectric layer is heated but is not ablated.
- the top conductive layer/underlying substrate combination such that they exhibit relatively poor adhesion, for example, in the case of a layer of gold, by deposition onto a layer of polymer.
- a method for designing a circuit pattern for a step-and-repeat laser ablation process on an upper level of the device, wherein the mask pattern for defining the conducting or semiconducting structures on the upper level includes “sacrificial” structures at the edge of the field of laser exposure, which block laser exposure in portions of the overlap regions in which metal structures on the lower level cross through the overlap region. In this way the removal of underlying metal structure by laser ablation in the region of overlap can be substantially prevented.
- FIG. 1 shows a fabrication process of a multi-layer stack for polymer-based printed TFTs
- FIG. 2 shows positioning of an overlap region of two adjacent masks, in-between a pixel electrode and a source line, where there is no underlying metallic material
- FIG. 3 shows a schematic of a source-drain pattern of an active matrix TFT array before gate patterning by laser ablation
- FIG. 4 shows a schematic of a processed panel after a layer of a preferred conductive material is deposited over a prepared substrate
- FIG. 5 demonstrates the formation of an isolated gate line that results after a laser ablation process is repeated through a mask, 5 (a) with an ablation region of 500 ⁇ m, and 5 (b) using a much larger mask size;
- FIG. 6 shows an example of a patterned 50 dpi panel, using a fluence of 94 mJ cm ⁇ 2 ;
- FIGS. 7 (a) and (b) shows formation of two gate lines on a panel demonstrating a kink in the upper gate line
- FIG. 8 shows an Atomic Force Microscopy (AMM) image taken after ablation of a gold layer, over the edge of an ablated region;
- AMM Atomic Force Microscopy
- FIG. 9 shows an Atomic Force Microscopy (AFM) image taken over the edge of a two shot overlap region
- FIG. 10 illustrates line conductivity measurements that show good interline isolation was obtained using a laser ablation process according to an embodiment of the invention
- FIG. 11 shows a graph of drain current against gate voltage illustrating characteristics of a pixel TFT with laser ablated gold gate interconnects showing good on and off currents measured for a TFT fabricated as described herein;
- FIG. 12 shows an example of a mask design for a gate pattern for a logic circuit
- FIG. 13 illustrates a mask design where a laser beam has been shot at the left hand side sub-field to be imaged on the substrate surface and the right hand side sub-field still remains to be imaged;
- FIG. 14 shows a schematic of an integrated circuit diagram on the source and drain level
- FIG. 15 shows a schematic after the ablation of the metallic material that falls within both of the sub-fields of a mask.
- An example is disclosed to ablate material within upper layers of a multi-layer device structure in order to create gate line isolation.
- the method utilizes a technique of laser ablation to remove material within a large area and realize a high resolution, high conductivity and high throughput process at a low temperature.
- the ablation region is formed by a mask that is moved in a step-and-repeat manner to adjacent positions on the substrate where the ablation process is then repeated.
- a region of overlap between adjacent masks is created referred to here as the stitching region.
- the prevention of radiation degradation of the underlying layers within this two-shot overlap area is achieved by positioning the overlap area between the pixel and the source line in a region where there is no gold present on the lower layer.
- the fabrication of a multi-layer stack for polymer-based printed TFTs is conducted according to FIG. 1 .
- Conductive material is deposited and patterned on a substrate 1 to form source and drain electrodes 2 .
- the substrate may be either glass or a polymer film, but preferably a plastic substrate such as polyethyleneterephthalate (PET) or polyethylenenaphthalene (PEN) is used.
- the patterned conductive layer 2 comprises a conducting polymer, such as PEDOT, or a metallic material, such as gold, silver, copper or aluminium. It may be deposited and patterned through solution processing techniques such as, but not limited to, spin, dip, blade, bar, slot-die, or spray coating, inkjet, gravure, offset or screen printing. Alternatively, vacuum deposition techniques may be used, such as evaporation and sputtering as well as photolithographic patterning techniques.
- a layer of semiconducting material 3 may then be deposited over the substrate and patterned electrodes.
- the semiconducting layer may comprise materials such as, but not limited to, polyarylamine, polyfluorene or polythiophene derivatives.
- a broad range of printing techniques may be used to deposit the semiconducting material including, but not limited to, inkjet printing, soft lithographic printing (J. A. Rogers et al., Appl. Phys. Lett. 75, 1010 (1999); S. Brittain et al., Physics World May 1998, p. 31), screen printing (Z. Bao, et al., Chem.
- the semiconducting layer may be deposited as a thin continuous film and patterned subtractively by techniques such as photolithography (see WO 99/10939) or laser ablation.
- a layer of gate dielectric material 4 is then deposited onto the layered substrate.
- Materials such as polyisobutylene or polyvinylphenol may be used as the dielectric material, but preferably polymethylmethacrylate (PMMA) and/or polystyrene are used.
- PMMA polymethylmethacrylate
- the dielectric material may be deposited in the form of a continuous layer, by techniques such as, but not limited to, spray or blade coating. However, preferably, the technique of spray coating is used.
- the deposition of the dielectric layer is then followed by the deposition of a gate electrode 5 and interconnect lines.
- the material of the gate electrode may be a thin film of inorganic metal such as gold or a cheaper metal such as copper or aluminium.
- the gate electrode is deposited using techniques such as sputtering or evaporation techniques or solution processing techniques such as spin, dip, blade, bar, slot-die, gravure, offset or screen printing. Alternatively electroless plating techniques maybe used.
- the selective ablation process described below is more easily achieved for thin layers of metal than for thick layers. However, in many cases a minimum layer thickness is required in order to reach the necessary conductance. A thickness of 50 nm provides the necessary conductance for a range of applications, including gate interconnections for flat panel displays.
- the metallic layer 7 is preferably ablated using a 248 nm Excimer laser 6 , although other wavelengths can be used as well.
- a laser such as a Lumonics PM800 lasers (300 mJ, 30W) may be used.
- a mask is positioned over the layered substrate to create the ablation region.
- the upper layer of the preferred gold material within the ablation region is removed upon firing a single shot from the laser, substantially without any damage to the underlying metallic layers or the dielectric layer and in addition, very little debris.
- the ablation region is large when only a single shot is fired.
- a range of fluence from 28 to 112 mJ cm ⁇ 2 may be used to remove the upper gold layer without any apparent damage to the underlying layers. This results in a clean process without the formation of excess debris. This range of fluence is related to the absorption coefficient, thickness and adhesion of the upper metal layers.
- the mask is repositioned to an adjacent position along the substrate.
- the mask is moved, it is positioned such as to overlap with the previously ablated region.
- the ablation process is repeated in the new laser exposure region of the substrate.
- the region of overlap will now be exposed to two shots of the laser beam.
- the overlap region is positioned such that no highly absorbing layers, in particular no gold patterns in underlying layers on the source and drain level are present in the overlap region.
- this can be achieved by positioning the overlap region 8 in between the pixel and an electrode line such as the source line, where there is no underlying gold material.
- the positioning of the overlap region, in FIG. 2 is adjacent to the source line 9 .
- the transistor 10 and the pixel electrode 11 may also be seen in FIG. 2 .
- This laser ablation process may be used to image an entire panel in the way described above.
- a standard substrate is used and is prepared using the processing techniques described above, up to and including the deposition of the dielectric material.
- a schematic of the processed panel before ablation is shown in FIG. 3 .
- a layer of the preferred conductive material is then deposited over the prepared substrate.
- Preferably, a 50 nm of gold material is then sputtered over the substrate surface, to form a layer of gold. The result of this process is shown in FIG. 4 .
- the mask is positioned on the substrate and using a rectangular laser spot of dimensions, such as 508 ⁇ m ⁇ 394 ⁇ m, a single pulsed laser shot may be fired through the ablation region created by the mask.
- the mask is then repositioned 500 ⁇ m along the substrate adjacent to the previous ablation region with a 8 ⁇ m overlap with the previous region, and the laser ablation process is repeated. This results in a gate line width after ablation in the region of 106 ⁇ m. After the imaging process, the gate lines will be isolated. Due to the positioning of the overlap region, no damage can occur to the underling gold layer because of the absence of gold features on the source-drain level in the overlap region. This is demonstrated in FIG. 5a .
- this shows a PET substrate 500 bearing a lower gold layer 502 with a dielectric stack 504 deposited over the underlying active layers of the device.
- Ah upper deposited gold layer is present, uniform 506 a before ablation, and in striped regions 506 b after ablation.
- the figure shows removal of material from the upper gold layer of the device.
- a rectangular laser spot 508 is used (in the illustrated example, with dimensions 508 ⁇ m ⁇ 394 ⁇ m).
- the rectangular homogenised pulsed laser is moved across the surface of the layered substrate to remove regions of the upper gold layer (which here results in a width of gate region 506 b after ablation of approximately 106 ⁇ m).
- FIG. 5a shows the ablation region as a 500 ⁇ m window—covering just a single pixel.
- ablation region may be used, for example a 3 ⁇ 3 pixel array. This is illustrated in FIG. 5b .
- FIG. 6 shows an example of a 50 dpi panel patterned, using a fluence of 94 mJ cm ⁇ 2 to ablate a 50 nm gold layer. Ordinarily, this fluence would be sufficient to ablate the underlying layer of gold in the overlap region (example ringed in the Figure) if the upper layers of the substrate were not present. A thicker gold layer on the source and drain level would increase the ablation threshold and further reduce the risk of degradation to the underlying gold layer.
- An advantage of this technique is that it is able to overcome distortions over large areas of a panel.
- a typical width of the two-shot overlap region is 10 ⁇ m and the step-and-repeat distance of the laser system between subsequent exposures is 5000 ⁇ m.
- the step-and-repeat distance of the laser system between subsequent exposures is 5000 ⁇ m.
- For the given width of overlap region even with a complex (i.e. non-rectangular) mask shape, it is therefore possible to correct for substrate distortions up to approximately 1 ⁇ m/500 ⁇ m by simply adjusting the position of the next exposure area, and/or increasing/decreasing the width of the overlap region.
- typical substrate distortions on PET substrates were measured to be on the order of 1 ⁇ m/2000 ⁇ m, i.e. can be easily compensated for with a 10 ⁇ m wide overlap region.
- FIG. 7 a shows two gate lines, where a lateral distortion correction (perpendicular to the longitudinal step-and-repeat direction) has occurred.
- a slight kink in the gate line at the position indicated by the circle reflects a small shift of the exposure region on the right in order to compensate for a distortion of the source-drain pattern on the underlying layer.
- the relationship between the distortion of the source-drain pattern and the distortion correcting gate pattern is shown more clearly in an expanded view in FIG. 7b .
- FIG. 8 shows an Atomic Force Microscopy (AFM) image, which was taken after the ablation of the gold layer under the above stated conditions.
- the AFM cross section was measured across the edge of the ablated region as indicated by the dashed line in FIG. 8 (top).
- the step height equals the thickness of the gold layer (40 nm), indicating that no underlying dielectric material was removed during the one shot ablation process.
- a large burring region is seen as (the peak in the Figure) would be expected and as is discussed above.
- FIG. 9 shows an A-FM image taken over the edge of a two shot overlap region.
- the conditions are the same as for the one shot AFM discussed above. It can be seen that all of the dielectric stack material has been removed by the shot from the laser beam at 94 mJ cm ⁇ 2 , i.e. a groove extending approximately to the underlying substrate depth has been created in the overlap region. If any gold pattern had been presented on the source-drain level, this pattern would have been damaged in the overlap region leading potentially to electrical shorting to the gate layer, broken interconnections at the source-drain level, and other damage causing device failure.
- FIG. 11 illustrates that good on and off currents are obtained for the TFT design as discussed above.
- a sacrificial metal structure is defined on the upper metal level which may or may not be connected to any of the active metal structure on the upper level patterned by laser ablation, which protects the underlying metal during the laser ablation.
- the gate mask may be partitioned into separately imaged regions.
- a mask is used that creates a ablation region for the laser ablation process.
- a suitable mask is designed such that the mask is partitioned into sub-fields. These sub-fields comprise individual segments that shield the lower conductive material, that is preferably gold, from the laser beam.
- An example of a mask design for the gate pattern for a logic circuit is shown in FIG. 12 .
- FIG. 12 shows a mask that has been divided into two sub-fields.
- the mask is placed on the substrate surface and a single shot is fired through the ablation (clear) region of the mask.
- the mask is moved to an adjacent position along the substrate surface in order to image an adjacent part of the substrate using the remaining sub-field of the mask.
- FIG. 13 illustrates the above, where a laser beam has been shot at the left hand side sub-field to be imaged on the substrate surface and the right hand side sub-field still remains to be imaged.
- the mask is then moved such that We right hand sub-field is at an adjacent position on the substrate and a laser beam will then be shot onto the right hand side of the mask.
- the overlap region will experience two shots of the laser beam and therefore this region must not fall where there is conductive material in the underlying layers.
- FIG. 14 shows a schematic diagram of an integrated circuit at the source and drain level, which is to be patterned at the gate level using the mask of FIG. 13 .
- a layer of a metallic material preferably gold is then deposited over the substrate surface.
- the gate lines are then patterned using the mask. After a single laser shot has been fired into the left hand side sub-field of the mask, the mask is moved to an adjacent position and then the right hand side sub-field of the mask is used to image the next portion of the substrate.
- the mask pattern of (at least) one of the sub-fields has been designed in such a way that those areas are protected by a non-laser exposed area on the mask in which a “sacrificial” gold structure 9 remains on the gate level.
- This sacrificial structure is not electrically connected to any of the electrodes on the gate level, and therefore does not significantly affect device performance. All other areas in the overlap region have had the gold material ablated from them.
- a region of gold material is deliberately left at the gate level of the circuit. The gold material is left on the gate level after ablation using the sub-field mask design.
- Some of the conducting electrodes of the TFT and/or the interconnects in a circuit or display device may be formed from organic or inorganic conductors that can, for example, be deposited by printing of a colloidal suspension or by electroplating onto a pre-patterned substrate.
- any vacuum or solution processable conjugated polymeric or oligomeric material that exhibits adequate field-effect mobilities exceeding 10 ⁇ 3 cm 2 /Vs, preferably exceeding 10 ⁇ 2 cm 2 /Vs, may be used.
- Suitable materials are reviewed for example in H. E. Katz, J. Mater. Chem. 7, 369 (1997), or Z. Bao, Advanced Materials 12, 227 (2000).
- Other possibilities include small conjugated molecules with solubilising side chains (J. G. Laquindanum, et al., J. Am. Chem. Soc. 120, 664 (1998)), semiconducting organic-inorganic hybrid materials self-assembled from solution (C. R.
- the electrodes may be coarse-patterned by techniques such as inkjet printing, soft lithographic printing (J. A. Rogers et al., Appl. Phys. Lett. 75, 1010 (1999); S. Brittain et al., Physics World May 1998, p. 31), screen printing (Z. Bao, et al., Chem. Mat. 9, 12999 (1997)), and photolithographic patterning (see WO 99/10939), offset printing, flexographic printing or other graphic arts printing techniques.
- the laser ablation process described herein can be used to provide higher resolution patterning of these electrodes than is achievable with graphic arts printing techniques by trimming the edges of such coarsely patterned features.
- Devices such as TFTs fabricated as described above may be part of a more complex circuit or device in which one or more such devices can be integrated with each other and/or with other devices.
- Examples of applications include logic circuits and active matrix circuitry for a display, sensor or a memory device, and user-defined gate array circuits.
- the techniques described herein may, in the context of TFT fabrications, also be employed to pattern the source-drain layer of a bottom gate design.
- the patterning process may also be used to pattern other components of such circuits, such as interconnect lines, resistors, capacitors, inductors, diodes and the like.
- the structures described above can be supplemented by other conductive and/or semiconductive structures on the same substrate, for example interconnects. Multiple structures as described above may be formed on the same substrate, and may be connected together by electrically conductive interconnects to form an integrated circuit.
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Optics & Photonics (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Plasma & Fusion (AREA)
- Mechanical Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- Electromagnetism (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Thin Film Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Laser Beam Processing (AREA)
Abstract
Description
Claims (19)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/260,240 USRE45885E1 (en) | 2005-06-01 | 2006-08-31 | Laser ablation of electronic devices |
Applications Claiming Priority (12)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB0511132.3 | 2005-06-01 | ||
GBGB0511132.3A GB0511132D0 (en) | 2005-06-01 | 2005-06-01 | Layer-selective laser ablation patterning |
GB0513915.9 | 2005-07-08 | ||
GBGB0513915.9A GB0513915D0 (en) | 2005-06-01 | 2005-07-08 | Layer-selective laser ablation patterning |
GBGB0518105.2A GB0518105D0 (en) | 2005-09-06 | 2005-09-06 | Step-and-repeat laser ablation of electronic devices |
GB0518105.2 | 2005-09-06 | ||
GB0523141.0 | 2005-11-14 | ||
GBGB0523141.0A GB0523141D0 (en) | 2005-09-06 | 2005-11-14 | Laser ablation of electronic devices |
PCT/GB2006/050133 WO2006129126A2 (en) | 2005-06-01 | 2006-05-30 | Layer-selective laser ablation patterning |
PCT/GB2006/050265 WO2007029028A1 (en) | 2005-09-06 | 2006-08-31 | Laser ablation of electronic devices |
US12/065,722 US8062984B2 (en) | 2005-09-06 | 2006-08-31 | Laser ablation of electronic devices |
US14/260,240 USRE45885E1 (en) | 2005-06-01 | 2006-08-31 | Laser ablation of electronic devices |
Publications (1)
Publication Number | Publication Date |
---|---|
USRE45885E1 true USRE45885E1 (en) | 2016-02-09 |
Family
ID=34834937
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/915,731 Active 2029-12-01 US9209400B2 (en) | 2005-06-01 | 2006-05-30 | Layer-selective laser ablation patterning |
US14/260,240 Expired - Fee Related USRE45885E1 (en) | 2005-06-01 | 2006-08-31 | Laser ablation of electronic devices |
US14/919,056 Abandoned US20160111667A1 (en) | 2005-06-01 | 2015-10-21 | Layer-selective laser ablation patterning |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/915,731 Active 2029-12-01 US9209400B2 (en) | 2005-06-01 | 2006-05-30 | Layer-selective laser ablation patterning |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/919,056 Abandoned US20160111667A1 (en) | 2005-06-01 | 2015-10-21 | Layer-selective laser ablation patterning |
Country Status (5)
Country | Link |
---|---|
US (3) | US9209400B2 (en) |
EP (1) | EP2463928B1 (en) |
JP (2) | JP5342876B2 (en) |
CN (1) | CN101669224B (en) |
GB (2) | GB0511132D0 (en) |
Families Citing this family (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB0506899D0 (en) | 2005-04-05 | 2005-05-11 | Plastic Logic Ltd | Multiple conductive layer TFT |
GB0518105D0 (en) * | 2005-09-06 | 2005-10-12 | Plastic Logic Ltd | Step-and-repeat laser ablation of electronic devices |
WO2007029028A1 (en) | 2005-09-06 | 2007-03-15 | Plastic Logic Limited | Laser ablation of electronic devices |
GB0511132D0 (en) | 2005-06-01 | 2005-07-06 | Plastic Logic Ltd | Layer-selective laser ablation patterning |
EP2005499B1 (en) * | 2006-03-29 | 2013-04-24 | Plastic Logic Limited | Techniques for device fabrication with self-aligned electrodes |
US7923837B2 (en) * | 2007-10-31 | 2011-04-12 | Hewlett-Packard Development Company, L.P. | Microelectronic device patterned by ablating and subsequently sintering said microelectronic device |
US20100081255A1 (en) * | 2008-09-29 | 2010-04-01 | Erasenthiran Poonjolai | Methods for reducing defects through selective laser scribing |
US20120318776A1 (en) * | 2009-09-24 | 2012-12-20 | Electro Scientific Industries, Inc. | Method and apparatus for machining a workpiece |
US8197037B2 (en) | 2009-12-15 | 2012-06-12 | Xerox Corporation | Method of removing thermoset polymer from piezoelectric transducers in a print head |
FR2959865B1 (en) * | 2010-05-07 | 2013-04-05 | Commissariat Energie Atomique | REDUCING THE EFFECTS OF CAPS DUE TO LASER ABLATION OF A METAL LEVEL USING A NON-RETICULATED PHOTO- OR THERMO-RETICULABLE POLYMER LAYER |
GB2480876B (en) * | 2010-06-04 | 2015-02-25 | Plastic Logic Ltd | Conductive elements in organic electronic devices |
DE102011106799A1 (en) * | 2010-08-04 | 2012-02-09 | Heidelberger Druckmaschinen Aktiengesellschaft | Process for re-imaging a printed printing form |
CN104094170A (en) * | 2011-12-01 | 2014-10-08 | 艾利丹尼森公司 | Backplane for electrophoretic display |
KR101960745B1 (en) | 2012-11-14 | 2019-03-21 | 엘지디스플레이 주식회사 | Method of cutting flexible display device and method of fabricating flexible display device |
DE102012112550A1 (en) * | 2012-12-18 | 2014-06-18 | Lpkf Laser & Electronics Ag | Method for metallizing a workpiece and a layer structure of a workpiece and a metal layer |
JP6169093B2 (en) * | 2013-09-30 | 2017-07-26 | 株式会社シンク・ラボラトリー | Patterned roll and method for producing the same |
KR20150051479A (en) | 2013-11-04 | 2015-05-13 | 삼성디스플레이 주식회사 | Display apparatus and a method for preparing the same |
US11130195B2 (en) | 2014-07-29 | 2021-09-28 | Gentex Corporation | Laser ablation with reduced visual effects |
US10185198B2 (en) | 2015-06-19 | 2019-01-22 | Gentex Corporation | Second surface laser ablation |
DE112015006970T5 (en) * | 2015-09-25 | 2018-09-20 | Intel Corporation | Thin elements for electronics enclosures, using laser spluttering |
DE102016100157A1 (en) * | 2016-01-05 | 2017-07-06 | Thyssenkrupp Rasselstein Gmbh | A method of removing an organic material coating adhered to the surface of a tinned steel sheet |
WO2017210315A1 (en) | 2016-05-31 | 2017-12-07 | Corning Incorporated | Anti-counterfeiting measures for glass articles |
EP3796116A3 (en) | 2016-09-15 | 2021-06-23 | IO Tech Group, Ltd. | Method and system for additive-ablative fabrication |
US10899940B2 (en) * | 2017-01-25 | 2021-01-26 | Xerox Corporation | Interlayer printing process |
US11009760B2 (en) | 2017-05-05 | 2021-05-18 | Gentex Corporation | Interleaving laser ablation |
US10563014B2 (en) * | 2017-09-11 | 2020-02-18 | Fujifilm Electronic Materials U.S.A., Inc. | Dielectric film forming composition |
BR112020026480A2 (en) | 2018-11-16 | 2021-05-18 | Illumina, Inc. | Laminated fluidic circuit apparatus and method for a fluid cartridge |
JP6911003B2 (en) * | 2018-12-14 | 2021-07-28 | Tdk株式会社 | Method of manufacturing element array and method of removing specific element |
CN114322741A (en) * | 2021-12-14 | 2022-04-12 | 厦门大学 | Laser pyrolysis composite additive manufacturing integrated precursor ceramic thin film sensor and preparation method thereof |
CN114523196B (en) * | 2022-04-22 | 2022-07-15 | 武汉铱科赛科技有限公司 | Blind hole drilling method, equipment, device and system with selective laser absorption |
Citations (39)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4081653A (en) | 1976-12-27 | 1978-03-28 | Western Electric Co., Inc. | Removal of thin films from substrates by laser induced explosion |
US4684437A (en) | 1985-10-31 | 1987-08-04 | International Business Machines Corporation | Selective metal etching in metal/polymer structures |
US5446521A (en) | 1993-06-30 | 1995-08-29 | Intel Corporation | Phase-shifted opaquing ring |
JPH09293891A (en) | 1996-04-26 | 1997-11-11 | Sanyo Electric Co Ltd | Removal of metal film, manufacture of solar battery and solar battery |
US5723236A (en) | 1995-05-31 | 1998-03-03 | Sharp Kabushiki Kaisha | Photomasks and a manufacturing method thereof |
JPH10263871A (en) | 1997-03-24 | 1998-10-06 | Shinko Electric Ind Co Ltd | Manufacture of dielectric mask for laser machining |
WO1998053510A1 (en) | 1997-05-21 | 1998-11-26 | Cambridge Display Technology Ltd. | Patterning organic light-emitting devices |
WO1999010939A2 (en) | 1997-08-22 | 1999-03-04 | Koninklijke Philips Electronics N.V. | A method of manufacturing a field-effect transistor substantially consisting of organic materials |
JPH11123884A (en) | 1997-10-24 | 1999-05-11 | Toray Ind Inc | Manufacture of original plate for direct-description type waterless lithographic printing plate |
US5972543A (en) | 1995-08-04 | 1999-10-26 | Dai Nippon Printing Co., Ltd. | Phase shift mask and method of producing the same |
JPH11320166A (en) | 1998-05-21 | 1999-11-24 | Ricoh Microelectronics Co Ltd | Light processing device |
JP2000208794A (en) | 1999-01-19 | 2000-07-28 | Fuji Electric Co Ltd | Method of laser patterning pattern-shaped thin film of thin-film solar cell or the like |
WO2001047043A1 (en) | 1999-12-21 | 2001-06-28 | Plastic Logic Limited | Solution processed devices |
US20010015438A1 (en) * | 1999-03-09 | 2001-08-23 | International Business Machines Corporation | Low temperature thin film transistor fabrication |
US6285001B1 (en) * | 1995-04-26 | 2001-09-04 | 3M Innovative Properties Company | Method and apparatus for step and repeat exposures |
US6399258B2 (en) * | 1999-01-14 | 2002-06-04 | 3M Innovative Properties Company | Method for patterning thin films |
US20020102478A1 (en) | 1992-12-07 | 2002-08-01 | Hitachi, Ltd. | Photomask and pattern forming method employing the same |
JP2003133690A (en) | 2001-10-26 | 2003-05-09 | Matsushita Electric Works Ltd | Method for forming circuit by using ultra short pulse laser |
WO2003041185A2 (en) | 2001-11-05 | 2003-05-15 | 3M Innovative Properties Company | Organic thin film transistor with polymeric interface |
JP2003258256A (en) | 2002-02-27 | 2003-09-12 | Konica Corp | Organic tft device and its manufacturing method |
WO2003080285A1 (en) | 2002-03-21 | 2003-10-02 | Louis Pöhlau Lohrentz | Device and method for laser structuring functional polymers and the uses thereof |
JP2003309266A (en) | 2002-04-17 | 2003-10-31 | Konica Minolta Holdings Inc | Method for manufacturing organic thin-film transistor element |
JP2004508731A (en) | 2000-09-11 | 2004-03-18 | シーメンス アクチエンゲゼルシヤフト | Use of organic rectifiers, circuits, RFID tags, and organic rectifiers |
US6719916B2 (en) * | 2001-04-18 | 2004-04-13 | National Research Council Of Canada | Multilayer microstructures and laser based method for precision and reduced damage patterning of such structures |
US20040075120A1 (en) | 2002-10-17 | 2004-04-22 | Xerox Corporation | Process and device using gelable composition |
JP2004179542A (en) | 2002-11-28 | 2004-06-24 | National Institute Of Advanced Industrial & Technology | Organic thin-film transistor and manufacturing method of the same |
US20040137142A1 (en) * | 2002-11-14 | 2004-07-15 | Ryuji Nishikawa | Method for manufacturing organic electroluminescence panel |
WO2004060600A2 (en) | 2003-01-03 | 2004-07-22 | Cambridge Display Technology Limited | Ablation methods and apparatus |
EP1443556A2 (en) * | 2003-01-28 | 2004-08-04 | Seiko Epson Corporation | Method of manufacturing thin film element, thin film transistor circuit substrate, active matrix display device, electro-optical device, and electronic apparatus |
US20040149986A1 (en) * | 2002-04-16 | 2004-08-05 | Dubowski Jan J. | Multilayer microstructures and laser based method for precision and reduced damage patterning of such structures |
US20040155948A1 (en) * | 2003-02-11 | 2004-08-12 | Laurian Dinca | Compensating mechanical image stretch in a printing device |
JP2004306127A (en) | 2003-04-10 | 2004-11-04 | Matsushita Electric Ind Co Ltd | Processing method for patterning thin film |
US20050009248A1 (en) * | 2003-07-09 | 2005-01-13 | Weng Jian-Gang | Solution-processed thin film transistor formation method |
JP2005081420A (en) | 2003-09-10 | 2005-03-31 | Sony Corp | Thin film deposition/removal device, and thin film deposition/removal method |
US20050211975A1 (en) | 2004-03-26 | 2005-09-29 | Hitachi, Ltd. | Thin film transistor and semiconductor device using the same |
US20050279999A1 (en) | 2004-06-17 | 2005-12-22 | Hun-Jung Lee | Thin film transistor, method of fabricating the same, and flat panel display having the same |
EP1897157A2 (en) | 2005-06-01 | 2008-03-12 | Plastic Logic Limited | Layer-selective laser ablation patterning |
US20090009812A1 (en) | 2004-11-29 | 2009-01-08 | Plastic Logic Limited | Distortion Compensation for Printing |
US20090212292A1 (en) | 2005-06-01 | 2009-08-27 | Carl Hayton | Layer-selective laser ablation patterning |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06267986A (en) * | 1993-03-17 | 1994-09-22 | Hitachi Ltd | Method of manufacturing thin film transistor |
JPH07276508A (en) * | 1994-04-05 | 1995-10-24 | Shinozaki Seisakusho:Kk | Method for boring fine hole on polymer resin material |
JPH086070A (en) * | 1994-06-16 | 1996-01-12 | Hitachi Ltd | Production of liquid crystal display element |
NO314525B1 (en) * | 1999-04-22 | 2003-03-31 | Thin Film Electronics Asa | Process for the preparation of organic semiconductor devices in thin film |
JP4653867B2 (en) * | 1999-06-30 | 2011-03-16 | エーユー オプトロニクス コーポレイション | Defect repair method for electronic components |
JP2003209365A (en) * | 2002-01-17 | 2003-07-25 | Mitsubishi Gas Chem Co Inc | Method for forming through-hole on multilayer double side copper-plated board by laser |
JP2004031933A (en) * | 2002-05-09 | 2004-01-29 | Konica Minolta Holdings Inc | Method for manufacturing organic thin-film transistor, and organic thin-film transistor and organic transistor sheet manufactured using the same |
JP2004235495A (en) * | 2003-01-31 | 2004-08-19 | Toppan Printing Co Ltd | Material machining method by ultra-short pulse laser |
TWI232934B (en) * | 2003-11-19 | 2005-05-21 | Ind Tech Res Inst | A biochip containing splitable reaction confinement and method for producing same and application thereof |
-
2005
- 2005-06-01 GB GBGB0511132.3A patent/GB0511132D0/en not_active Ceased
- 2005-07-08 GB GBGB0513915.9A patent/GB0513915D0/en not_active Ceased
-
2006
- 2006-05-30 US US11/915,731 patent/US9209400B2/en active Active
- 2006-05-30 CN CN200680028267.5A patent/CN101669224B/en active Active
- 2006-05-30 JP JP2008514206A patent/JP5342876B2/en not_active Expired - Fee Related
- 2006-05-30 EP EP12157149.1A patent/EP2463928B1/en active Active
- 2006-08-31 US US14/260,240 patent/USRE45885E1/en not_active Expired - Fee Related
-
2012
- 2012-12-25 JP JP2012281399A patent/JP5635066B2/en not_active Expired - Fee Related
-
2015
- 2015-10-21 US US14/919,056 patent/US20160111667A1/en not_active Abandoned
Patent Citations (42)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4081653A (en) | 1976-12-27 | 1978-03-28 | Western Electric Co., Inc. | Removal of thin films from substrates by laser induced explosion |
US4684437A (en) | 1985-10-31 | 1987-08-04 | International Business Machines Corporation | Selective metal etching in metal/polymer structures |
US20020102478A1 (en) | 1992-12-07 | 2002-08-01 | Hitachi, Ltd. | Photomask and pattern forming method employing the same |
US5446521A (en) | 1993-06-30 | 1995-08-29 | Intel Corporation | Phase-shifted opaquing ring |
US6285001B1 (en) * | 1995-04-26 | 2001-09-04 | 3M Innovative Properties Company | Method and apparatus for step and repeat exposures |
US5723236A (en) | 1995-05-31 | 1998-03-03 | Sharp Kabushiki Kaisha | Photomasks and a manufacturing method thereof |
US5972543A (en) | 1995-08-04 | 1999-10-26 | Dai Nippon Printing Co., Ltd. | Phase shift mask and method of producing the same |
JPH09293891A (en) | 1996-04-26 | 1997-11-11 | Sanyo Electric Co Ltd | Removal of metal film, manufacture of solar battery and solar battery |
JPH10263871A (en) | 1997-03-24 | 1998-10-06 | Shinko Electric Ind Co Ltd | Manufacture of dielectric mask for laser machining |
WO1998053510A1 (en) | 1997-05-21 | 1998-11-26 | Cambridge Display Technology Ltd. | Patterning organic light-emitting devices |
WO1999010939A2 (en) | 1997-08-22 | 1999-03-04 | Koninklijke Philips Electronics N.V. | A method of manufacturing a field-effect transistor substantially consisting of organic materials |
JPH11123884A (en) | 1997-10-24 | 1999-05-11 | Toray Ind Inc | Manufacture of original plate for direct-description type waterless lithographic printing plate |
JPH11320166A (en) | 1998-05-21 | 1999-11-24 | Ricoh Microelectronics Co Ltd | Light processing device |
US6399258B2 (en) * | 1999-01-14 | 2002-06-04 | 3M Innovative Properties Company | Method for patterning thin films |
JP2000208794A (en) | 1999-01-19 | 2000-07-28 | Fuji Electric Co Ltd | Method of laser patterning pattern-shaped thin film of thin-film solar cell or the like |
US20010015438A1 (en) * | 1999-03-09 | 2001-08-23 | International Business Machines Corporation | Low temperature thin film transistor fabrication |
WO2001047043A1 (en) | 1999-12-21 | 2001-06-28 | Plastic Logic Limited | Solution processed devices |
JP2004508731A (en) | 2000-09-11 | 2004-03-18 | シーメンス アクチエンゲゼルシヤフト | Use of organic rectifiers, circuits, RFID tags, and organic rectifiers |
US6719916B2 (en) * | 2001-04-18 | 2004-04-13 | National Research Council Of Canada | Multilayer microstructures and laser based method for precision and reduced damage patterning of such structures |
JP2003133690A (en) | 2001-10-26 | 2003-05-09 | Matsushita Electric Works Ltd | Method for forming circuit by using ultra short pulse laser |
WO2003041185A2 (en) | 2001-11-05 | 2003-05-15 | 3M Innovative Properties Company | Organic thin film transistor with polymeric interface |
JP2005509298A (en) | 2001-11-05 | 2005-04-07 | スリーエム イノベイティブ プロパティズ カンパニー | Organic thin film transistor with polymer interface |
JP2003258256A (en) | 2002-02-27 | 2003-09-12 | Konica Corp | Organic tft device and its manufacturing method |
WO2003080285A1 (en) | 2002-03-21 | 2003-10-02 | Louis Pöhlau Lohrentz | Device and method for laser structuring functional polymers and the uses thereof |
US20050106507A1 (en) * | 2002-03-21 | 2005-05-19 | Adolf Bernds | Device and method for laser structuring functional polymers and the use thereof |
US20040149986A1 (en) * | 2002-04-16 | 2004-08-05 | Dubowski Jan J. | Multilayer microstructures and laser based method for precision and reduced damage patterning of such structures |
JP2003309266A (en) | 2002-04-17 | 2003-10-31 | Konica Minolta Holdings Inc | Method for manufacturing organic thin-film transistor element |
US20040075120A1 (en) | 2002-10-17 | 2004-04-22 | Xerox Corporation | Process and device using gelable composition |
US20040137142A1 (en) * | 2002-11-14 | 2004-07-15 | Ryuji Nishikawa | Method for manufacturing organic electroluminescence panel |
JP2004179542A (en) | 2002-11-28 | 2004-06-24 | National Institute Of Advanced Industrial & Technology | Organic thin-film transistor and manufacturing method of the same |
WO2004060600A2 (en) | 2003-01-03 | 2004-07-22 | Cambridge Display Technology Limited | Ablation methods and apparatus |
EP1443556A2 (en) * | 2003-01-28 | 2004-08-04 | Seiko Epson Corporation | Method of manufacturing thin film element, thin film transistor circuit substrate, active matrix display device, electro-optical device, and electronic apparatus |
US20040155948A1 (en) * | 2003-02-11 | 2004-08-12 | Laurian Dinca | Compensating mechanical image stretch in a printing device |
JP2004306127A (en) | 2003-04-10 | 2004-11-04 | Matsushita Electric Ind Co Ltd | Processing method for patterning thin film |
US20050009248A1 (en) * | 2003-07-09 | 2005-01-13 | Weng Jian-Gang | Solution-processed thin film transistor formation method |
JP2005081420A (en) | 2003-09-10 | 2005-03-31 | Sony Corp | Thin film deposition/removal device, and thin film deposition/removal method |
US20050211975A1 (en) | 2004-03-26 | 2005-09-29 | Hitachi, Ltd. | Thin film transistor and semiconductor device using the same |
US20050279999A1 (en) | 2004-06-17 | 2005-12-22 | Hun-Jung Lee | Thin film transistor, method of fabricating the same, and flat panel display having the same |
US20090009812A1 (en) | 2004-11-29 | 2009-01-08 | Plastic Logic Limited | Distortion Compensation for Printing |
EP1897157A2 (en) | 2005-06-01 | 2008-03-12 | Plastic Logic Limited | Layer-selective laser ablation patterning |
US20090212292A1 (en) | 2005-06-01 | 2009-08-27 | Carl Hayton | Layer-selective laser ablation patterning |
EP2463928A2 (en) | 2005-06-01 | 2012-06-13 | Plastic Logic Limited | Layer-selective laser ablation patterning |
Non-Patent Citations (37)
Title |
---|
Annex to Summons mailed Mar. 7, 2013 for European Application No. 06744335.8. |
Aug. 31, 2006 International Preliminary Report on Patentability for PCT/GB2006/050265. |
Bao, Z. et al., "High Performance Plastic Transistors Fabricated by Printing Techniques," Chem. Mat. 9, 1299-1301 (1997). |
Bao, Z., "Materials and Fabrication Needs for Low-Cost Organic Transistor Circuits" Advanced Materials 12, vol. 3, p. 227-230 (2000). |
Basting, "Excimer Laser Technology Laser Sources, Optics, Systems and Applications" Lambda Physik, 2001 p. 151. |
Brittain, S. et al., "Soft Lithography and Microfabrication" Physics World, vol. 11, No. 5, p. 31, (May 1998). |
Communication pursuant to Article 94(3) EPC issued on Apr. 12, 2013 for European Application No. 06 779 619.3. |
Communication pursuant to Article 94(3) EPC issued on Feb. 16, 2010 for European Application No. 06 7744 335.8-2203. |
Decision of Rejection mailed Jan. 22, 2013 for Japanese Application No. JP2008-514206. |
Decision to Refuse a European Patent Application issue on Jul. 16, 2013 for European Application No. 06 744 335.8-1552. |
Duan, X., "High performance thin film transistors assembled from semiconductor nanowires and nanoribbons " Nature 425, 274-278 (2003). |
English Translation of Chinese Office Action mailed on Oct. 29, 2012 for Chinese Application No. 2006-800282675. |
Examination Report mailed Nov. 30, 2011 for European Application No. 06744335.8. |
Extended Search Report for EP Application No. 12157149.1 dated May 22, 2014 in 10 pages. |
Ghandour et al., "Excimer ablation of ITO on flexible substrates for large format display", pp. 90-101, Proceedings 2002 SPIE, Photonics West. |
Haight, et al., "Femtosecond laser ablation and deposition of metal films on transparent substrates with applications in photomask repair", Proceedings of SPIE, vol. 5714, Mar. 21, 2005, pp. 24-36, XP055116749. |
Hosokawa, et al., "Femtosecond Multistep Laser Etching of Transparent Amorphous Organic Film", Japanese Journal of Applied Physics, Japan Society of Applied Physics, Tokyo JP, vol. 40, No. 10B, Part 2, Oct. 15, 2001, pp. L1116-L1118, XP001111222, ISSN: 0021-4922. |
International Preliminary Report on Patentability issued on Oct. 6, 2009 for International Application No. PCT/GB2006/050133. |
International Search Report issued in application No. PCT/GB2006/050265 on Nov. 27, 2006. |
International Search Report mailed Sep. 24, 2009 for International Application No. PCT/GB2006/050133. |
Jolic, et al., "Fabrication of three-dimensional inductor coil using excimer laser micromachining." Journal of Micromechanics and Microengineering, Institute of Physics Publishing, 13(5):782-789 (Sep. 1, 2003). |
Kagan, C.R. et al., "Organic-Inorganic Hybrid Materials as Semiconducting Channels in Thin-Film Field-Effect Transistors" Science 286, No. 5441, p. 946 (1999). |
Katz, H.E., "Organic molecular solids as thin film transistor semiconductors," J. Mater. Chem. vol. 7, Issue 3, p. 369-572 (1997). |
Laquindanum, J.G. et al., "Synthesis, Morphology, and Field-Effect Mobility of Anthradithiophenes" J. Am. Chem. Soc. 120, p. 664-672 (1998). |
Musaev, et al., "UV laser ablation of parylene films from gold substrates," National Nuclear Security Administration's Kansas City Plant, Department of Physics, University of Missouri-Kansas City, Kansas City, in 15 pages, 2011. |
Noach, et al., "Microfabrication of an electroluminescent of polymer light emitting diode pixel array", Applied Physics Letters, AIP, American Institute of Physics, Melville, NY,vol. 69, No. 24, Dec. 9, 1996, p. 3650, XP012016774, ISSN: 0003-6951. |
Notice of Reasons for Rejection issue on Jul. 3, 2012 for Japanese Patent Application No. 2008-514206. |
Notice of Reasons for Rejection issued on Aug. 7, 2012 for Japanese Patent Application No. 2010-529697. |
Notice of Reasons for Rejection mailed Mar. 4, 2014 for Japanese Application No. JP 2012-281399. |
Office Action issued on Feb. 13, 2013 for Korean Application No. 10-2007-7028115. |
Office Action issued on Nov. 2, 2010 for Chinese Application No. 200680028267.5. |
Ridley, B.A. et al., "All-Inorganic Field Effect Transistors Fabricated by Printing" Science 286, No. 5440, p. 746-749 (1999). |
Rogers, J.A. et al., "Low-Voltage 0.1 pm organic transistors and complementary inverter circuits fabricated with a low-cost form of near-field photolithography," Appl. Phys. Lett. 75, No. 7, p. 1010 (1999). |
Schaefer et al., "Ablation of PEDOT/PSS with excimer lasers for micro structuring of organic electronic devices," Synthetic Metals 161 (2011) pp. 1051-1057. |
Schrodner, et al., "Polymer field effect transistors made by laser patterning", Organic Electronics, Elsevier, Amsterdam, vol. 6, No. 4, May 31, 2005, pp. 161-167, XP027680009. |
Search Report under Section 17(5) issued on Nov. 9, 2005 for Patent Application GB 0513915.9. |
Wu et al., "Single-shot Excimer Laser Ablation of Thick Polymer Resists on Metallic Substrates", AMP Journal of Technology, vol. 1, pp. 69-79, Nov. 1991. |
Also Published As
Publication number | Publication date |
---|---|
EP2463928B1 (en) | 2016-11-09 |
JP2013118390A (en) | 2013-06-13 |
EP2463928A2 (en) | 2012-06-13 |
JP5635066B2 (en) | 2014-12-03 |
EP2463928A3 (en) | 2014-06-25 |
CN101669224A (en) | 2010-03-10 |
GB0513915D0 (en) | 2005-08-17 |
GB0511132D0 (en) | 2005-07-06 |
US20090212292A1 (en) | 2009-08-27 |
JP2009508321A (en) | 2009-02-26 |
JP5342876B2 (en) | 2013-11-13 |
US9209400B2 (en) | 2015-12-08 |
US20160111667A1 (en) | 2016-04-21 |
CN101669224B (en) | 2014-05-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
USRE45885E1 (en) | Laser ablation of electronic devices | |
EP1922775B1 (en) | Laser ablation of electronic devices | |
US8062984B2 (en) | Laser ablation of electronic devices | |
EP2005499B1 (en) | Techniques for device fabrication with self-aligned electrodes | |
EP1834358B1 (en) | Method of manufacturing an electronic device array | |
KR101366545B1 (en) | Layer-selective laser ablation patterning | |
EP1866965B1 (en) | Method of producing plurality of organic transistors using laser patterning | |
US8684779B2 (en) | Electrode patterning | |
EP1866981A1 (en) | Patterning metal layers | |
JP5514545B2 (en) | Distortion-tolerant processing |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: FLEXENABLE LIMITED, UNITED KINGDOM Free format text: CHANGE OF NAME;ASSIGNOR:PLASTIC LOGIC LIMITED;REEL/FRAME:036175/0809 Effective date: 20150130 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 8 |
|
FEPP | Fee payment procedure |
Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
LAPS | Lapse for failure to pay maintenance fees |
Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |