WO1999005855A1 - Contour emphasizing circuit - Google Patents
Contour emphasizing circuit Download PDFInfo
- Publication number
- WO1999005855A1 WO1999005855A1 PCT/JP1998/003317 JP9803317W WO9905855A1 WO 1999005855 A1 WO1999005855 A1 WO 1999005855A1 JP 9803317 W JP9803317 W JP 9803317W WO 9905855 A1 WO9905855 A1 WO 9905855A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- contour
- signal
- level
- unit
- coefficient
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/14—Picture signal circuitry for video frequency region
- H04N5/21—Circuitry for suppressing or minimising disturbance, e.g. moiré or halo
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/14—Picture signal circuitry for video frequency region
- H04N5/20—Circuitry for controlling amplitude response
- H04N5/205—Circuitry for controlling amplitude response for correcting amplitude versus frequency characteristic
- H04N5/208—Circuitry for controlling amplitude response for correcting amplitude versus frequency characteristic for compensating for attenuation of high frequency components, e.g. crispening, aperture distortion correction
Definitions
- a contour component is extracted from an input video signal (for example, a digital input video signal), and the extracted contour component is multiplied by a contour emphasis coefficient (a coefficient including 1) and added to the input video signal.
- a contour emphasis coefficient a coefficient including 1
- PDP display devices using a PDP plasma display panel
- LCD display devices using an LCD (liquid crystal display) panel have attracted attention.
- Such a display device is a direct drive method using a digitized video signal.
- a contour-enhancing circuit as shown in FIG. I was trying to get an enhanced video signal.
- the contour emphasizing circuit shown in FIG. 1 includes a contour extracting unit 10, a delay adjusting unit 12, and an adding unit 14.
- the contour extraction unit 10 is a 1-dot delay unit 18 and 20 that sequentially delays the digital luminance signal (an example of a video signal) Y input to the input terminal 16 by one dot, and inputs to the input terminal 16
- Adder 22 that adds the luminance signal Y and the output signal of the one-dot delay unit 20, a multiplier 24 that multiplies the sum of the adder 22 by a coefficient 14, and a one-dot delay unit
- a multiplier 26 that multiplies the output signal of 18 by a factor of 1 and outputs 2 and a subtractor 28 that subtracts the output signal of the multiplier 24 from the output signal of the multiplier 26 and the reference pixel
- the horizontal contour component (that is, high-frequency component) HE of the reference pixel is extracted from the pixels adjacent to the left and right (temporally before and after) of the pixel and output.
- the delay adjuster 12 inputs the timing at which the luminance signal Y input to the input terminal 16 is input to the adder 14 and the contour component HE extracted by the contour extractor 10 to the adder 14 In order to adjust the timing of the luminance signal Y, the luminance signal Y input to the input terminal 16 is output with a delay of a predetermined time.
- the adder 14 adds the luminance signal Y output from the delay adjuster 12 and the contour component HE extracted by the contour extractor 10, and adds the sum (Y + HE) to the luminance of the contour-emphasized brightness. Output to the output terminal 30 as a signal.
- the contour emphasis circuit shown in FIG. 1 uses the contour component HE extracted by the contour extraction unit 10 as it is, regardless of whether the luminance level of the luminance signal Y input to the input terminal 16 is high or low. Since the configuration is to output to 14, the following problems were encountered.
- the present invention has been made in order to solve the above-described problems, and an object of the present invention is to provide a contour emphasis circuit that can perform contour emphasis suitable for the brightness level of an input video signal. Disclosure of the invention
- An outline emphasizing circuit includes an outline extracting unit that extracts an outline component from an input video signal, a level determining unit that determines a luminance level of the input video signal, and a plurality of coefficients according to the determination signal of the level determining unit.
- a coefficient control unit that outputs the coefficient by multiplying this coefficient by the extracted contour component of the contour extraction unit, and adds the contour component output from the coefficient control unit to the input video signal to enhance the contour of the video signal. And an adder for outputting.
- the coefficient of the coefficient control unit is switched in a plurality of stages according to the determination signal of the level determination unit, the coefficient to be applied to the extracted contour component is also switched in a plurality of stages in accordance with the luminance level of the input video signal. For this reason, the contour component added to the input video signal can be controlled to a size suitable for the luminance level of the input video signal, and the contour can be emphasized to prevent an unnatural image.
- the level determination unit is configured by a decoder that decodes which of the n-level (n is an integer of 2 or more) luminance levels of the input video signal corresponds to the luminance level.
- N multipliers for multiplying the extracted contour component of the extractor by a coefficient corresponding to n levels of luminance levels and outputting the result, and coupled to the output side of each of the n multipliers to decode the decoding signal of the decoder to a gate control signal
- n OR gates connected to the output side of the n AND gates.
- the level determination unit is configured by a decoder that decodes the luminance level of the input video signal to which of the four divided luminance levels
- the coefficient control unit is used as an extracted contour component of the contour extraction unit.
- Four multipliers that multiply and output 1/8, 1/4, 1/2, and 1 coefficients, and are connected to the output side of each of the four multipliers to decode the decoding signal of the decoder with the gate control signal.
- four OR gates, and an OR gate connected to the output side of the four AND gates.
- the configuration of the contour extraction unit can be simplified by configuring the contour extraction unit with a horizontal contour component extraction unit that extracts a horizontal contour component from the input video signal.
- FIG. 1 is a block diagram showing a conventional example of a contour enhancement circuit.
- FIG. 2 is a block diagram showing an embodiment of the contour emphasizing circuit according to the present invention.
- FIG. 3 is a block diagram showing a specific example of a level determination unit and a coefficient control unit in FIG. BEST MODE FOR CARRYING OUT THE INVENTION
- FIG. 2 shows an embodiment of the contour emphasizing circuit according to the present invention, and the same parts as those in FIG.
- 10 is a contour extraction unit
- 12 and 13 are delay adjustment units
- 14 is an addition unit
- Reference numeral 15 denotes a level determination unit
- reference numeral 11 denotes a coefficient control unit.
- the contour extraction unit 10 sequentially delays the digital luminance signal (an example of a video signal) Y inputted to the input terminal 16 by one dot by one dot. , 20, an adder 22 that adds the luminance signal Y input to the input terminal 16 and the output signal of the 1-dot delay unit 20, and a multiplication that multiplies the addition value of the adder 22 by a coefficient 1Z4 and outputs the result.
- the digital luminance signal an example of a video signal
- a multiplier 26 that multiplies the output signal of the 1-dot delay unit 18 by a factor of 1 and outputs the result
- a subtractor 2 8 that subtracts the output signal of the multiplier 24 from the output signal of the multiplier 26 From the pixels adjacent to the left and right of the reference pixel, the horizontal contour component HE of the reference pixel is extracted and output.
- the level determination section 15 is configured to determine the luminance level of the luminance signal Y input to the input terminal 16 and output a corresponding determination signal. Specifically, as shown in FIG. 3, it is configured by a decoder 32 that decodes the luminance level of the luminance signal Y based on the value of the upper 3 bits of the 8-bit luminance signal Y. That is, the decoder 32 sets the upper 3 bits of the luminance signal Y input to the input terminal 16 to “00”, “001”, “0110 to 011”, and “100”.
- the coefficient control unit 17 switches the coefficient in accordance with the determination signal output from the level determination unit 15 via the delay adjustment unit 13, and switches the coefficient to the contour extraction unit 10. It is configured to output by multiplying the extracted contour component.
- the contour component HE extracted by the contour extraction unit 10 and input via the input terminal 34 has a value of 1/8, 1/4, 1/2, and 1 Four multipliers 3 6, 3 6 3 6, 3 6 4 that multiply and output the coefficients, and the output sides of these 4 multipliers 3 6 3 6 2 , 3 6:, 3 6 4 And AND gates 3 8 3 8 2 , 3 8 3 , 3 8 4 which are combined with the decoding signal of the decoder 3 2 as a gate control signal, and these 4 AND gates 3 8, 3 8 2 , 3 8, 3 consists of 8 4 Oage bets 4 coupled to the output side of the 0 Prefecture, and outputs the OR gate 4 0 contour component to the adder 1 4 from the output side through the output terminal 4 2.
- the delay adjuster 13 is configured to determine whether the timing at which the contour component HE extracted from the input luminance signal Y by the contour extractor 10 is input to the coefficient controller 17 and the determination signal of the level determiner 15 are In order to adjust the timing of input to the coefficient control unit 17, the determination signal of the level determination unit 15 is output with a predetermined delay.
- the adder 14 adds the contour component output from the coefficient control unit 17 to a signal obtained by delaying the luminance signal Y input to the input terminal 16 by the delay adjustment unit 12 for a predetermined time, and The added value is output to the output terminal 30 as a luminance signal whose outline is emphasized.
- the delay adjuster 12 receives the timing at which the luminance signal Y input to the input terminal 16 is input to the adder 14 and the contour component output from the coefficient controller 17 to the adder 14. In order to adjust the input timing, the luminance signal Y input to the input terminal 16 is output with a predetermined delay.
- the contour extraction unit 10 extracts a horizontal contour component HE from the 8-bit luminance signal Y input to the input terminal 16, and the extracted contour component HE is input to the coefficient control unit 17. I do.
- the decoder 32 and the coefficient control unit 17 are configured such that the luminance level of the 8-bit luminance signal Y input to the input terminal 16 is “0 0 to 1 F” (1 hexadecimal notation).
- the decoder 32 decodes that the luminance level is “0 to 1F” based on the value of the upper three bits of the luminance signal Y being “0000”, and outputs an H level signal from the output side. Output a signal. This output signal is delayed for a predetermined time by a delay adjuster 13 (not shown in FIG. 3) and input to the AND gate 38, and the AND gate 38 is turned on.
- the multiplier 36! In 1/8 contour component (HEZ8) passes through the AND gate 38 1, and inputs to the adder 14 via the OR gate 40 and output terminal 42.
- the decoder 32 decodes that the luminance level is “20 to 3F” based on the value of the upper 3 bits of the luminance signal Y being “001”, and outputs an H-level signal from the output side 2. This output signal is delayed for a predetermined time by the delay adjuster 13 and AND gated.
- the decoder 32 decodes that the luminance level is “40 to 7 F” based on the value of the upper 3 bits of the luminance signal Y being “0 10 to 01 1”, and outputs the H level from the output side 3. Output a signal.
- the decoder 32 decodes that the luminance level is “40 to 7F” based on the value of the upper 3 bits of the luminance signal Y being “0 10 to 01 1”, and outputs an H level signal from the output side. Is output. This output signal is inputted en Doge DOO 38 "this is delayed a predetermined time by the delay adjusting unit 1 3, to the AND gate 38 4 conductive.
- the multiplier 36 through 4 in 1x contour component (HE) is the AND gate 38 4, the input to the adder 14 and via Oage Ichito 40 and the output terminal 42 I do.
- the adder 14 is input to the input terminal 16 and Then, the contour component output from the coefficient control unit 17 is added to the luminance signal Y delayed by a predetermined time, and the added value is output to the output terminal 30 as a contour-enhanced luminance signal.
- the contour component HE No. 8
- the added value Y + HEZ8
- the luminance signal Y has a contour component (HE / 4), (HE / 2) or (HE) is added, and the added value (Y + HE / 4), (Y + HE / 2), or (Y + HE) is output to the output terminal 30 as a luminance signal whose outline is emphasized. Therefore, contour emphasis suitable for the luminance level of the luminance signal Y can be performed.
- the contour extracting unit is configured by the horizontal contour component extracting unit that extracts a horizontal contour component from the input video signal.
- the present invention is not limited to this. What is necessary is just to extract a contour component from a signal.
- the contour extraction unit is composed of a vertical contour component extraction unit that extracts a vertical contour component from the input video signal, or the contour extraction unit extracts horizontal and vertical contour components from the input video signal.
- the contour extraction unit extracts horizontal and vertical contour components from the input video signal.
- it can also be used for the case where it is composed of a vertical contour component extraction unit.
- the level determination unit is configured by a decoder that decodes which of the four levels of the luminance level of the input video signal corresponds to the luminance level
- the coefficient control unit is an extracted contour component of the contour extraction unit Multiplied by 1/8, 1/4, 1/2, and 1 and output, and the decoder's decoding signal is coupled to the output side of each of the four multipliers. Is described as a gate control signal, and an orgate coupled to the output side of the four AND gates has been described, but the present invention is not limited to this. .
- the level determination unit is configured by a decoder that decodes a luminance level of an input video signal to which of n-level (n is an integer of 2 or more) classified luminance levels
- a coefficient control unit includes: N multipliers for multiplying and outputting coefficients corresponding to the extracted contour components of the contour extraction unit, and n multipliers coupled to the respective output sides of the n multipliers to use the decoding signal of the decoder as a gate control signal And an orgate coupled to the output of these n AND gates It can also be used in some cases.
- the level determination unit is configured by a decoder
- the coefficient control unit is configured by a multiplier, an AND gate, and an OR gate
- the coefficient control unit may switch the coefficient in a plurality of stages according to the judgment signal of the level judgment unit, and multiply this coefficient by the extracted contour component of the contour extraction unit. Anything should be output.
- an edge component is extracted from an input video signal, the extracted edge component is multiplied by a coefficient for edge enhancement, added to the input video signal, and an edge that outputs an edge-enhanced video signal is output.
- contour emphasis suitable for the luminance level of the input video signal can be performed. For this reason, a large outline component is added to a ⁇ ⁇ image with a low luminance level to prevent an unnatural image due to overemphasizing the outline, and a small outline component is added to a bright image with a high luminance level. In addition, it can be used to prevent a predetermined contour from being emphasized.
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- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Picture Signal Circuits (AREA)
- Liquid Crystal Display Device Control (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Controls And Circuits For Display Device (AREA)
- Image Processing (AREA)
Description
Claims
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2000-7000803A KR100538765B1 (ko) | 1997-07-25 | 1998-07-24 | 윤곽강조회로 |
AU83579/98A AU742007B2 (en) | 1997-07-25 | 1998-07-24 | Contour emphasizing circuit |
DE69835890T DE69835890T2 (de) | 1997-07-25 | 1998-07-24 | Konturbetonungsschaltung |
EP98933928A EP1011264B1 (en) | 1997-07-25 | 1998-07-24 | Contour emphasizing circuit |
CA002297957A CA2297957C (en) | 1997-07-25 | 1998-07-24 | Contour emphasizing circuit |
US11/063,238 US7321401B2 (en) | 1997-07-25 | 2005-02-22 | Contour emphasizing circuit |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9/213955 | 1997-07-25 | ||
JP21395597A JP3697844B2 (ja) | 1997-07-25 | 1997-07-25 | 輪郭強調回路 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1999005855A1 true WO1999005855A1 (en) | 1999-02-04 |
Family
ID=16647832
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP1998/003317 WO1999005855A1 (en) | 1997-07-25 | 1998-07-24 | Contour emphasizing circuit |
Country Status (11)
Country | Link |
---|---|
US (1) | US7321401B2 (ja) |
EP (1) | EP1011264B1 (ja) |
JP (1) | JP3697844B2 (ja) |
KR (1) | KR100538765B1 (ja) |
AU (1) | AU742007B2 (ja) |
CA (1) | CA2297957C (ja) |
DE (1) | DE69835890T2 (ja) |
ES (1) | ES2272002T3 (ja) |
RU (1) | RU2216118C2 (ja) |
TW (1) | TW401683B (ja) |
WO (1) | WO1999005855A1 (ja) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3804595B2 (ja) * | 2002-08-15 | 2006-08-02 | ソニー株式会社 | 映像信号処理方法及び装置 |
US7750945B2 (en) | 2004-10-13 | 2010-07-06 | Panasonic Corporation | Video signal processing device and image processing device |
KR101136220B1 (ko) * | 2005-05-17 | 2012-04-17 | 엘지디스플레이 주식회사 | 액정표시장치 |
JP2007127972A (ja) * | 2005-11-07 | 2007-05-24 | Toshiba Corp | 画像表示調整装置 |
JP4273428B2 (ja) * | 2006-01-31 | 2009-06-03 | ソニー株式会社 | 画像処理装置、画像処理方法、画像処理方法のプログラム及び画像処理方法のプログラムを記録した記録媒体 |
KR101244679B1 (ko) | 2006-07-27 | 2013-03-18 | 삼성전자주식회사 | 밝기에 따른 동적 이득 조절 방법 및 장치 |
US20110115815A1 (en) * | 2009-11-18 | 2011-05-19 | Xinyu Xu | Methods and Systems for Image Enhancement |
JP5743918B2 (ja) * | 2012-01-31 | 2015-07-01 | 株式会社東芝 | 画像処理装置 |
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JPS536523A (en) * | 1976-07-07 | 1978-01-21 | Matsushita Electric Ind Co Ltd | Picture quality adjuster |
JPS63164765A (ja) * | 1986-12-26 | 1988-07-08 | Matsushita Electric Ind Co Ltd | 画質補償装置 |
JPH03120962A (ja) * | 1989-10-04 | 1991-05-23 | Sony Corp | 固体撮像装置の映像信号処理回路 |
JPH04348671A (ja) * | 1991-05-27 | 1992-12-03 | Nec Yamagata Ltd | 輪郭補正回路 |
JPH06350877A (ja) * | 1993-06-08 | 1994-12-22 | Matsushita Electric Ind Co Ltd | 輪郭補償装置とその装置に用いる利得制御信号発生回路 |
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US3790700A (en) | 1971-12-17 | 1974-02-05 | Hughes Aircraft Co | Catv program control system |
JPH0396176A (ja) * | 1989-09-08 | 1991-04-22 | Kondeishiyonaru Akusesu Technol Kenkyusho:Kk | 映像雑音の抵減装置 |
KR930002906B1 (ko) * | 1989-12-23 | 1993-04-15 | 삼성전자 주식회사 | 윤곽 보정회로 |
JP2551205B2 (ja) | 1990-06-28 | 1996-11-06 | 日本ビクター株式会社 | 輪郭補正回路 |
KR920008630B1 (ko) * | 1990-09-28 | 1992-10-02 | 삼성전자 주식회사 | 수평윤곽 보상회로 |
KR0171366B1 (ko) * | 1991-10-28 | 1999-03-20 | 강진구 | 자동화질 보상회로 |
US5374995A (en) * | 1993-03-22 | 1994-12-20 | Eastman Kodak Company | Method and apparatus for enhancing sharpness of a sequence of images subject to continuous zoom |
JP3071131B2 (ja) * | 1995-09-05 | 2000-07-31 | 三洋電機株式会社 | ガンマ補正装置 |
US5923213A (en) | 1997-07-09 | 1999-07-13 | U.S. Philips Corporation | Digitally gain-controlled amplifying device, and camera using such a device |
-
1997
- 1997-07-25 JP JP21395597A patent/JP3697844B2/ja not_active Expired - Fee Related
-
1998
- 1998-07-24 WO PCT/JP1998/003317 patent/WO1999005855A1/ja active IP Right Grant
- 1998-07-24 KR KR10-2000-7000803A patent/KR100538765B1/ko not_active IP Right Cessation
- 1998-07-24 DE DE69835890T patent/DE69835890T2/de not_active Expired - Lifetime
- 1998-07-24 CA CA002297957A patent/CA2297957C/en not_active Expired - Fee Related
- 1998-07-24 EP EP98933928A patent/EP1011264B1/en not_active Expired - Lifetime
- 1998-07-24 AU AU83579/98A patent/AU742007B2/en not_active Ceased
- 1998-07-24 RU RU2000104520/09A patent/RU2216118C2/ru not_active IP Right Cessation
- 1998-07-24 TW TW087112186A patent/TW401683B/zh not_active IP Right Cessation
- 1998-07-24 ES ES98933928T patent/ES2272002T3/es not_active Expired - Lifetime
-
2005
- 2005-02-22 US US11/063,238 patent/US7321401B2/en not_active Expired - Fee Related
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Publication number | Priority date | Publication date | Assignee | Title |
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JPS536523A (en) * | 1976-07-07 | 1978-01-21 | Matsushita Electric Ind Co Ltd | Picture quality adjuster |
JPS63164765A (ja) * | 1986-12-26 | 1988-07-08 | Matsushita Electric Ind Co Ltd | 画質補償装置 |
JPH03120962A (ja) * | 1989-10-04 | 1991-05-23 | Sony Corp | 固体撮像装置の映像信号処理回路 |
JPH04348671A (ja) * | 1991-05-27 | 1992-12-03 | Nec Yamagata Ltd | 輪郭補正回路 |
JPH06350877A (ja) * | 1993-06-08 | 1994-12-22 | Matsushita Electric Ind Co Ltd | 輪郭補償装置とその装置に用いる利得制御信号発生回路 |
Non-Patent Citations (1)
Title |
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See also references of EP1011264A4 * |
Also Published As
Publication number | Publication date |
---|---|
US20050190301A1 (en) | 2005-09-01 |
US7321401B2 (en) | 2008-01-22 |
EP1011264A4 (en) | 2001-03-21 |
JPH1146312A (ja) | 1999-02-16 |
CA2297957C (en) | 2005-05-17 |
TW401683B (en) | 2000-08-11 |
DE69835890D1 (de) | 2006-10-26 |
AU742007B2 (en) | 2001-12-13 |
KR20010022230A (ko) | 2001-03-15 |
DE69835890T2 (de) | 2007-02-15 |
JP3697844B2 (ja) | 2005-09-21 |
AU8357998A (en) | 1999-02-16 |
EP1011264B1 (en) | 2006-09-13 |
CA2297957A1 (en) | 1999-02-04 |
RU2216118C2 (ru) | 2003-11-10 |
EP1011264A1 (en) | 2000-06-21 |
ES2272002T3 (es) | 2007-04-16 |
KR100538765B1 (ko) | 2005-12-26 |
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