WO1998025213A1 - Dispositif de circuit semi-conducteur integre - Google Patents

Dispositif de circuit semi-conducteur integre Download PDF

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Publication number
WO1998025213A1
WO1998025213A1 PCT/JP1996/003550 JP9603550W WO9825213A1 WO 1998025213 A1 WO1998025213 A1 WO 1998025213A1 JP 9603550 W JP9603550 W JP 9603550W WO 9825213 A1 WO9825213 A1 WO 9825213A1
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WO
WIPO (PCT)
Prior art keywords
chip
terminal
dram
integrated circuit
external connection
Prior art date
Application number
PCT/JP1996/003550
Other languages
English (en)
Japanese (ja)
Inventor
Koki Noguchi
Satoshi Michishita
Masashi Horiguchi
Masaharu Kubo
Toshio Miyamoto
Asao Nishimura
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Priority to PCT/JP1996/003550 priority Critical patent/WO1998025213A1/fr
Priority to AU10404/97A priority patent/AU1040497A/en
Priority to JP52543298A priority patent/JP3942198B2/ja
Priority to TW086100626A priority patent/TW326104B/zh
Publication of WO1998025213A1 publication Critical patent/WO1998025213A1/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4239—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with asynchronous protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7839—Architectures of general purpose stored program computers comprising a single central processing unit with memory
    • G06F15/7842—Architectures of general purpose stored program computers comprising a single central processing unit with memory on one IC chip (single chip microcontrollers)
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Definitions

  • the present invention relates to a semiconductor integrated circuit device in which a plurality of types of semiconductor chips are housed in a single package so that signals can be input and output from each other from an MCM (Multi Chip Module) -like approach.
  • Microcomputer including a processing unit, programmable nonvolatile memory such as flash memory, and logic LSI such as DRAM (Dynamic Random Access Memory) and As IC (Application Specific Integrated Circuit.)
  • the present invention relates to a technology that is effective when applied to a semiconductor integrated circuit device.
  • the inventor of the present invention has realized an approach of DRAM 'SIMM (Single In-line memory Module), a flash memory and a DRAM microcomputer-on-chip with high customer needs.
  • DRAM 'SIMM Single In-line memory Module
  • flash memories, DRAMs, AS ICs, etc. all in one chip
  • multiple types of semiconductor chips can be housed in a single package from an MCM-like approach to enable signal input and output to and from each other.
  • the technology was considered. The following is the technology studied by the present inventors, and the outline is as follows.
  • a p-type impurity (boron) is ion-implanted into the main surface of the semiconductor substrate 100 to form a p-type well 101, and then a field is formed on the surface of the p-type well 101 by the LOCOS method.
  • An oxide film 102 is formed.
  • the element formed at the left end of the figure is the MOS FET that forms the memory cell of the DRAM, and the element that is formed to the right is the MOS FET that forms the memory cell of the flash memory and a part of the peripheral circuit of the flash memory.
  • the element at the right end is the MOS FET that constitutes a logic LSI such as a microcomputer or AS IC.
  • the actual LSI is mainly composed of an n- channel MOS FET and a p-channel MOS FET. For simplicity of explanation, only the region where the n- channel MOS FET is formed is shown. .
  • a tunnel oxide film 1 ⁇ 3 of the flash memory is formed.
  • the thickness of the tunnel oxide film 103 is set to about 8 to 13 plates.
  • the polycrystalline silicon film deposited by the CVD method on the semiconductor substrate 100 is patterned to form (part of) the floating gate 104 of the flash memory.
  • a second gate insulating film (ONO film) 105 having a thickness of about 10 to 30 nm is formed by stacking a silicon oxide film, a silicon nitride film, and a silicon oxide film thereon.
  • a gate oxide film 1 ⁇ 6 of a high breakdown voltage MOSFET is formed in the peripheral circuit region of the flash memory.
  • the gate oxide film 106 is formed to have a larger thickness (10 to 30 nm) than the gate oxide films of other MOS FETs in order to increase the breakdown voltage.
  • a gate oxide film 107 of the MOS FET constituting the logic LSI and a gate oxide film 130 of the VIOS FET constituting the memory cell of the DRAM are formed.
  • the thickness of the gate oxide film 107 is about 4 to 10 nm, and the thickness of the gate oxide film 130 is about 8 to 15 nm.
  • the polycrystalline silicon film deposited by the CVD method on the semiconductor substrate 100 is patterned to form the gate electrode (lead line) 108 of the DRAM memory cell and the flash memory.
  • the gate electrode 110 and the gate electrode 111 of the MOS FET that constitutes the logic LSI are formed simultaneously, the (partially formed) floating gate 104 of the flash memory is patterned as shown in Figure 85. To form a floating gate 104.
  • n-type impurities phosphorus and arsenic
  • n-type impurities are ion-implanted into a part of the memory cell region of the flash memory to form an n + type semiconductor region 112 of the flash memory.
  • n-type impurities are ion-implanted into a part of the memory cell area of the flash memory, the peripheral circuit area, and the logic LSI formation area, and the n-type semiconductor area of the flash memory is formed.
  • the gate electrode (word line) 108 of the DRAM memory cell, the control gate 109 of the flash memory, the gate electrode 110 of the high-voltage MOSFET, and the logic LSI A side-effect spacer 114 is formed on the side wall of the gate electrode 111 of the M ⁇ S FET to be constituted.
  • an n-type impurity (phosphorous or arsenic) is implanted into a part of the memory cell area of the flash memory, the peripheral circuit area, and the logic LSI forming area, thereby forming the flash memory.
  • n + -type semiconductor region 115, n-type semiconductor region 115, 1.15 of high-voltage MOS FET, and n'-type semiconductor region 1 115, 115 of MOS SFET constituting logic LSI By forming one of the source and drain regions of the flash memory, the source region of the high voltage MOS FET, the drain region and the source and drain regions of the MOS FET that constitutes the logic LSI, an LDD (Lightly Doped Drain) Make structure,: ,
  • the silicon oxide film 116 deposited on the semiconductor substrate 1 • 0 by CVD is etched to form connection holes on both sides of the DRAM gate electrode (word line).
  • word line After connecting holes are formed on the n + type semiconductor region 112 of the flash memory, plugs 117 of a polycrystalline silicon film are formed on the other side of these connecting holes.
  • an n-type semiconductor region 118 is formed by impurities diffused from this polycrystalline silicon film.
  • the polycrystalline silicon film deposited by the CVD method is patterned to form bit lines BL for DRAM and bit lines BL for flash memory.
  • the polycrystalline silicon film deposited on the silicon oxide film 119 is patterned. To form the lower electrode 120 of the DRAM capacitor.
  • the tantalum oxide film (or silicon nitride film) and the polycrystalline silicon film deposited on the semiconductor substrate 100 are patterned to form a capacitor insulating film for a DRAM capacitor.
  • an upper electrode 122 and a silicon oxide film 123 on the semiconductor substrate 100 by the CVD method as shown in FIG. 93 an A1 film deposited on the silicon oxide film 123 is formed.
  • a first layer metal wiring 124 is formed.
  • a silicon oxide film 125 is deposited on the semiconductor substrate 100 by a CVD method, and then the A 1 film deposited on the silicon oxide film 125 is patterned to form a second layer metal wiring. Form one 26.
  • the gate oxide of the MOS FET in the DRAM section needs to be somewhat thicker than the gate oxide of the MOS FET in the logic section in consideration of withstand voltage.
  • the gate oxide film of the high breakdown voltage MOS FET of the flash memory to which the high breakdown voltage is applied needs to be further thickened in order to secure a sufficient breakdown voltage. That is, when DRAM, logic, and flash memory are mixed, a gate oxide film having a different thickness is required depending on the required power supply level, so that the number of steps and the number of masks are greatly increased.
  • the DRAM is composed of one transistor + one capacitor, high-temperature heat treatment (heat treatment for stabilizing the tantalum oxide film or high-temperature nitridation treatment for forming a silicon nitride film) is performed when forming the capacitor. It is necessary to set the gate length of the part slightly longer. However, increasing the gate length of the logic section sacrifices the speed of the mouthpiece. (3) The elevation of the DRAM part on the semiconductor chip is higher than that of the logic part, and a step is created between the two parts, which adversely affects the wiring formation. In particular, this tendency is remarkable in the case of a DRAM employing a stacked capacitor structure.
  • a third object of the present invention is to reduce the number of external connection terminals in a circuit structure by a functional block configuration in a package structure in which two types of semiconductor chips of a CPU and a flash memory and a DRAM are packaged.
  • An object of the present invention is to provide a semiconductor integrated circuit device capable of reducing the mounting area by integrating one type of semiconductor chip into a single package and enabling the cost of a microcomputer system to be reduced. Further, one object of the present invention is to provide a common external connection terminal when each semiconductor chip has a built-in logic circuit such as an ASIC, and when the DRAM is a synchronous DRAM. Therefore, an object of the present invention is to provide a semiconductor integrated circuit device capable of further reducing the number of external connection terminals and reducing the cost.
  • Another object of the present invention is to provide the above-described semiconductor integrated circuit device at a low cost.
  • a so-called microcomputer equipped with a flash memory having a CPU and a flash memory for example, a so-called microcomputer equipped with a flash memory having a CPU and a flash memory.
  • a semiconductor chip called a DRAM chip and a semiconductor chip called a DRAM on-chip logic which is equipped with a DRAM and a logic circuit such as an AS IC.
  • Operation measures between the microcomputer with memory and the DRAM on-chip logic are indispensable.
  • the data transfer speed between the CPU operation of the computer with the flash memory equipped microphone and the access operation to the DRAM of the DRAM on-chip logic from the CPU on the DRAM and the access operation for the DRAM from the logic circuit inside the DRAM on-chip logic Measures are required.
  • the direct connection interface of the DRAM can be used to connect at high speed.
  • the logic circuit of the chip logic wants to access the DRAM
  • the first method is to return a wait signal to the CPU when the logic circuit is operating.
  • the memory between the microcomputer equipped with flash memory and the DRAM on-chip logic must be asynchronous, one clock cycle cannot be transferred, that is, the wait signal is viewed. Since there is no time, it is a two-cycle data transfer.
  • the logic circuit of the DRAM on-chip logic outputs a request signal requesting the CPU to open the bus, and the CPU does nothing while the bus is open to the logic circuit. Because of this, the overhead of arbitration becomes large and the CPU itself cannot control time.
  • the present inventor focused on the fact that it is preferable that the CPU of the microcomputer equipped with the flash memory control the time itself, and sets the DRAVI self-refresh period as viewed from the CPU of the computer with the microphone memory equipped with the flash memory. It is used effectively to enable the DRAM self-refresh operation, and during this self-refresh period, the logic inside the DRAM on-chip logic is It was conceived that by making it possible to access DRAM from a memory circuit, it would be possible to increase the speed of data transfer between a microcomputer equipped with flash memory and DRAM on-chip logic.
  • One object of the present invention is to provide a semiconductor chip on which a DRAM and a logic circuit such as an ASIC are mounted by effectively utilizing a self-refresh period of the DRAM viewed externally without the need for weight control.
  • the purpose of the present invention is to provide a semiconductor integrated circuit device that enables access operation from a logic circuit to a DRAM during a self-refresh period, thereby realizing high-speed data transfer between an external device and a semiconductor chip.
  • the weight control is not required and the CPU is not required.
  • the present invention provides a semiconductor integrated circuit device that enables an access operation from a logic circuit to a DRAM during a DRAM self-refresh period, thereby realizing high-speed data transfer between semiconductor chips.
  • a semiconductor integrated circuit device which does not require weight control for exchanging weight signals and can control processing timing itself from a CPU, thereby facilitating program creation. It is in.
  • a semiconductor chip equipped with a DRAM and a logic circuit can be directly connected to a semiconductor chip equipped with a CPU and a flash memory to enable high-speed operation. It is an object of the present invention to provide a semiconductor integrated circuit device that can achieve the above.
  • one semiconductor integrated circuit device of the present invention has at least a CPU and a flash memory.
  • the plurality of second semiconductor chips are housed in the same package so that signals can be input / output to each other, and the plurality of connection terminals of the first semiconductor chip and the one or more second semiconductor chips And a plurality of external connection terminals respectively connected to the plurality of connection terminals.
  • At least a DRAM and a logic circuit are formed on the one or more second semiconductor chips.
  • At least a DRAM and a logic circuit are formed on the first semiconductor chip.
  • the semiconductor integrated circuit device may include a plurality of connection terminals of the first semiconductor chip and a plurality of connection terminals of the one or more second semiconductor chips, among the plurality of external connection terminals.
  • the common external connection terminal commonly assigned is an address terminal, a data input / output terminal, a power supply terminal, The ground terminal, the address strobe terminal, the write enable terminal, the output enable terminal, and the interrupt terminal, and the same external connection terminal commonly assigned are standardized to bus specifications.
  • the DRAM is a synchronous DRAM, and a clock terminal of the first semiconductor chip and a clock terminal of the one or more second semiconductor chips are the same as the plurality of external connection terminals.
  • the DRAM is commonly assigned to the external connection terminal, and the DRAM is a synchronous DRAM or an EDO-DRAM.
  • the two types of semiconductor chips that is, the semiconductor chip using the CPU and the flash memory and the semiconductor chip using the DRAM, are packaged into a package structure.
  • the number of external connection terminals can be reduced, and the mounting area can be reduced by combining two types of semiconductor chips into one package, reducing the cost of microcomputer systems. It can be.
  • the number of external connection terminals can be further increased because the external connection terminals can be further shared. And cost can be reduced.
  • One semiconductor integrated circuit device of the present invention includes a semiconductor chip on which at least a DRAM and a logic circuit are formed, and the logic circuit controls at least an access operation of a write operation and a read operation of the DRAM.
  • Both control means capable of executing a refresh operation Z access operation during the self-refresh operation of the DRAM and processing data stored in the DRAM and processing of data stored in the DRAM Processing means for outputting a write request Z read request to the control means.
  • one semiconductor integrated circuit device of the present invention includes a first semiconductor chip on which at least a CPU and a flash memory are formed, and one or more second semiconductor chips on which at least a DRAM and a logic circuit are formed.
  • the first semiconductor chip and the one or more second semiconductor chips are housed in the same package so that signals can be input and output to and from each other, and A second semiconductor chip having a plurality of external connection terminals connected to the plurality of connection terminals of the first semiconductor chip and the plurality of connection terminals of the one or more second semiconductor chips, respectively;
  • the logic circuit of the semiconductor chip controls at least an access operation of a write operation / read operation to the DRAM, and a refresh operation / flash at the time of the self-refresh operation of the DRAM.
  • control unit executes the DRAM as a memory function during a normal access operation, and executes a refresh operation no access operation according to a request of the processing unit during a self refresh operation:
  • the execution of the refresh operation / access operation at the time of the self-refresh operation is performed by a write request of the processing unit,
  • the access operation is repeated according to the read request, and the refresh operation is performed during a period between the write operation and the read operation.
  • the control means may include an access period for executing a normal write operation / read operation for the DRAM based on an externally input address strobe signal, and a self-refresh permission output to the processing means.
  • a self-refresh period in which a refresh operation no-access operation is performed by inputting a write request signal Z read request signal in response to a signal is set.
  • the self refresh period is a write access period in which a write operation is performed with a write request signal from the processing unit as an input, and a read access period in which a read operation is performed with a read request signal from the processing unit as an input.
  • a refresh period for performing a refresh operation in a period excluding the write access period and the read access period.
  • a data width of an internal data bus of the semiconductor chip is wider than a data width of a data input / output terminal of an external connection terminal of the semiconductor chip.
  • the interface of the semiconductor chip is standardized to the interface specification of the semiconductor chip including only the DRAM.
  • the DRAM is a synchronous DRAM or EDO-DRAM.
  • a semiconductor chip equipped with a DRAM and a logic circuit can be directly connected to a semiconductor chip equipped with a CPU and a flash memory to enable high-speed operation. Can be.
  • FIGS. 1 to 6 are schematic configuration diagrams showing a configuration example of a semiconductor integrated circuit device according to an embodiment of the present invention.
  • FIGS. 7 to 14 constitute a semiconductor integrated circuit device according to an embodiment of the present invention.
  • FIGS. 15 to 18 are explanatory diagrams showing a list of example terminal functions of a semiconductor chip
  • FIGS. Connection diagram showing an example of chip connection Figure 21 is a schematic configuration diagram schematically showing an example of the internal functions of a semiconductor chip
  • Figure 22 is a configuration diagram showing a detailed example of a DRAM access control unit
  • Figure 23 is an internal diagram FIG.
  • FIG. 24 is an explanatory diagram showing an example of a transition state of an operation mode by a control signal generation circuit.
  • FIG. 24 is an operation timing diagram showing a control example of a DRAM access control unit for DRAM
  • FIG. 25 is an embodiment of the present invention.
  • Figure 26 is an overall perspective view of the package
  • Figure 26 is a cross-sectional view of this package
  • Figure 27 Is a plan view showing a lead pattern formed on one surface of the tape carrier
  • FIGS. 29 to 37 are cross-sectional views showing a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.
  • 38 to 66 are cross-sectional views showing another method of manufacturing the semiconductor integrated circuit device, FIGS.
  • FIGS. 67 to 69 are plan views showing the pattern of the leads formed on one surface of the tape carrier
  • FIGS. FIG. 72 is a cross-sectional view showing another embodiment of this semiconductor integrated circuit device
  • FIGS. 73 to 77 are functional block diagrams showing a system configuration example using the semiconductor integrated circuit device of this embodiment
  • FIGS. 78 to 94 are cross-sectional views showing the microcomputer, flash memory, DRAM, and ASIC mixed processes studied by the present inventors.
  • the semiconductor integrated circuit device is, for example, an LSI package having a stacked structure in which a plurality of types of semiconductor chips are connected to each other so as to be able to input and output signals.
  • a chip IF first semiconductor chip
  • a logic circuit A and a chip AD (second semiconductor chip) called a so-called DRAM chip logic are mounted.
  • the connection terminals of each chip MF and chip AD are connected to the package. Internally, they are connected to each other via a bus, and are connected to external connection terminals that enable external connections.
  • the flash memory F is a programmable non-volatile memory, which is one of the LSI memories, and is a memory in which writing or erasing is performed by applying a high voltage to a memory cell.
  • DRAMD is a type of LSI memory that needs to supply a control (refresh) signal for repeated data reproduction in order to retain the contents of data.
  • AS ICs are special-purpose ICs or dedicated ICs, and are different from general-purpose LSIs sold in the general market, such as large-capacity memory LSIs and microphone processor LSIs. And sell it.
  • a chip MF first semiconductor chip on which a microcomputer M including a CPU, a memory, a peripheral circuit, and the like and a flash memory F are mounted; It consists of a chip D (second semiconductor chip) on which only DRAMD is mounted, and has a configuration in which the logic circuit A such as an AS IC is removed from the second semiconductor chip in the configuration example of FIG.
  • a microphone memory computer M including a CPU, a memory and peripheral circuits, a flash memory F, and a logic circuit A are mounted.
  • the configuration example shown in Fig. 2 consists of a chip MFA (first semiconductor chip) called an on-chip logic microcomputer and a chip D (second semiconductor chip) equipped with only DRAMD.
  • the first semiconductor chip is equipped with a logic circuit A such as an AS IC.
  • FIG. 1 when a chip MFA and a chip AD are configured as shown in FIG. 4, as a modified example of FIG. 2, one chip MF and a plurality of chips are arranged as shown in FIG.
  • FIG. 2 In the case of the configuration including the chip D, a configuration example such as the configuration including the chip MFA and the plurality of chips D as shown in FIG.
  • the chip AD and the chip D are easily connected directly to the chip MF and the chip MFA by the general-purpose DRAM interface specifications, and the DR AMD is used as an extended memory in each semiconductor integrated circuit device. Further, the logic circuit A such as the ASIC of the chip AD can control the access to the DRAM inside the chip AD independently of the access control by the CPU of the chip MF and the chip MFA.
  • FIGS. 15 to 18 show a list of examples of the terminal functions of the chip MF.
  • FIG. 7 and 8 show examples of the 144-pin chip MF
  • FIG. 7 is a functional block diagram showing an example of the internal configuration
  • FIG. 8 is an explanatory diagram showing an example of the terminal functions.
  • Fig. 9, Fig. 10 Shows an example of the pin 112 of the chip MF
  • FIG. 9 is a functional block diagram showing an example of the internal configuration
  • FIG. 10 is an explanatory diagram showing an example of the terminal function.
  • the difference between the 144-pin chip MF and the 112-pin chip MF is that the external terminals of the data input / output correspond to the data width of 32 bits and 16 bits, respectively. 31 is the only difference between D0 and D15.
  • a 144-pin chip MF will be mainly described.
  • This 144-pin chip MF has at least a microcomputer and a flash memory, and has a circuit configuration having overall control and processing functions of the semiconductor integrated circuit device and a programmable memory function capable of electrically erasing all at once.
  • processor CPU flash memory F1ash, random access memory / cache memory RAM / Cache, data transfer controller DTC, direct memory access controller DMAC, State controller BSC, user break controller UBC, interrupt controller INTC, serial communication interface SCI, multifunction timer pulse unit MTU, conveyor match timer CMT, A / D converter A / D, watchdog timer WDT, Phase It consists of a NOREC loop circuit PLL.
  • the CPU is, for example, a central processing unit having an instruction set of the RISC type. Since this CPU basically operates in one instruction and one cycle, the instruction execution speed is dramatically improved, and the internal 32-bit configuration enhances the data processing capability.
  • the features of this CPU include a general-purpose register machine (16 general-purpose registers, 16 x 32 bits, 3 x 32-bit control registers, and 4 x 32 bits system registers), RI Instruction set compatible with SC (Improved code efficiency with 16-bit fixed instruction length, load-store architecture (basic operation is executed between registers), delay branch instructions reduce pipeline turbulence by adopting delayed branch instructions, C Language-oriented instruction set), instruction execution time is 1 instruction cycle (35 nsZ instruction at 28 MHz operation), address space is 4 GB architecturally, and built-in multiplier allows 32 x 32 ⁇ 64 multiplication by 2 ⁇ 4 cycle execution, 32 X 32 + 64 ⁇ 64 multiply-accumulate operation 2 ⁇ 4 cycle execution, 5 steps,
  • the flash memory F 1 ash is a circuit that incorporates, for example, a 64K-byte or 128-byte electrically erasable programmable memory.
  • the Fash is connected to the CPU, DMAC, and DTC via a 32-bit data bus, for example.
  • the CPU, DMAC, and DTC can access the F1ash in 8, 16 or 32 bits wide. This F 1 ash data can always be accessed in one state.
  • the random access memory / cache memory RAM / Cache is, for example, a memory composed of a 4 KB random access memory RAVI and a 1 KB cache memory Cache.
  • the features of this cache are instruction code and PC relative reading, data caching, line length is 4 bytes (1 long word is 2 instruction lengths), cache tag is 256 entries, direct map method, built-in RO / RA, The built-in I / I area is not subject to caching and is also used as built-in RAM.
  • various functions are provided, such as using 2 KB of the built-in RAM as an address array and data array.
  • the data transfer controller DTC is a circuit that can be activated by an interrupt or software to perform data transfer.
  • the features of this DTC are that data can be transferred independently of the CPU by a peripheral I / O interrupt request, a transfer mode can be set for each interrupt source (transfer mode is set in memory), and one activation Depending on the cause, multiple data transfers are possible, a variety of transfer modes (normal mode, solid beat mode, block transfer mode) can be selected, the transfer unit can be set to byte Z-word / launder-word, DTC started Requests an interrupt to the CPU (can generate an interrupt to the CPU after one data transfer is completed, can generate an interrupt to the CPU after all specified data transfers have been completed)
  • the address space can be specified by 32 bits for both the source address and the destination address
  • the device to be transferred is internal memory Flash memory F l a s h, and RAM / C a c h e, external memory
  • the data transfer is performed on-chip peripheral circuits.
  • the direct memory access controller DMAC is composed of, for example, four channels and has an external device with DACK (transfer request acceptance signal), external memory, and memory pin.
  • DACK transfer request acceptance signal
  • This is a circuit that can perform high-speed data transfer between CPU external devices and storage peripheral circuits (excluding DMAC, BSC, and UBC) instead of the CPU.
  • Using this DMAC can reduce the load on the CPU and increase the operating efficiency of the chip MF.
  • the features of this DMAC are: cycle stealing transfer, support for dual address mode transfer, direct transfer mode Z indirect
  • the transfer mode can be switched (only channel 3). In this direct transfer mode, the data at the transfer source address is transferred to the transfer destination address. In the indirect transfer mode, the data at the transfer source address is used as the address. This function transfers the data in that address to the destination address.
  • transfer request function by reload function, external request, internal circuit, and auto request.
  • bus mode selection priority fixed mode, priority setting by round mouth bin mode, and CP It has various functions such as an interrupt request to the server.
  • the bus state controller BSC is a circuit that separates an address space, outputs control signals corresponding to various memories, and the like. This makes it possible to directly connect DRAM, SRAM, ROM, etc. to the chip MF without external circuits.
  • This BSC include memory access during external expansion (external data bus is 32 bits), address space divided into 5 areas (SRAM space x 4 areas, space x 1 area), each area The bus size (8Z16 / 32 bits), the number of wait cycles, the output of the chip select signal corresponding to each area, the output of the DRAM bar RAS and the bar CAS signal when accessing the DRAM space, and the RAS precharge time securing T Any characteristics that can generate p cycles can be set, DRAM burst access function (supports high-speed access mode of DRAM), DRAM refresh function (programmable refresh interval, bar CAS befor RAS refresh / senoref refresh supported ), Wait cycles can be inserted by an external wait signal, address data multiplexed I / O data
  • the user break controller UBC is a circuit that provides a function that facilitates user program debugging.
  • a break condition is set in this UBC, user breaks occur according to the contents of the bus cycle by the CPU or DMAC and DTC. A work interrupt is generated.
  • a high-performance self-monitoring debugger can be easily created, and programs can be easily debugged with the chip MF alone without using a large-scale in-circuit emulator. .
  • the features of this UBC are that an interrupt is generated when the CPU or DMAC generates a bus cycle under a certain set condition, it is easy to build an on-chip debugger, and the break condition is an address, CPU cycle or D MAZ DTC cycle, instruction fetch or data access, read or write, operand size (longword, word, byte) can be set.
  • the break condition is an address, CPU cycle or D MAZ DTC cycle, instruction fetch or data access, read or write, operand size (longword, word, byte) can be set.
  • the interrupt controller INTC is a circuit that determines the priority of an interrupt factor and controls an interrupt request to the processor CPU.
  • This INTC has a register for setting the priority of each interrupt, so that interrupt requests can be processed according to the priority set by the user.
  • the INTC features nine external interrupt pins, 43 internal interrupt sources, 16 levels of priority, a noise canceller function that indicates the status of the NMI pin, and an interrupt function. Can be output to the outside to notify the external bus master that an internal peripheral circuit interrupt has occurred while the chip MF has released the bus right, so that the bus right can be requested. .
  • the serial communication interface SCI comprises, for example, two independent channels, and these two channels have the same function.
  • This SCI is a circuit that can perform serial communication in two systems: start-stop synchronous communication and clock synchronous communication.
  • a serial communication function between multiple processors is provided.
  • the features of this SCI are: start-stop synchronous Z-clock synchronous mode can be selected per channel; transmission and reception can be performed simultaneously (full-duplex); a dedicated baud rate generator is built-in; communication functions between multiprocessors And various other functions.
  • Multi-function timer pulse unit MTU is, for example, 1 of 6 channels. This is a circuit composed of a 6-bit timer. The features of this MTU are that it can output up to 16 types of waveforms or input / output up to 16 types of pulses based on 5 channels of 16-bit timers, and 16 input / output compare registers and inputs.
  • Input capture register total number of 16 independent comparators, selectable from 8 types of counter input clocks, input capture function, pulse output mode Synchronization function of multiple power counters, complementary PWM output mode (outputs non-overlap waveform for 6-phase inverter control, dead time automatic setting, PWM duty can be set to any value from 0 to 100%, output OFF function), reset synchronous PWM mode (positive phase 'negative phase PWM waveform of arbitrary duty, 3 phase output), phase counting mode (2 phase encoder counting process is possible) Seed function is provided.
  • the compare match timer CMT is composed of, for example, two channels, a 16-bit free running counter, one compare register, and the like, and has a function of generating an interrupt request at the compare match.
  • the A / D converter AZD is a 10-bit x 8 channel, which enables conversion by an external trigger and has two built-in sample & hold functions, so that two channels can be sampled simultaneously. .
  • the watchdog timer WDT is a single-channel timer that can monitor the system. This WDT outputs an overflow signal to the outside if the CPU overflows without correctly rewriting the counter value due to system runaway or the like. At the same time, an internal reset signal of the chip MF can be generated. When not used as a WDT, it can be used as an interval timer. When used as an interval timer, an interval timer interrupt is generated each time the counter overflows. WDT is also used when exiting standby mode.
  • the internal reset signal can be generated by setting a register, and the type of reset can be selected from power-on reset and manual reset. The features of this WDT include switching of the watchdog timer Z interval timer, temporary counting overflow, internal reset, and the ability to generate an external signal or interrupt. ing.
  • the phase-look loop circuit PLL is a circuit that incorporates, for example, a clock oscillator and operates as a PLL circuit for clock doubling.
  • these internal circuits are connected to each other by an internal address bus BUSAI and upper and lower internal data buses BUS DI, as shown in FIG.
  • the peripheral address bus BUS AO, the peripheral data bus BUS DO, and the control signal line SL are connected between the I / O and the external connection terminal I / O.
  • the internal address bus BU SAI has a bus width of 24 bits, and includes a processor CPU, flash memory F1ash, random access memory / cache memory RAM / Cache, data transfer controller DTC, and direct memory access controller. Connected between DMA C and bus state controller BSC.
  • the internal data bus BUSDI consists of a high-order 16-bit bus and a low-order 16-bit bus, each of which includes a processor CP, flash memory F1ash, random access memory, and cache memory RAM / Cache,
  • the data transfer controller DTC, the direct memory access controller DMAC, and the state controller BSC are connected between each other, and the 32-bit bus is connected to the upper 16-bit bus and the lower 16-bit bus. It can handle the data width.
  • the peripheral address bus BUS AO has a bus width of 24 bits, a bus state controller BSC, an interrupt controller I NTC, a serial communication interface SCI, a multifunction timer panelless MTi; and a compare match timer. It is connected between the internal circuit of each of CMT and watchdog timer WDT and the external connection terminal I / O.
  • the peripheral data bus BU SDO has a bus width of 16 bits.
  • the control signal line SL consists of a data transfer controller DTC, a direct memory access controller DMAC, a bus state controller BSC, a user break controller UBC, an interrupt controller I NTC, a serial communication interface SCI, and a multifunction timer panorama. It is connected between the internal circuits of the unit MTU, compare match timer CMT, and AZD converter AZD, and between these internal circuits and the external connection terminal IZ ⁇ .
  • the functions are assigned as shown in Fig. 8 as the external connection terminal I ZO, with 98 input / output terminals and 8 input terminals:
  • Each external connection terminal The functions of IZO are as shown in the list of examples of terminal functions corresponding to the classifications, symbols, input / output, and names, as shown in Fig. 15 to Fig. 18.
  • the MF is assigned functions as shown in Fig. 10, and has 74 input / output terminals and 8 input terminals.
  • FIG. 11 is a functional block diagram showing an example of the internal configuration of the chip AD
  • FIG. 12 is an explanatory diagram showing an example of the terminal functions.
  • the chip AD shows an example of 144 pins.
  • the chip AD has a circuit configuration having a DRAM and an AS IC, a memory function capable of writing and reading data at any time, and a processing function using a logic circuit.
  • FIG. It consists of a circuit VS, a plurality of DRAM banks Bank, a main amplifier MA, a data transfer circuit DT, a digital signal processing circuit DSP, a row address buffer RAB, a column address buffer CAB, and a control logic Z timing generation circuit CRZTG.
  • This DRAM is a simple dynamic random access memory DRAM that can be written and read at any time that requires a memory retention operation, a synchronous sink-gate DRAM (S DRAM) that uses a clock, and a long data output time.
  • S DRAM synchronous sink-gate DRAM
  • EEO-DRAM Possible extended data out DRAM
  • Power supply circuit VS is the power supply V cc from the outside, as the input voltage of the ground V ss, a plurality of D RAM bank B ank, c plurality of DRAM banks B ank is a circuit for supplying necessary power to the main amplifier MA, Each bank can operate independently, and each bank
  • the memory includes, for example, a memory cell, a word decoder, a column decoder, a sense amplifier, and a timing generator.
  • the capacity of these DRAM banks Bank is 256 kbits per bank.
  • the main amplifier MA is a circuit that performs data input / output between the plurality of DRAM banks B ank and the external connection terminals D 0 to D 31. For example, between each DRAM bank B ank, there are 128 and many global data lines through which data is exchanged.
  • the data transfer circuit DT switches a data transfer pattern between a DRAM consisting of a DRAM bank B ank and a main amplifier MA and a digital signal processing circuit DSP in real time. For example, it is possible to select one of the adjacent data or clear the data.
  • Digital signal processing circuit DSP is a circuit that executes processing of digital signals such as images and sound.For example, in the case of image processing, processing to remove hidden surfaces by Z comparison, processing to give transparency by ct blending, etc. Execute. Also, data is output from the serial output ports SD0 to SD23 to an output device such as a display.
  • the digital signal processing circuit DSP and the data transfer circuit DT are controlled by control signals C0 to C27.
  • Waxes ⁇ address buffer RAB and the column ⁇ address buffer CAB is a circuit for supplying an external ⁇ address signal input terminal AO ⁇ A 1 0 captures Adoresu signal, and generates an internal Adoresu No. signals to each DRAM bank B ank c. Bar The column address is captured at the timing of bar CAS L, bar CASH, bar CASHL, and bar CASHH at the timing of the RAS.
  • Control logic / timing generation circuit CR / TG is a circuit that generates various timing signals required for the operation of the DRAM.
  • CS is a chip select signal
  • RAS is a row address strobe signal
  • CAS L, CASH, CASHL, and bar CASHH are column address strobe signals
  • RD / bar WR is a read / write signal.
  • the four column address strobe signals are used to enable byte control (read Z write control for each byte) and the CASL signal is Lowest byte D0 to D7
  • bar CASH is the second lowest byte D8 to D15
  • bar CAS HL is third lowest byte D16 to D23
  • bar CAS HH is for the highest byte D24-D31.
  • the plurality of DRAM banks Bank, the row address buffer RAB, and the column address buffer CAB are connected to each other by the internal address bus BU SAI, and further, the row address buffer RAB
  • the peripheral address bus BUSAO is connected between the column address buffer CAB and the external connection terminal I / ⁇
  • the peripheral data bus BUS DO is connected between the main amplifier MA and the external connection terminal IZO.
  • the data transfer circuit DT and the digital signal processing circuit DSP are connected to each other by an address bus and an internal data bus BUS I.
  • the data transfer circuit DT, the digital signal processing circuit DSP and the external connection terminal I / O Are connected by a peripheral bus BUSO for data and control signals.
  • power supply Vcc ground Vss voltage terminals Vcc, Vss, address terminals AO to A10, data input / output terminals D0 to D 31 1, Chip select pin bar CS, Row address strobe pin bar RAS, Column address strobe pin bar CAS L, Bar CASH, Bar CASHL, Bar CASHH, Read / write pin R DZ Bar WR, Clock pin CK, serial data output terminals SD0 to SD23, and ASIC control signal terminals C0 to C27 are provided.
  • FIG. 13 is a functional block diagram showing an example of the internal configuration of the chip D
  • FIG. 14 is an explanatory diagram showing an example of the terminal functions. Note that chip D shows an example of 50 pins.
  • This chip D has only a DRAM formed therein and has a circuit configuration having a memory function capable of writing and reading at any time.
  • a power supply circuit VS a plurality of DRAM banks Bank, a main Consists of amplifier MA, row address buffer RAB, column address buffer CAB, control logic / timing generator CR / TG c.
  • This chip D has a circuit configuration of only the DRAM in which the logic circuit of the data transfer circuit DT and the digital signal processing circuit DSP of the chip AD shown in FIG. Therefore, the internal circuit constituting the chip D is the same as the internal circuit of the chip AD, and the functional description is omitted here.
  • power supply Vcc as external connection terminals, as shown in FIG. 14, power supply Vcc, ground Vss voltage terminals Vcc, Vss, address terminals A0 to A11, data input / output terminals 0 ⁇ 20 ⁇ 0 (331, row address strobe pin bar RAS, column address strobe pin bar LCAS, bar UCAS, write enable pin bar WE, output enable pin bar OE.
  • the semiconductor integrated circuit device configured by combining the chip MF and the chip MFA with one or more chips AD and the chip D has one feature of the present invention.
  • Signal terminals common to the connection terminal of the chip MF or the chip MFA and the connection terminal of the chip AD or the chip D are commonly assigned to the same external connection terminal.
  • the connection terminals commonly assigned to the same external connection terminal will be described in detail.
  • FIG. 19 is a connection diagram showing a connection example between the 144-pin chip MF shown in FIGS. 1 and 8 and the two 50-pin chips D shown in FIGS. Note that FIG. 19 shows only the connection between the signal terminal common to the connection terminals of the chip MF and the connection terminal of the chip D and the external connection terminal.
  • the connection terminal which is a terminal, is also connected to the external connection terminal.
  • the address terminals A0 to A11 of the chip MF are connected to the address terminals AO to A11 of the two chips D and The same external connection terminals A 0 to A 11 are connected, and the data input / output terminals D 0 to D 31 of the chip MF are divided and connected to the data input / output terminals D Q 0 to DQ 15 of each chip D. Connected to the same external connection terminals DO to D31.
  • the power supply terminal V cc and the ground terminal V ss of the chip MF are connected to the power terminal V cc and the ground terminal V ss of the respective chip D, and also connected to the same external connection terminal V cc and V ss, respectively. I have. Since these voltage terminals are actually assigned to a plurality of terminals such as a chip MF, a chip D, and an external connection terminal, each is connected by the same terminal. Further, as for the control signal, the row address stove terminal bar RAS of the chip MF is connected to the two chips D and connected to the external connection terminal bar RAS, and the column address strobe terminal bar of the chip MF is connected.
  • CAS L and bar CAS H are connected to the column address strobe terminal bar LCAS and bar UCAS of one chip D and connected to the external connection terminal bar CAS L and bar CASH, and the column address strobe terminal of chip MF is connected.
  • One terminal CASH L and CAS HH are connected to the column address strobe terminals LCAS and UCAS of the other chip D, and to the external connection terminals CASHL and CASHH.
  • the read Z write terminal RDZ bar WR of the chip MF is commonly connected to the write enable terminal bars WE of the two chips D and is also connected to the external connection terminal RD / bar WR, and the chip select terminal bar of the chip MF is connected.
  • CS 3 is commonly connected to the output enable terminal bar OE of the two chips D and is also connected to the external connection terminal bar CS 3.
  • connection terminals of the chip D are common to the connection terminals of the chip MF, and are connected to the same external connection terminals. Connected. Note that, in the semiconductor integrated circuit device including the chip MF and the chip D, there is actually a connection terminal which is an independent signal terminal only in the chip MF. Therefore, an external connection terminal connected to the independent connection terminal is also provided. Provided so that it can be connected to the outside.
  • FIG. 20 is a connection diagram showing a connection example between the 144-pin chip MF shown in FIGS. 7 and 8 and the 144-pin chip AD shown in FIGS. 11 and 12.
  • FIG. 20 as in FIG. 19, only the connection between the signal terminal common to the connection terminal of the chip MF and the connection terminal of the chip AD and the external connection terminal are shown.
  • the connection terminal which is an independent signal terminal only for chip MF and chip AD, is also connected to the external connection terminal.
  • the address terminals AO to A10 of the chip MF are connected to the address terminals AO to A10 of the chip AD and have the same external connection.
  • data input / output terminals D0 to D31 of chip MF are connected to data input / output terminals D0 to D31 of chip AD. And are connected to the same external connection terminals D0 to D31.
  • the power supply terminal Vcc and the ground terminal Vss of the chip MF are connected to the power supply terminal Vcc and the ground terminal Vss of the chip AD, respectively, and are also connected to the same external connection terminals Vcc and Vss, respectively. Note that these voltage terminals are actually assigned to multiple terminals of the chip MF, chip AD, and external connection terminal, so each is connected by the same terminal.
  • the row address strobe pin bar RAS of the chip MF, the column address strobe pin bar CAS L, the bar CASH, the bar CA SHL, the bar CASHH, the read Z write pin RD / bar WR, and the chip selector pin bar CS3, clock pin CK is row address strobe pin of chip AD RAS, column address strobe pin CAS L, bar CASH, bar CASH L, bar CASHH, read Z write pin RDZ bar WR, chip select Connected to the CS terminal 3 and the clock terminal CK, respectively, and the same external connection terminal, the row address strobe terminal bar RAS, the column address strobe terminal bar CASL, bar CASH, bar CASHL, bar CA SHH, read / Write terminal RD / bar WR, chip select terminal CS3, clock terminal CK It has been.
  • the serial data outputs SD0 to SD23 which are signals specific to only the chip AD, and the AS IC control signal terminal
  • connection terminals that are independent signal terminals only on the chip MF, so external connection terminals connected to these independent connection terminals are also provided so that they can be connected to the outside. ing.
  • the DRAM of the chip AD and the chip D is a synchronous DRAM, it is necessary to further synchronize within the semiconductor integrated circuit device.
  • the clock terminal to which the given clock signal is assigned is also connected to the same external connection terminal as a common connection terminal.
  • a semiconductor integrated circuit composed of a combination of a chip MF, a chip MFA, and one or more chips AD, a chip D
  • the outline of the read operation, write operation, and refresh operation from the processor CPU of the chip MF (chip MFA) to the DRAM of the chip AD (chip D) will be described.
  • the RAS circuitry When RAS goes low (L), the RAS circuitry is activated and memory operations begin. Subsequently, when the bar CAS becomes L, a read operation or a write operation starts, and data is exchanged with the chip MF outside the chip AD. As described above, in the DRAM of the chip AD, the precharge period and the active period are alternately repeated. Normally, the cycle time of the bus RAS is the cycle time of the chip AD.
  • the read operation is specified by setting the write enable signal WE to H before the falling point of CAS, and until the CAS rises. Do it by holding it. Once the data is output, the data is held until the CAS rises.
  • RAS access time the time from the fall of RAS and CAS to the output of data to the data output terminal
  • CAS access time the time from when the column address is determined to when the data is output.
  • a refresh operation is performed by interrupting during random access operations such as reading and writing, and a refresh operation is performed only to retain information stored inside the chip AD, such as during a battery backup period.
  • the former is standard for bar RAS online refresh and CBR (bar CAS efor bar RAS) refresh, and the latter is standard for self refresh.
  • RAS only refresh
  • all memory cells in one row are refreshed simultaneously during one cycle of basic RAS with the same timing standard as read operation and write operation.
  • the refresh address must be given from the chip MF outside the chip AD by setting the bar CAS to H. 3
  • Intensive refresh is a method in which refresh is repeated in the minimum cycle, and during this period, no memory access can be made from the chip MF outside the chip AD, but during the remaining period, the refresh is not interrupted and external memory access is accepted.
  • Distributed refresh is one in which one refresh operation is evenly distributed over the maximum refresh period. Actually, since distributed refresh is frequently used, one cycle of the refresh operation is the timing that interrupts the normal read / write operation cycle.
  • CBR refresh internally determines that it is a refresh operation by setting L to CAS before RAS. An address is generated from an internal refresh address counter by this determination pulse, and a lead line is selected and refreshed. Therefore, it is not necessary to give an address from outside the chip AD.
  • self-refresh is performed after the end of a normal memory cycle.
  • the pulse width of the bar RAS for example, more than 1 00 mu s.
  • the refresh operation using the refresh address counter and refresh timer starts, and self-refresh continues as long as both RAS and CAS are low.
  • a RAS bar precharge period is required.
  • the read operation, the write operation, and the refresh operation are performed from the processor CPU of the chip MF to the DRAM of the chip AD.
  • the chip AD It has a circuit configuration capable of executing a refresh operation / access operation by an internal mouthpiece circuit.
  • the refresh operation and the Z access operation can be performed during the self-refresh operation.
  • FIG. 21 is a schematic configuration diagram schematically showing an example of internal functions of the chip AD shown in FIG.
  • This chip AD is composed of a dynamic random access memory DRAM, a memory built-in logic Logic, and a DRAM access control circuit DAC.
  • the DRAM, logic with built-in memory, and DRAM access control circuit DAC shown in FIG. 21 correspond to the DRAM part by the plurality of DRAM banks Bank and main amplifier MA shown in FIG. It supports the AS IC part by the circuit DT and the digital signal processing circuit DSP, and the access control part by the row address buffer RAB and column address buffer CAB.
  • the input buffer IB and the output buffer OB are connected to the circuit IZO and the digital signal processing circuit DSP for inputting and outputting data between the main amplifier IA and the external connection terminals D0 to D32 shown in FIG. Compatible with circuit I / O.
  • a chip select signal bar CS, a row address strobe signal bar RAS, and a column address strobe signal CAS are connected to a control signal terminal, and an end address signal is connected to a DRAM access control circuit DAC through a pad address terminal. Input and data signals can be input / output via the data input / output terminal.
  • the DRAM and the DRAM access control circuit DAC are connected by an address bus BUS A, and the DRAM is connected to a memory logic Logic and a data input / output terminal by a data bus BUS D.
  • the internal data bus BUS D has a bus width of 64 bits, which is wider than that of an 8-bit data input / output terminal, for example.
  • the logic with built-in memory and the DRAM access control circuit DAC are connected by an address bus and a control signal line, and the DRAM access control circuit DAC has a self-connection to the logic with built-in memory.
  • the refresh operation permission signal is output, and the logic built in the memory outputs the read Z write signal R / W and the address signal to the DRAM access control circuit DAC.
  • the read / write signal R / W can be separately output as the read signal R and the write signal W.
  • a data input / output inhibit signal DIS is output from the DRAM access control circuit DAC to the input buffer IB and the output buffer OB.
  • FIG. 22 is a configuration diagram showing a detailed example of the DRAM access control circuit DAC.
  • the DRAM access control circuit DAC includes an internal control signal generation circuit CSG, a plurality of selector circuits SC, and the like.
  • the chip select signal bar CS and the row address strobe signal input to the internal control signal generation circuit CSG are provided. Based on bar RAS and column address strobe signal CAS, it generates a control signal for selecting an address, etc., and also generates a self-refresh operation enable signal and outputs it to logic L 0 gic with built-in memory.
  • the logic inside the memory that has received the permission signal can access the DRAM, and outputs a read / write signal R / W to the DRAM access control circuit DAC to issue a read Z write request. And outputs an address signal to the DRAM access control circuit DAC to select an arbitrary memory cell. Data can be read / written between the memory cell and the logic with built-in memory. Note that this read / write request can be made by outputting a read signal R when making a read request and outputting a write signal W when making a write request.
  • the address control signal generated by the internal control code generation circuit CSG is used for access operations from the processor CPU of the chip MF outside the chip AD and access from the logic Logic inside the chip AD memory. For operation, one is selected via a selector circuit SC and used as an address control signal for selecting an arbitrary memory cell of the DRAM.
  • FIG. 23 is an explanatory diagram showing an example of a transition state of the operation mode by the internal control signal generation circuit CSG.
  • This operation mode can be divided into a normal DRAM access operation mode, a DRAM senoref refresh operation mode, and an access operation mode using the internal logic logic of the internal memory.
  • a transition is made to the operation mode without a read / write request from the read / write signal RZW from the logic inside the memory Logic, and the normal DRAM access operation mode is returned by releasing the refresh.
  • a transition is made from the self-refresh operation mode to the internal access operation mode when there is a read / write request from the logic Logic in the memory, and the return to the self-refresh operation mode is performed by the completion of the read / write.
  • transition from the normal DRAM access operation mode to the internal access operation mode is made when there is a read / write request from the logic inside the memory, and return to the normal DRAM access operation mode is performed by releasing the refresh.
  • FIG. 24 is an operation timing chart showing a control example of the DRAM access control circuit DAC including the internal control signal generation circuit CSG for the DRAM.
  • a normal DRAM access period in which a normal DRAM access can be executed and a normal DRAM access period between the normal DRAM access period and the normal DRAM access period are performed.
  • Executable DRAM self refresh There is a DRAM self-refresh period.
  • the DRAM senoref refresh period is a period during which normal access operation from the chip MF to the DRAM is not performed.
  • the self-refresh operation enable signal is supplied to the logic logic in the memory based on the input address strobe signal RAS and the column address strobe signal CAS in synchronization with the clock signal CK.
  • the refresh operation is released only when there is a request for access operation for reading and writing from the logic Logic of the memory by the control signal RZW to the DRAM. Access operation from the signal processing circuit DSP) is enabled.
  • the execution of the refresh operation Z access operation during the self-refresh period can be repeated in accordance with a read request by the control signal R, for example, as shown in FIG.
  • the refresh operation can be performed during the period between the operations, and the read operation can be repeated in response to the write request by the control signal W.
  • the refresh operation can be performed during the period between the write operations and the read operation by the control signal R.
  • the read and write access operations can be repeated, and the refresh operation can be executed during the access operation.
  • the logic AD of the memory of the chip AD can access the DRAM
  • the logic LSI of the memory of the chip AD can access the DRAM.
  • a write request can write data to the DRAM
  • a read request can read data from the DRAM.
  • the access operation to the DRAM by the logic built into the memory of the chip AD during the self-refresh operation is the same when the other chip is connected to the chip AD.
  • the chip MFA or the CPU Similar effects can be expected for other semiconductor chips including.
  • the present invention can be applied to a semiconductor integrated circuit device having a package structure capable of performing an access operation to a DRAM of a portable AD and a self-refresh operation of the DRAM.
  • FIG. 25 is an overall perspective view of the package of the present embodiment
  • FIG. 26 is a sectional view of the package.
  • the package of the present embodiment seals the first chip MF (microcomputer equipped with flash memory) on which a microcomputer and a flash memory are formed in a first TCP (Tape Carrier Package) 1A and
  • the second chip AD (DRAM on-chip logic) on which DRAM and ASIC are formed is sealed in a second TCP 1B, and these two TCP 1A and IB are vertically arranged. It has a stacked TCP structure that is overlapped and joined together.
  • the first chip MF sealed in the first TCP 1A has its main surface (element forming surface) facing down in a device hole 3a opened in the center of the tape carrier 2a. And one end (inner lead portion) of a lead 5a formed on one surface of the tape carrier 2a via a bump electrode 4 formed on the periphery of the main surface. It is connected to the.
  • the main surface of the chip MF is covered with a botting resin 6 for protecting the LSI (microcomputer with flash memory) formed on the main surface from the external environment.
  • the lead 5a formed on one surface of the tape carrier 2a has a pattern as shown in FIG.
  • the surfaces of these leads 5a are covered with the solder resist 7 except for one end (inner lead portion) protruding into the device hole 3a.
  • the other end of each lead 5a is electrically connected to a through hole 8a penetrating from one surface of the tape carrier 2a to the other surface.
  • These through holes 8a are arranged in two rows along four sides of the tape carrier 2a, and the surface of each through hole 8a is provided with this laminated TCP as shown in FIG.
  • Solder bumps 9 serving as external connection terminals when mounted on a printed wiring board are joined.
  • the second TCP 1 B is stacked on the first TCP 1 A. TCP 1 A and TCP 1 B are tightly joined by adhesive 10 applied to the mating surface of both Have been.
  • the second chip AD sealed in the TCP 1B is disposed with its main surface facing downward in a device hole 3b opened in the center of the tape carrier 2b. It is electrically connected to one end (inner lead portion) of a lead 5b formed on one surface of the tape carrier 2b via a bump electrode 4 formed on the periphery of the main surface.
  • the main surface of the chip AD is covered with a potting resin 6 for protecting the LSI (DRAM on-chip logic) formed on the main surface from the external environment.
  • the outer diameter of the tape carrier 2b of the TCP 1B is the same as the tape carrier 2a of the TCP 1A.
  • the dimensions of the device hole 3b of the tape carrier 2b are smaller than the device holes 3a of the tape carrier 2a, since the outer diameter of the chip AD is smaller than that of the chip MF.
  • the lead 4b formed on one surface of the tape carrier 2b has a pattern as shown in FIG.
  • the other end of each lead 5b is electrically connected to a through hole 8b penetrating from one surface of the tape carrier 2b to the other surface.
  • These through holes 8b are arranged in two rows along the four sides of the tape carrier 2b, like the through holes 8a of the tape carrier 2a.
  • the through holes 8a of the tape carrier 2a and the through holes 8b of the tape carrier 2b are formed with the same number and the same pitch, and they face each other when the tape carriers 2a and 2b are overlapped.
  • connection terminals (pins) common to the two chips MF and AD that is, having the same function
  • pins are arranged at the same position on the tape carriers 2a and 2b. It is electrically connected through the through holes 8a and 8b, and is commonly drawn to the outside (printed circuit board) via the solder bumps 9 joined to one end of the through hole 8a.
  • FIG. 27 the numbers (1 to 144) of the connection terminals formed on the chip MF and the numbers (1 to 200) of the through holes 8a formed on the tape carrier 2a are given.
  • FIG. 28 shows the connection terminal numbers (1 to 144) formed on the chip AD. And the number (1 to 200) of the through hole 8b formed in the tape carrier 2b. The same numbers are given to the through holes 8a and 8b arranged at the same position on the tape carriers 2a and 2b.
  • Table 1 shows an example of the assignment of the connection terminals for the chips MF and AD and the through holes 8a and 8b.
  • MF pin # column number (1: 144) corresponds to the switch-up MF connection terminal number (1 to 1 44) shown in FIG. 27
  • ADp i n # column number ( 1 to 144) correspond to the connection terminal numbers (1 to 144) of the chip AD shown in FIG.
  • the numbers in the Via # column are the numbers (1 to 200) of through holes 8a and 8b shown in FIGS. This is the number assigned to the terminal. ⁇
  • connection terminal common to the chips MF and AD is arranged at substantially the same position as the chips MF and AD.
  • the leads 5a and 5b of the tape carriers 2a and 2b can be easily routed and the lead length can be reduced, so that the data transfer of the chips MF and AD can be speeded up.
  • the tape carrier 2a since the number of required through holes 8a and 8b can be minimized, the tape carrier 2a,
  • the package size can be reduced by reducing the outer diameter of 2b.
  • each member constituting the laminated TCP of the present embodiment is made of the following materials and dimensions.
  • the tape carriers 2a and 2b are made of a 75 yum thick polyimide resin film.
  • Leads 5a and 5b are made of 18 (m) thick Cu (copper) foil, and the surface of one end (inner lead) is Au (gold) or Sn (tin). It has the following plating.
  • the adhesive 10 is made of polyimide resin, and its film thickness is 12 im.
  • the solder resist 7 is made of an epoxy resin and has a thickness of 20 ⁇ m.
  • the solder bumps 9 serving as external connection terminals and the solders 11 in the through holes 8a and 8b are made of a lead (Pb) -tin (Sn) alloy.
  • the chip MF and the chip AD are composed of 50-thick single-crystal silicon, and the potting resin 6 for protecting their main surfaces is composed of epoxy resin.
  • the bump electrodes 4 formed on the main surfaces of the chip MF and the chip AD are made of Au, and their height is 20 ⁇ . That is, in this laminated TCP, the total thickness of the chip MF and the bump electrode 4 is smaller than the thickness of the tape carrier 2a, and the total thickness of the chip AD and the bump electrode 4 is smaller than the thickness of the tape carrier 2b. Because it is made thin, the thickness of the part excluding the solder bumps 9 in the stacking direction is 218 ⁇ , making it an ultra-thin package.
  • FIGS. 29A to 33 are (a) a cross-sectional view of TCP1B, and (b) are cross-sectional views of TCP1A.
  • tape carriers 2a and 2b made of polyimide resin film are prepared, and they are punched out to make device holes in the tape carrier 2a.
  • tape carrier 2b is connected to device hole 3b. And a through hole 8b.
  • these tape carriers 2a and 2b are long films wound on reels, and only a part (one for TCP 1A and one for TCP 113) is shown in the figure.
  • a Cu foil is laminated on one surface of each of the tape carriers 2a and 2b, and the Cu foil is wet-etched to form leads 5a on the tape carrier 2a. Then, a lead 5b is formed on the tape carrier 2b. At the same time, a Cu foil hole 12a is formed at one end of the through hole 8a, and a Cu foil hole 12b is formed at one end of the through hole 8b.
  • a Cu foil hole 1 2 The diameter of a is smaller than the through hole 8a, and the diameter of the Cu foil hole 12b is smaller than the through hole 8b. Also, Cu foil has a smaller thermal expansion coefficient and higher dimensional stability than polyimide resin tape carriers 2a and 2b, so it passes through the diameter of 1! Foil holes 1 2 & and 1 2b. If the holes are smaller than the holes 8a and 8b, the positioning of the tape carrier 2a and the tape carrier 2b when using the through holes 8a and 8b in the subsequent process will be highly accurate. Can be done.
  • a solder resist 7 is applied to the lower surface of the tape carrier 2a.
  • the adhesive 10 is applied to the lower surface of the tape carrier 2b.
  • the bump electrodes 4 formed on the connection terminals of the chip MF and the leads 5a of the tape carrier 2a are collectively connected by a gang bonding method.
  • the bump electrodes 4 formed on the connection terminals of the chip AD and the leads 5b of the tape carrier 2b are collectively connected by a gang bonding method.
  • the chip MF and the chip AD are polished in advance in a wafer state, and then thinned to 50 ⁇ by spin etching.
  • the bump electrode 4 is formed in the final step of the wafer process using a stud bump bonding method.
  • Lead 5 Since the inner leads of a and 5b are plated with Au or Sn, the lead 5a and the bump electrode 4 and the lead 5b and the bump electrode 4 are connected by Au—Au bonding or Au—S Bonded by n-eutectic bonding.
  • the bonding between the leads 5a and 5b and the bump electrode 4 may be performed by a single point bonding method instead of the gearing bonding method.
  • potting resin 6 is applied to the main surface of chip MF and the gap between tape carrier 2a and device hole 3a. I do. Similarly, potting resin 6 is applied to the main surface of chip AD and the gap between tape carrier 2b and device hole 3b.
  • the long tape carriers 2a and 2b are separated into individual pieces using a cutting die, and each of the tape carriers 2a and 2b is mounted on a socket and subjected to an aging inspection. Sort out. Aging of the tape carriers 2a and 2b is performed by applying socket pins to test pads formed on each part of the tape carriers 2a and 2b.
  • the tape carriers 2a and 2b are overlapped so that the positions of the through holes 8a and 8b facing each other exactly match, and then heat-pressed.
  • TCP 1A and TCP 1B can be tightly joined.
  • the above-described Cu foil holes 12a and 12b are used.
  • a test pad formed on each part of the tape carriers 2a and 2b may be used.
  • solder paste made of a lead (Pb) -tin (Sn) alloy is embedded in the through holes 8a and 8b by screen printing, and this solder base is removed. Reflow to form solder 11 1.
  • solder bump 9 is formed at one end of the through hole 8a of the tape carrier 2a, whereby the stacked TCP shown in FIGS. 1 and 2 is completed.
  • Solder bumps 9 are placed beforehand with the solder bump forming surface of tape carrier 2a facing up.
  • the solder ball formed above is positioned on the through hole 8a, and then the solder ball is formed by reflow.
  • the solder bumps arranged on the surface of the glass substrate may be transferred to the surface of the through hole 8a.
  • the solder bump 9 is made of a lead (Pb) -tin (Sn) alloy having a lower melting point than the solder 11 filled in the through holes 8a and 8b.
  • solder bumps 9 are positioned on the electrodes 15 of the printed wiring board 14, and then the solder bumps 9 are formed. Should be reflowed.
  • the chip MF which forms a computer with a microphone port with flash memory, has a larger number of functional blocks and generates more heat than the chip AD, which forms DRAM on-chip logic.
  • Chip MF is arranged.
  • arranging a chip having a large number of connection terminals on the lower side (substrate side) facilitates routing of wiring connecting the chip connection terminals and external connection terminals.
  • the DRAM memory cell formed in the chip AD adopt a stacked-type capacitor (STC) structure.
  • STC stacked-type capacitor
  • the heat dissipation fins 16 made of a metal with high thermal conductivity such as A1 can be attached to the top of the multilayer TCP. Good.
  • a chip MF that generates a large amount of heat is arranged above the chip AD (on the side close to the radiation fins 16).
  • TCP 1A and 1B may be packaged in the following way.
  • TCP 1A and TCP 1B are separately formed according to the method described above.
  • solder is inserted inside the through hole 8a of TCP 1A.
  • the paste lip is embedded, and the solder paste 11p is embedded inside the through hole 8b of the TCP 1B. Screen printing is used for embedding the solder paste.
  • the tape carriers 2a and 2b are overlapped and heated and pressed, and the two are joined with an adhesive 10 and the solder paste 11p is reflowed to form a through hole 8a. Solder 11 is formed inside a, 8b. Subsequent steps are the same as the above-mentioned manufacturing method.
  • TCP 1A and TCP 1B are temporarily attached with the adhesive force of solder paste 11p, so the superimposed TCP 1A and 1B are transported to a heating furnace or the like, and both are heated and pressed. In the meantime, the displacement of the facing through holes 8a and 8b can be prevented.
  • tape carriers 2a and 2b are overlapped to form TCP 1A and 1B into one package, and holes are drilled into tape carriers 2a and 2b using a drill. Then, a conductive layer may be formed inside the holes by an electroless plating method.
  • the chips MF and AD can be sealed by a trans-famold method instead of the above-mentioned botting method.
  • the bump electrode 4 of the chip MF is electrically connected to the lead 5a of the tape carrier 2a according to the method described above, and the bump electrode 4 of the chip AD and the tape carrier 2b are electrically connected. Connect lead 5b electrically.
  • the chips MF and AD are sealed with a mold resin 17.
  • the tape carriers 2a and 2b are mounted on a mold respectively, and a plurality of chips MF and AD are respectively sealed in a batch.
  • Epoxy resin is used for the mold resin 17.
  • a structure in which the entire surface of the chips MF and AD is covered with the molding resin 17 and the back surface of the chips MF and AD may be exposed from the molding resin 17 may be employed.
  • the resin processed into a sheet is applied to the upper surfaces of the tape carriers 2a and 2b and heated and pressed, so that the resin flows into the main and side surfaces of the chips MF and AD.
  • the thickness of the mold resin 17 for encapsulating the chips MF and AD is extremely small, the case where the back surface of the chips MF and AD is exposed from the mold resin 17 or the entire surface of the chips MF and AD If the thickness of the mold resin 17 is uneven between the main surface and the back surface of the chip MF, AD, the thermal expansion coefficient of the chip MF, AD and the mold resin 17 If there is a difference between them, the TCP 1A and IB will warp, causing chip cracks and poor connection when mounting the board. Therefore, the mold resin 17 has a low coefficient of thermal expansion, and it is necessary to select a material close to the coefficient of thermal expansion of the chips MF and AD.
  • the tape carriers 2a and 2b are separated into individual pieces using a cutting die, and the individual TCPs 1A and 1B are subjected to an aging test to select non-defective products.
  • the tape carriers 2a and 2b are overlapped and heated and pressed together so that the positions of the facing through holes 8a and 8b are exactly matched, and the two are joined with an adhesive 10.
  • the solder 11 is formed inside the through holes 8a and 8b according to the method described above, and the solder bump 9 is formed at one end of the through hole 8a of the tape carrier 2a.
  • TCP is completed.
  • the TCP 1A, 1B May be stacked to make one package
  • the chip MF and the chip AD may be simultaneously and collectively sealed with the mold resin 17.
  • the bump electrode 4 of the chip MF is electrically connected to the lead 5a of the tape carrier 2a according to the method described above, and the bump electrode 4 of the chip AD and the tape carrier 2b.
  • the tape carriers 2a and 2b are overlapped and heated and pressed together, and the two are joined with an adhesive 10.
  • solder 11 is formed inside through holes 8a and 8b according to the method described above, and solder bumps are attached to one end of through hole 8a of tape carrier 2a.
  • the outer diameter dimension accuracy of the sealing portion is improved compared to the method of sealing the chips MF and AD with the botting resin 6. Therefore, it is possible to manufacture a laminated TCP having a high dimensional stability and a uniform shape. Also, by sealing a plurality of chips MF and AD in a batch at a time, the sealing time can be reduced. Furthermore, by making the thickness of the mold resin 17 the same as that of the tape carriers 2a and 2b, there is no gap between TCP 1A and TCP 1B.
  • the reliability of high-les multilayer TCP of the c the present invention capable of producing a multilayer type TCP is a method for the construction of external connection terminals in the solder bumps 9
  • the leads 5a and 5b can form an external connection terminal. A method of manufacturing the stacked TCP will be described with reference to FIGS.
  • a tape carrier 2a, 2b made of polyimide resin film is punched out to form a device hole 3a in the tape carrier 2a, and a device hole 3b in the tape carrier 2b. .
  • These through holes 8a and 8b are not formed in these tape carriers 2a and 2b.
  • a lead 5a is formed on the tape carrier 2a in accordance with the above-described method, and a lead 5b is formed on the tape carrier 2b, and one end (inner lead portion) is formed.
  • solder resist 7 is applied to one surface of tape carrier 2a, and adhesive 10 is applied to one surface of tape carrier 2b.
  • the leads 5a and 5b are formed in such a length that their other ends (outer leads) can be used as external connection terminals.
  • the bump electrode 4 of the chip MF is electrically connected to the lead 5a of the tape carrier 2a according to the method described above, and the bump electrode 4 of the chip AD is connected to the lead 5 of the tape carrier 2b.
  • the chips MF and AD are sealed with botting resin 6, and then the tape carriers 2a and 2b are singulated, and each TCP 1A and 1B is subjected to aging inspection. To select good products.
  • the TCPs 1A and 1B are made into one package by overlapping and joining the tape carriers 2a and 2b according to the method described above, and then, as shown in Fig. 52. Then, the tape carriers 2a and 2b supporting the other ends (outer lead portions) of the leads 5a and 5b are cut and removed.
  • the illustrated stacked TCP may be disposed with the main surface of the chips MF and AD facing upward. Further, force for sealing chips IF and AD with botting resin 6 As shown in FIG. 55, chips MF and AD may be sealed with molding resin 17.
  • the manufacturing process is simplified as compared with the above-mentioned multilayer TCP in which the external connection terminals are composed of the solder bumps 9.
  • the manufacturing cost of the stacked TCP can be reduced ; and the through holes 5a, 5b need not be provided in the tape carriers 2a, 2b, so that the leads 5a, 5b In addition to facilitating the routing, the manufacturing cost of the tape carriers 2a and 2b can be reduced.
  • the time required for forming the external connection terminals can be reduced. Also, connect the other ends (outer leads) of the leads 5a and 5b.
  • the electrodes 15 on the printed wiring board 14 By overlapping and connecting the electrodes 15 on the printed wiring board 14, the area of the electrodes 15 occupying the surface of the printed wiring board 14 can be reduced, and the mounting of the stacked TCP (lead 5 a , 5b and the electrode 15) can be performed once.
  • the leads 5a and 5b constituting the external connection terminal may be individually molded using two dies.
  • chip MF, AD sealed with botting resin 6 chip MF, AD sealed with botting resin 6
  • Figure 57 chip MF, AD sealed with molding resin 17
  • the stacked TCP shown in Fig. 58 has an external connection terminal by forming the other end (outer lead) of the lead 5a formed on the lower TCP 1A into a gull-wing shape. Electrical connection to 1B is made through solder 11 embedded in through holes 8a and 8b formed in tape carriers 2a and 2b.
  • the above structure, in which the external connection terminal is formed by a gull-wing shaped lead, is a flexible lead in which the stress applied to the connection between the stacked TCP and the printed wiring board due to the difference in the coefficient of thermal expansion between them is flexible.
  • the connection reliability with the board is higher than the structure in which the external connection terminals are composed of solder bumps because they are absorbed and mitigated by the deformation.
  • the package of the present invention can be mounted on the printed wiring board 14 individually without forming the TCP 1A and the TCP 1B into one package.
  • the mounting density is lower than that of the stacked TCP in which TCPs 1A and 1B are packaged in one package, the process of stacking TCPs 1A and 1B into one package is unnecessary. The manufacturing cost of the package can be reduced.
  • the stacked TCP of the present invention is used in a PGA (Pin Grid Array) type package, as shown in FIG. 60, instead of a method in which the external connection terminals are constituted by the solder bumps 9 and the leads 5a and 5b.
  • the external connection terminal can also be configured with pin 18.
  • the surface of the pin 18 is plated with Sn (tin) or the like, and is electrically connected to the lead 5a and / or the lead 5b inside the through holes 8a and 8b.
  • the chip MF and the lead 5a and the chip AD and the lead 5b can be connected by using an anisotropic conductive film.
  • an anisotropic conductive film To manufacture a laminated TCP using an anisotropic conductive film, first, as shown in Fig. 61, the device hole 3a, the single hole 8a and the lead After forming device hole 3a, through hole 8a and lead 5b on tape carrier 2b, solder resist 7 is applied to one side of tape carrier 2a, and tape carrier 2b is formed. Adhesive 10 is applied to one side of the substrate.
  • the anisotropic conductive film 19a which has been cut to the same size as the device hole 3a of the tape carrier 2a in advance, is projected into the device hole 3a. Position on one end (inner lead) of lead 5a. Similarly, an anisotropic conductive film 19b, which has been cut to the same size as the device hole 3b of the tape carrier 2b in advance, is provided with one end 19b of the lead 5b protruding into the inside of the device hole 3b. (Inner lead part) Position: Next, as shown in FIG. 63, the chip MF on which the bump electrodes 4 are formed faces down on the anisotropic conductive film 19 a with the main surface facing downward.
  • the anisotropic conductive film 19a is heated and pressurized to electrically connect the bump electrode 4 and the lead 5a via the conductive particles in the anisotropic conductive film 19a.
  • the anisotropic conductive film 19 b is heated and pressed.
  • bump conductive via conductive particles in the anisotropic conductive film 19b. 4 and lead 5 b Following electrically connected SOULTZ, a tape carrier 2 a, 2 b pieces and fragmented, to sort non-defective are denoted by the individual T C P 1 A, 1 B aging test.
  • the tape carriers 2a and 2b are superimposed according to the above-described method to form one package of TCPs 1A and 1B.
  • solder 11 is filled in a and 8b, and solder bump 9 is formed at one end of through hole 8a.
  • the various stacked TCPs of the present invention described above are applied not only to the case where the chip MF and the chip AD are combined, but also to the above-described configuration examples of the chip MFA-chip D, the chip MFA + chip AD, the chip MF + chip D, and the like. Of course you can do two.
  • the stacked TCP of the present invention can also be applied to a case where three or more chips are stacked. it can.
  • Chip MF is a molding resin. Sealed with 17.
  • the lead 5a formed on one surface of the tape carrier 2a has a pattern as shown in FIG.
  • TCP 1 C sealing chip D On top of TCP 1 A, TCP 1 C sealing chip D, is stacked, and further on top, TCP 1 D sealing chip D 2 is stacked.
  • Chip D t sealed in TCP 1 C is arranged toward the main surface on the apertured the Device Isuhoru 3 in c in a central portion of the tape carrier 2 c, the central portion of the main surface It is electrically connected to one end (inner lead portion) of a lead 5c formed on one surface of the tape carrier 2c via the bump electrode 4 formed on the tape carrier 2c.
  • the chip D 2 sealed in the TCP 1 D is arranged with its main surface facing upward in a device hole 3 d opened in the center of the tape carrier 2 d.
  • the lead 5c formed on one surface of the tape carrier 2c has a pattern as shown in FIG. 68, and the lead 5d formed on one surface of the tape carrier 2d is formed as shown in FIG. It has a pattern.
  • the multilayer TCP is the three-chip MF, D "common D 2 to (i.e. having the same function) through a connection terminal (pin) disposed at the same position of the tape carrier 2 a, 2 c, 2 d Electrical connection through holes 8a, 8c, 8d
  • the lead 5a formed on the carrier 2a has a structure in which the lead 5a is commonly drawn to the outside (blind wiring board) through the other end (outer lead). It goes without saying that the external connection terminals can be constituted by the above-mentioned solder bumps and pins in addition to the leads.
  • the external connection terminals can be constituted by the above-mentioned solder bumps and pins in addition to the leads.
  • the numbers (1 to 144) of the connection terminals formed on the chip MF and the numbers (1 to 144) of the through holes 8a formed on the tape carrier 2a are given:
  • the numbers (1 to 46) of the connection terminals formed on the chip D and the numbers (1 to 144) of the through holes 8c formed on the tape carrier 2c are given.
  • the chip D 2 the formed number of the connection terminals (1-46) and a tape carrier 2 d to form through holes 8 d number (1 to 144) are then Togazuke.
  • the same numbers are given to the through holes 8a, 8c, 8d arranged at the same position on the tape carriers 2a, 2c, 2d.
  • the area of the chip DD is less than half of the area of any chip MF, as shown in FIG. 70, are arranged side by side and tip D ,, D 2 next, the common connection terminal of Common chip D 2 It can be connected with lead 5e. In this way, an ultra-thin package can be realized as in the case of the above-described stacked TCP mounting two chips MF and AD.
  • the package of the present invention is not limited to the above-described structure, and various design changes can be made to its details.
  • a structure in which the chip MF sealed in the TCP 1 A and the lead 5 a formed in the tape carrier 2 a are electrically connected with the Au wire 20 can be adopted. .
  • the chip MF and chip AD are not packaged into one package, but are individually sealed in a QFP (Quad Flat package) type package and printed wiring. It can also be mounted on the substrate 14.
  • QFP Quad Flat package
  • the package of the present invention is used for devices and systems such as multimedia devices and information home appliances, for example, a car navigation system as shown in FIG. 73, a D-ROM (Compact Disk ROM) drive device as shown in FIG. It is used for a game device as shown, a PDA (Personal Digital Assistance) as shown in FIG. 76, a mobile communication device as shown in FIG. 77, and the like.
  • Figure 73 is a functional block diagram showing an example of the internal configuration of a car navigation system. is there.
  • This car navigation system includes a control unit, a display unit connected to the control unit, a GPS and a CD-ROM.
  • the control section is for main CP, program EPROM (4M), work RAVI (SRAM: 1M), I / O control circuit, ARTOP, image RAM (DRAM: 4M), CG (Computer Graphics) It consists of a ROM (mask ROM: 4M), gate array, etc., and the display unit consists of a slave microcomputer, TFT, etc.
  • the main CPU of the control unit controls according to a control program stored in a program EPROM.
  • the control unit compares the position information by GPS, which measures the position of the car between the satellite and the ground station, and the map information stored on the CD via the I / O control circuit and the gate array. Enter and store this information in the work RAM.
  • ART ⁇ P performs processing such as arranging the position of the car on a map based on the position information and the map information stored in the work RAM.
  • the image information stored in the image RAM is passed to the display unit, and the display unit displays the image information on a TFT screen based on the control of the computer with the slave microphone, so that the vehicle information is displayed.
  • An image whose position is arranged on a map can be displayed.
  • the main CPU is constituted by a processor
  • the program EP ROM is constituted by a flash memory
  • the ARTOP is constituted by a logic circuit by an ASIC.
  • the image RAM is composed of DRAM and the gate array is composed of a logic circuit composed of ASIC, the chip AD of this embodiment can be used for this block. It is also possible to simply use a chip MF for the main CP and a program EPROM, and a chip D for the image RAM.
  • FIG. 74 is a functional block diagram showing an example of the internal configuration of the CD-ROM drive device.
  • the CD-RO drive is composed of a microcomputer including flash memory, a pre-servo circuit, a signal processing circuit, a ROM decoder, a host I / F, a pre-servo circuit, and a signal processing circuit that are bidirectionally connected to the microcomputer. To each other It consists of pickups and SRAMs connected in different directions, D / A connected to the ROM decoder, and buffer RAM connected to the host IZF. A motor M for driving a CD-ROM is connected to the signal processing circuit, and signals from the CD-ROM are read by a pickup. The rotation of this motor is controlled by the signals of the pre-servo circuit and signal processing circuit. Furthermore, D-A is connected with Sby force.
  • the CD-ROM drive is connected to a host computer via a host I / F.
  • a signal from the CD-ROM is read by a pickup under the control of a microphone opening computer, the read information is processed by a signal processing circuit, and the processed information is stored in an SRAM. Store. Furthermore, the information stored in the SRAM can be decoded by a ROM decoder, converted to analog signals via DZA, and then output from the speaker, and temporarily stored in the buffer RAM. After storing, it can be output to the host computer via the host IZF.
  • the chip MFA of this embodiment is used for a block portion of a microcomputer including a flash memory, a signal processing circuit, and the like, and a block of a buffer RAM and a host I / F.
  • the chip AD of the present embodiment can be used for the part. It is also possible to simply use chip MF for the microcomputer part including flash memory and chip D for the buffer RAM part.
  • FIG. 75 is a functional block diagram showing an example of the internal configuration of the game device.
  • This game machine has a main unit control unit, a speaker, CD-ROM, ROM cassette, display RAM (SDRAM: 4M) connected to a CRT, buffer RAM (DRAM: 4M) and keyboard connected to the main unit control unit. It is composed of The main unit control section consists of a main CPU, system ROM (mask ROM: 16M), DRAM (SDRAM: 4M), RAM (SRAM: 256k), sound processor, graphics processor, image compression processor, I / ⁇
  • a main CPU of a main body control unit controls according to a control program stored in a system ROM.
  • CD—R ⁇ M ROM cassette Image and sound information and instruction information from the keyboard are input via the IZo control circuit, and these information are stored in DRAM and RAM.
  • the information stored in the DRAM and RAM is processed into audio and video signals using a sound processor and a graphic processor, respectively, and the audio signal is output as sound from speakers, and the video signal is output to the display RAM. After storing temporarily, it can be displayed as an image on the CRT screen. At this time, the video signal is used by being compressed in the amount of information by an image compression processor and stored in a buffer RAM.
  • the chip MFA of the present embodiment is used for blocks such as a main CPU, a system ROM, a sound processor, and a graphic processor, and the present embodiment is used for blocks such as a DRAM and an image compression processor. It is also possible to simply use the chip AD for the main CPU, the chip MF for the system ROM, and the chip D for the DRAM, RAM, and buffer RAM.
  • FIG. 76 is a functional block diagram showing an example of the internal configuration of the PDA.
  • This PDA consists of a microcomputer including a flash memory consisting of a graphic control circuit, a handwriting input circuit, a memory control circuit, a security management circuit, and a communication control circuit; an LCD connected to the microcomputer's graphic control circuit; Digitizer via A / D connected to power circuit, system memory (mask ROM: 16M) connected to memory control circuit, IC card connected to security management circuit, IR connected to communication control circuit It consists of IF, RS—232C, and a PCMCIA card via a PCMCIA control circuit.
  • This microphone port computer is connected to PHS, GSM, ADC, etc. from the communication control circuit via the network.
  • This PDA is controlled by a memory control circuit according to a control program stored in a system memory, converts information written using a digitizer into digital signals by A / D, and stores it in a handwriting input circuit.
  • the information stored in the handwriting input circuit can be displayed on an LCD screen after signal processing using a graphic control circuit.
  • security Information such as security management information can also be displayed on the LCD screen via the graphic control circuit.
  • communication with PHS, GSM, ADC, etc. can be performed by controlling a communication control circuit via a network, and a PCMCIA card via an IR-IF, RS-232C, PCMCIA control circuit. Information from such sources can also be imported into the microcomputer. The information on the IC card is used for security management by a security management circuit.
  • the chip MFA of the present embodiment is used for a block portion of a micro computer including a flash memory including a graphic control circuit, a handwriting input circuit, a memory control circuit, a security management circuit, and a communication control circuit. You can also simply use chip D for parts such as graphic control circuits and handwriting input circuits.
  • FIG. 77 is a functional block diagram showing an example of the internal configuration of the mobile communication device.
  • This mobile communication device is connected to a CPU including flash memory, a CH codec, an LCD controller / driver, and an IC card connected to the CPU, to a CH codec, and connected via a modem. It consists of an RFZ IF, a speech codec, and an LCD connected to the LCD controller / driver.
  • An antenna is connected to the RF / IF, and a speaker and a microphone are connected to the speech codec.
  • control is performed by a program stored in the flash memory of the CPU, and when a signal is received, a signal from an antenna is received via RF / IF and modulated using a modem. Then, the modulated signal can be converted into an audio signal using a CH codec and a speech codec, and output as audio from a speaker.
  • the voice signal from the microphone is converted using a speech codec and CH codec, demodulated using a modem, and then transmitted from the antenna via RF / IF. can do.
  • the chip MFA of the present embodiment is used for a block part such as a CPU and a CH codec, and an LCD controller Z driver and the like are used.
  • the chip AD of the present embodiment can be used. It is also possible to simply use a chip MF for the CPU part.
  • the semiconductor integrated circuit device configured by combining the chip MF, the chip MFA, the chip AD, the chip D, and the like according to the present embodiment is a car navigation system, a CD-ROM drive device, a game device, a PDA It can be widely applied to multimedia devices such as mobile communication devices, devices and systems such as information home appliances, and the like.
  • the number of external connection terminals is reduced by using a package structure in which two types of chips, a chip MF using a CPU and a flash memory, and a chip D using a DRAM, are integrated into one package. It is possible to reduce the mounting area by reducing the number of chips and by combining two types of chips into one package, and to reduce the cost of the semiconductor integrated circuit device. Further, it is possible to reduce the cost of equipment and systems using the semiconductor integrated circuit device.
  • chip MF and chip D each have a chip MFA or chip AD with a built-in logic circuit such as an AS IC, and if the DRAM is a synchronous DRAM, make the external connection terminals common. As a result, the number of external connection terminals can be further reduced and cost can be reduced.
  • weight control is unnecessary by using a chip AD equipped with a DRAM and a logic circuit such as ASIC, so that external
  • the access operation to the DRAM can be performed from the logic circuit during the self-refresh period of the DRAM, the speed of data transfer between the outside and the chip AD can be increased.
  • the CPU itself controls the time and realizes one clock cycle, it is not necessary to exchange wait signals, so that high-speed access can be performed. Further, the speed of processing in equipment and systems using the semiconductor integrated circuit device can be increased.
  • chip AD on which DRAM and logic circuits are mounted
  • chip MF on which CPU and flash memory are mounted
  • chip MFA chip MFA
  • the processing timing itself can be controlled from the CPU, that is, the processing timing itself can be known in the CPU program. Thus, it is possible to easily create a program for a semiconductor integrated circuit device.
  • Dividing DRAM, logic, flash memory, etc. with different power levels into two or more chips reduces the load on the process, so these are mixedly formed on one chip
  • the chip manufacturing cost can be greatly reduced as compared with the case.
  • the chip mounting area is greatly increased by mounting two types of chips, a chip MF using CP memory and flash memory, and a chip D using DRAM, in an ultra-thin stacked package and forming an on-package. Can be reduced.
  • the semiconductor integrated circuit device includes a first chip in which a flash memory and a logic circuit such as an AS IC are formed in a microcomputer including a CPU, a DRA, Functional blocks in a package structure in which multiple types of semiconductor chips, such as one or more second chips that form a logic circuit such as an ASIC, are housed in the same package so that signals can be input and output from each other.
  • a microcomputer including a CPU, a DRA
  • the number of external connection terminals It is useful for semiconductor integrated circuit devices that can reduce cost and reduce the mounting area by integrating two types of chips into one package, and is also useful for multimedia devices using this semiconductor integrated circuit device. It can be widely applied to devices such as information home appliances.

Abstract

L'invention porte sur un circuit semi-conducteur intégré renfermant deux types de puces, l'une comportant l'unité centrale et une mémoire flash, et l'autre, une DRAM, réunies dans un même boîtier. Cette structure réduit le nombre des connexions extérieures et la surface de montage du CI, et abaisse le coût de fabrication. Le susdit circuit comporte une puce (MF) sur laquelle sont montés les éléments constitutifs d'un micro-ordinateur, à savoir une unité centrale, une mémoire et des circuits périphériques et une mémoire flash, et une puce (AD) sur laquelle sont montés: une DRAM et un circuit logique par exemple un ASIC. Dans les connexions entre la puce (MF) et la puce (AD) les bornes d'adressage (A0-A10), les bornes d'E/S de données (D0-D31), la borne d'alimentation (Vcc), la borne de terre (Vss) et les bornes de commande telles que les bornes d'échantillonnage des adresses de rangées (RAS), ou les ou les bornes d'échantillonnage des adresses de colonnes (CASL, CASH, CASHL, CASHH) sont raccordées aux mêmes bornes de raccordement extérieur du circuit semi-conducteur intégré à un seul boîtier.
PCT/JP1996/003550 1996-12-04 1996-12-04 Dispositif de circuit semi-conducteur integre WO1998025213A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
PCT/JP1996/003550 WO1998025213A1 (fr) 1996-12-04 1996-12-04 Dispositif de circuit semi-conducteur integre
AU10404/97A AU1040497A (en) 1996-12-04 1996-12-04 Semiconductor integrated circuit device
JP52543298A JP3942198B2 (ja) 1996-12-04 1996-12-04 半導体集積回路装置
TW086100626A TW326104B (en) 1996-12-04 1997-01-21 Semiconductor integrated circuit apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP1996/003550 WO1998025213A1 (fr) 1996-12-04 1996-12-04 Dispositif de circuit semi-conducteur integre

Publications (1)

Publication Number Publication Date
WO1998025213A1 true WO1998025213A1 (fr) 1998-06-11

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP1996/003550 WO1998025213A1 (fr) 1996-12-04 1996-12-04 Dispositif de circuit semi-conducteur integre

Country Status (4)

Country Link
JP (1) JP3942198B2 (fr)
AU (1) AU1040497A (fr)
TW (1) TW326104B (fr)
WO (1) WO1998025213A1 (fr)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004049168A1 (fr) * 2002-11-28 2004-06-10 Renesas Technology Corp. Module de memoire, systeme de memoire, et dispositif d'informations
JP2005332555A (ja) * 2004-04-23 2005-12-02 Oki Electric Ind Co Ltd テスト回路、テスト方法、及び半導体集積回路装置
JP5956708B1 (ja) * 2015-11-30 2016-07-27 株式会社ＰＥＺＹ Ｃｏｍｐｕｔｉｎｇ ダイ及びパッケージ、並びに、ダイの製造方法及びパッケージの生成方法
JP2022503788A (ja) * 2018-12-29 2022-01-12 中芯集成電路（寧波）有限公司 マイクロコントローラ及びその製造方法

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JPH04273470A (ja) * 1991-02-28 1992-09-29 Hitachi Ltd 超小型電子機器
JPH06251172A (ja) * 1993-02-26 1994-09-09 Hitachi Ltd 半導体集積回路システム装置
JPH07105173A (ja) * 1993-09-30 1995-04-21 Hitachi Ltd データ処理装置
JPH08147966A (ja) * 1994-09-21 1996-06-07 Matsushita Electric Ind Co Ltd 半導体集積回路
JPH08167703A (ja) * 1994-10-11 1996-06-25 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法、ならびにメモリコアチップ及びメモリ周辺回路チップ

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JPH02219254A (ja) * 1989-02-20 1990-08-31 Hitachi Ltd 半導体集積回路装置
JPH04273470A (ja) * 1991-02-28 1992-09-29 Hitachi Ltd 超小型電子機器
JPH06251172A (ja) * 1993-02-26 1994-09-09 Hitachi Ltd 半導体集積回路システム装置
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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004049168A1 (fr) * 2002-11-28 2004-06-10 Renesas Technology Corp. Module de memoire, systeme de memoire, et dispositif d'informations
KR100786603B1 (ko) * 2002-11-28 2007-12-21 가부시끼가이샤 르네사스 테크놀로지 메모리 모듈, 메모리시스템 및 정보기기
US7613880B2 (en) 2002-11-28 2009-11-03 Renesas Technology Corp. Memory module, memory system, and information device
US7991954B2 (en) 2002-11-28 2011-08-02 Renesas Electronics Corporation Memory module, memory system, and information device
US8185690B2 (en) 2002-11-28 2012-05-22 Renesas Electronics Corporation Memory module, memory system, and information device
JP2005332555A (ja) * 2004-04-23 2005-12-02 Oki Electric Ind Co Ltd テスト回路、テスト方法、及び半導体集積回路装置
JP5956708B1 (ja) * 2015-11-30 2016-07-27 株式会社ＰＥＺＹ Ｃｏｍｐｕｔｉｎｇ ダイ及びパッケージ、並びに、ダイの製造方法及びパッケージの生成方法
JP2022503788A (ja) * 2018-12-29 2022-01-12 中芯集成電路（寧波）有限公司 マイクロコントローラ及びその製造方法
JP7083965B2 (ja) 2018-12-29 2022-06-13 中芯集成電路（寧波）有限公司 マイクロコントローラ及びその製造方法

Also Published As

Publication number Publication date
TW326104B (en) 1998-02-01
JP3942198B2 (ja) 2007-07-11
AU1040497A (en) 1998-06-29

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