WO1997017759A1 - Systeme de commande d'accord - Google Patents

Systeme de commande d'accord Download PDF

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Publication number
WO1997017759A1
WO1997017759A1 PCT/JP1996/001097 JP9601097W WO9717759A1 WO 1997017759 A1 WO1997017759 A1 WO 1997017759A1 JP 9601097 W JP9601097 W JP 9601097W WO 9717759 A1 WO9717759 A1 WO 9717759A1
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WO
WIPO (PCT)
Prior art keywords
circuit
tuning
phase shift
signal
input
Prior art date
Application number
PCT/JP1996/001097
Other languages
English (en)
Japanese (ja)
Inventor
Takeshi Ikeda
Tadataka Ohe
Akira Okamoto
Original Assignee
Takeshi Ikeda
Tadataka Ohe
Akira Okamoto
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Takeshi Ikeda, Tadataka Ohe, Akira Okamoto filed Critical Takeshi Ikeda
Priority to AU53481/96A priority Critical patent/AU5348196A/en
Priority to JP51804597A priority patent/JP3764483B2/ja
Priority to KR1019980703018A priority patent/KR100350400B1/ko
Publication of WO1997017759A1 publication Critical patent/WO1997017759A1/fr
Priority to HK99100745A priority patent/HK1015979A1/xx

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D13/00—Circuits for comparing the phase or frequency of two mutually-independent oscillations
    • H03D13/003—Circuits for comparing the phase or frequency of two mutually-independent oscillations in which both oscillations are converted by logic means into pulses which are applied to filtering or integrating means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
    • H03J3/00—Continuous tuning
    • H03J3/02—Details
    • H03J3/06—Arrangements for obtaining constant bandwidth or gain throughout tuning range or ranges
    • H03J3/08—Arrangements for obtaining constant bandwidth or gain throughout tuning range or ranges by varying a second parameter simultaneously with the tuning, e.g. coupling bandpass filter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/24—Automatic control of frequency or phase; Synchronisation using a reference signal directly applied to the generator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
    • H03J1/00—Details of adjusting, driving, indicating, or mechanical control arrangements for resonant circuits in general

Definitions

  • the present invention relates to a tuning control method for passing only a predetermined frequency signal.
  • an intermediate-frequency amplifier circuit of a superheterodyne receiver includes a function as a filter, and this intermediate-frequency amplifier circuit generally uses a plurality of sets of intermediate-frequency transformers (IFTs) and capacitors to achieve a desired function. Realizes frequency characteristics. For example, in the case of an AM receiver, a center frequency of 455 kHz is set, and a predetermined amount of attenuation is set when the center frequency is detuned by 9 kHz. I have. In some cases, a single ceramic filter is used instead of a plurality of sets of intermediate frequency transformers to achieve desired frequency characteristics.
  • IFTs intermediate-frequency transformers
  • the configuration of the intermediate frequency amplifier circuit which is a filter for tuning, includes an intermediate frequency transformer and a ceramics filter. It was difficult to integrate on top.
  • the local oscillation circuit combined with this intermediate frequency amplifier circuit is simply realized by an LC oscillator using a local oscillation transformer, and when it is of high accuracy, realized by a PLL configuration using crystal oscillation. .
  • the local oscillation circuit has a PLL configuration, it is difficult to integrate the local oscillation circuit because it includes a voltage-controlled oscillator (VCO) that performs sine wave oscillation, and the hybrid IC is used in part.
  • VCO voltage-controlled oscillator
  • the present invention has been conceived to solve such a problem, and an object thereof is to provide a new tuning control method suitable for integration.
  • the tuning control method includes two cascade-connected all-pass type phase shift circuits, and the output of the subsequent phase shift circuit is fed back to the input side of the preceding phase shift circuit as a feedback signal.
  • a tuning circuit that adds the feedback signal and the input signal and inputs the feedback signal and the input signal to the phase shift circuit at the preceding stage, and passes only a signal near a predetermined frequency; and a tuning circuit near the predetermined frequency to the tuning circuit.
  • the tuning frequency By controlling the phase difference between the input and output signals of one of the phase shift circuits included in the tuning circuit to be, for example, 90 °, the tuning frequency always changes following the frequency of the input signal. And both frequencies can be matched.
  • FIG. 1 is a configuration diagram of a tuning mechanism which is an embodiment to which a tuning control method of the present invention is applied,
  • FIG. 2 is a circuit diagram showing a detailed configuration of the tuning circuit
  • FIG. 3 is a circuit diagram extracted from the configuration of the previous phase shift circuit shown in FIG. 2, and FIG. 4 is a diagram showing input / output voltages and voltages appearing in the capacity shift circuit and the like of the phase shift circuit shown in FIG. Vector diagram showing the relationship between
  • Fig. 5 is a circuit diagram extracted from the configuration of the subsequent phase shift circuit shown in Fig. 2, and Fig. 6 is the relationship between the input / output voltage of the latter phase shift circuit and the voltage appearing in the capacity and the like.
  • FIG. 7 is a circuit diagram in which the whole of the two phase shift circuits and the voltage divider circuit shown in FIG. 2 are replaced with a circuit having a transfer function K 1,
  • FIG. 8 is a circuit diagram obtained by converting the circuit shown in FIG. 7 by Miller's theorem
  • FIG. 9 is a diagram showing tuning characteristics of the tuning circuit shown in FIG. 2
  • Fig. 10 is a diagram showing the phase relationship between the signals input to and output from the two phase shift circuits.
  • Fig. 11 is a diagram in which the tuning frequency is higher than the frequency of the signal input to the preceding phase shift circuit. Diagram showing the phase relationship between input and output signals of each phase shift circuit in the case,
  • FIG. 12 is a diagram showing the phase relationship between input and output signals of each phase shift circuit when the tuning frequency is lower than the signal frequency input to the preceding phase shift circuit
  • FIG. 13 is a circuit diagram showing a configuration of a frequency control circuit
  • FIG. 14 is a timing chart in the case where the tuning frequency of the tuning circuit is higher than the frequency of the signal input to the tuning circuit
  • FIG. 15 is a timing chart when the tuning frequency of the tuning circuit is lower than the frequency of the signal input to the tuning circuit
  • FIG. 16 is a circuit diagram showing another configuration example of the frequency control circuit.
  • FIG. 17 is a timing diagram when the tuning frequency is higher than the frequency of the signal input to the tuning circuit shown in FIG. 16,
  • FIG. 18 is a timing chart in the case where the tuning frequency is lower than the frequency of the signal input to the tuning circuit shown in FIG. 16,
  • Fig. 19 is a diagram showing the configuration of the tuning mechanism that also serves as FM detection.
  • FIG. 20 is a circuit diagram showing a detailed configuration of the frequency control circuit shown in FIG. 19,
  • FIG. 21 is a diagram showing a configuration of an FM receiver using the tuning mechanism shown in FIG. 22 is a diagram showing the configuration of a tuning mechanism using AM detection by synchronous rectification,
  • FIG. 23 is a diagram showing the detailed configuration of the synchronous rectifier circuit shown in FIG. 22,
  • FIG. 24 is a diagram showing a configuration of an AM receiver using the tuning mechanism shown in FIG. 22,
  • FIG. 25 is a circuit diagram showing a configuration of a phase shift circuit including an LR circuit,
  • FIG. 26 is a vector diagram showing the relationship between the input / output voltage of the phase shift circuit shown in FIG. 25 and the voltage appearing in the capacity and the like.
  • FIG. 27 is a circuit diagram showing another configuration of the phase shift circuit including the LR circuit, and
  • FIG. 28 is a diagram showing the input / output voltage of the phase shift circuit shown in FIG. Vector diagram showing the relationship of
  • FIG. 29 is a circuit diagram showing a second modification of the tuning circuit
  • FIG. 30 is a circuit diagram showing a configuration of a phase shift circuit including an LR circuit
  • FIG. 31 is a circuit diagram showing another configuration of the phase shift circuit including the LR circuit
  • FIG. 32 is a circuit diagram showing a fourth modification of the tuning circuit
  • FIG. 33 is a circuit diagram showing a fifth modification of the tuning circuit
  • FIG. 34 is a circuit diagram showing a sixth modification of the tuning circuit
  • FIG. 35 is a circuit diagram showing a seventh modification of the tuning circuit
  • FIG. 36 is a circuit diagram showing an eighth modification of the tuning circuit
  • Fig. 37 is a circuit diagram extracted from the configuration of the previous phase shift circuit shown in Fig. 36
  • Fig. 38 is the input / output voltage and capacity of the phase shift circuit shown in Fig. 37.
  • Vector diagram showing the relationship with the voltage appearing in
  • Fig. 39 is a circuit diagram extracted from the configuration of the subsequent phase shift circuit shown in Fig. 36.
  • Fig. 40 is the input / output voltage and capacity of the phase shift circuit shown in Fig. 39.
  • Vector diagram showing the relationship with the voltage appearing in
  • FIG. 41 is a circuit diagram showing a configuration of a phase shift circuit including an LR circuit
  • Fig. 42 is a vector diagram showing the relationship between the input / output voltage of the phase shift circuit shown in Fig. 41 and the voltage appearing in the capacity, etc.
  • FIG. 43 is a circuit diagram showing another configuration of the phase shift circuit including the LR circuit.
  • FIG. 44 is a vector diagram showing the relationship between the input / output voltage of the phase shift circuit shown in FIG. 43 and the voltage appearing in the capacity and the like.
  • FIG. 45 is a circuit diagram showing a tenth modification of the tuning circuit
  • FIG. 46 is a circuit diagram showing a first modification of the tuning circuit
  • FIG. 47 is a circuit diagram showing a twelfth modification of the tuning circuit.
  • Fig. 48 is a circuit diagram extracted from the configuration of the previous phase shift circuit shown in Fig. 47.
  • Fig. 49 is the input / output voltage and capacity of the phase shift circuit shown in Fig. 48.
  • Vector diagram showing the relationship with the voltage appearing in FIG. 50 is a circuit diagram extracted from the configuration of the subsequent phase shift circuit shown in FIG. 47.
  • FIG. 51 is an input / output voltage and capacity of the phase shift circuit shown in FIG. 50.
  • FIG. 52 is a circuit diagram showing a configuration of a phase shift circuit including an LR circuit
  • Fig. 53 is a vector diagram showing the relationship between the input / output voltage of the phase shift circuit shown in Fig. 52 and the voltage appearing in the inductor and the like.
  • FIG. 54 is a circuit diagram showing another configuration of the phase shift circuit including the LR circuit
  • FIG. 55 is a vector diagram showing the relationship between the input / output voltage of the phase shift circuit shown in FIG. 54 and the voltage appearing in the inductor and the like.
  • FIG. 56 is a circuit diagram showing a fourteenth modification of the tuning circuit
  • FIG. 57 is a circuit diagram showing a fifteenth modification of the tuning circuit.
  • FIG. 58 is a circuit diagram of a tuning circuit in which the variable resistor in the phase shift circuit shown in FIG. 3 is formed by a MOS type FET,
  • Fig. 59 is a circuit diagram of a tuning circuit that changes the overall tuning frequency by changing the capacitance of the capacitance.
  • FIG. 60 is a circuit diagram of a tuning circuit using an element other than FET as a variable resistor in each phase shift circuit shown in FIG. 2,
  • FIG. 61 is a circuit diagram in which a part necessary for the operation of the phase shift circuit in the configuration of the operational amplifier is extracted.
  • the tuning control method of the present invention when the time constants of the two phase shift circuits included in the tuning circuit are set to the same value, the phase difference between the input and output signals of each of the two phase shift circuits is 90%. Paying attention to the fact that the phase shift amount becomes 90 ° or 270 °, the phase shift amount of one phase shift circuit is set to 90 when an AC signal of a certain frequency is input. Alternatively, by controlling the tuning frequency to approach It is characterized in that it is controlled to match the frequency of the signal.
  • FIG. 1 is a diagram showing a configuration of a tuning mechanism according to an embodiment to which a tuning control method of the present invention is applied.
  • the tuning mechanism shown in FIG. 1 includes a tuning circuit 1 that functions as a filter that passes a signal near a certain frequency, and a frequency control circuit 2 that controls a pass center frequency of the tuning circuit 1.
  • Tuning circuit 1 includes two phase shifting circuits, takes out the output of the subsequent phase shifting circuit as the output of tuning circuit 1, and feeds back this signal via a feedback resistor. By adding the input signal that is input and the feedback signal that is fed back via the feedback resistor and inputting the result to the previous phase shift circuit, the total phase shift amount of the two phase shift circuits becomes 360 °. A predetermined tuning operation is performed at a frequency.
  • the phase shift amount in each phase shift circuit is 90 °.
  • the tuning frequency will be adjusted to the frequency of the input signal. Can be matched.
  • the tuning circuit 1 has a configuration in which the tuning frequency can be arbitrarily set within a certain range by changing the amount of phase shift between the two phase shift circuits by a control signal input from the outside. The detailed configuration and detailed operation of the tuning circuit 1 will be described later.
  • the frequency control circuit 2 receives two types of signals that are input / output to one of the phase shift circuits included in the tuning circuit 1, and when the phase difference between these two signals is shifted from 90 °, The tuning frequency of the tuning circuit 1 is controlled so as to eliminate this deviation.
  • the frequency control circuit 2 includes a phase difference detection circuit 3 and a control voltage generation circuit 4.
  • the phase difference detection circuit 3 has a duty ratio of 50% and a phase shift amount of 90% when the phase shift amount of the other phase shift circuit included in the tuning circuit 1 is 90 °. When it deviates from that, a rectangular wave signal whose duty ratio deviates from 50% is output in accordance with the deviation.
  • the control voltage generation circuit 4 generates a voltage corresponding to the duty ratio of the rectangular wave signal output from the phase difference detection circuit 3, and adds the generated voltage to a predetermined bias voltage.
  • the adjusted voltage is output to the tuning circuit 1 as a control signal.
  • phase difference detection circuit 3 and the control voltage generation circuit 4 included in the frequency control circuit 2 will be described later.
  • FIG. 2 is a circuit diagram showing a detailed configuration of the tuning circuit 1.
  • the tuning circuit 1 shown in the figure shifts the phase of each input AC signal by a predetermined amount, so that a total of 360 is obtained at a predetermined frequency.
  • a voltage divider consisting of two phase shifters 110 C and 130 C, and a resistor 16 2 and 16 4 provided on the output side of the subsequent phase shift circuit 130 C Circuit 160 and that of feedback resistor 170 and input resistor 174 (input resistor 174 has n times the resistance of feedback resistor 170)
  • it is configured to include an adding circuit for adding the divided output (feedback signal) of the voltage dividing circuit 160 and the signal (input signal) input to the input terminal 190 at a predetermined ratio. ing.
  • FIG. 3 shows a configuration extracted from the phase shift circuit 110C of the preceding stage shown in FIG.
  • the phase shift circuit 110C at the front stage shown in the figure shifts the phase of the AC signal input to the input terminal 122 by a predetermined amount from the operational amplifier 112, which is a type of differential amplifier.
  • the resistances of the resistor 118 and the resistor 120 are set to be the same.
  • the resistance of the variable resistor 116 can be changed according to an external control voltage.For example, as shown in FIG. 3, an FET channel is used as a resistor, and a control input shown in FIG. 2 is used.
  • the resistance value is set by applying a control voltage supplied from the outside via a terminal 194 to the gate.
  • the vector obtained by adding the voltage VC1 across the resistor 118 to the input voltage Ei is the voltage (divided output) E o 'at the connection point between the resistors 121 and 123.
  • FIG. 4 is a vector diagram showing the relationship between the input / output voltage of the phase shift circuit 110 C at the preceding stage and the voltage appearing in the capacity and the like.
  • the input voltage Ei and the divided voltage Eo ' differ only in the direction in which the voltage VC1 is synthesized. Its absolute value will be equal. Therefore, the relationship between the input voltage E i and the magnitude and phase of the divided output E o 'is represented by an isosceles triangle with the input voltage E i and the divided output E o' as the hypotenuse and the base of which is twice the voltage VC1. It can be seen that the amplitude of the divided voltage output E o 'is the same as the amplitude of the input signal regardless of the frequency, and the phase shift amount is expressed by 01 shown in FIG. The phase shift amount 01 changes from 180 ° to 360 ° in the clockwise direction (phase lag direction) based on the input voltage E i according to the frequency.
  • FIG. 5 shows an extracted configuration of the phase shift circuit 130C at the subsequent stage shown in FIG.
  • the phase-shift circuit 130C at the subsequent stage shown in the figure shifts the phase of the signal input to the operational amplifier 1332, which is a type of differential amplifier, and the input terminal 142 by a predetermined amount.
  • the variable resistor 1 3 6 to be input to the non-inverting input terminal of the operational amplifier 13 2 and the resistor inserted between the input terminal 14 2 and the inverting input terminal of the operational amplifier 13 2 1 3 8, resistors 14 1 and 14 3 connected to the output terminal of the operational amplifier 13 2 to form a voltage divider circuit, and the output terminal of this voltage divider circuit and the inverting input terminal of the operational amplifier 13 2 And a resistor 140 connected between them.
  • the resistances of the resistor 1 38 and the resistor 140 are set to be the same.
  • the resistance of the variable resistor 1336 can be changed according to an external control voltage, and a control voltage supplied from the outside via a control input terminal 1995 shown in FIG. 2 is applied to the gate. By doing so, the resistance value is set.
  • FIG. 6 is a vector diagram showing the relationship between the input / output voltage of the subsequent phase shift circuit 130 C and the voltage appearing in the capacity and the like.
  • the input voltage E i and the divided output E o ' differ only in the direction in which the voltage VR2 is synthesized. Its absolute value will be equal. Therefore, the relationship between the input voltage E i and the magnitude and phase of the divided output E o 'is represented by an isosceles triangle with the input voltage E i and the divided output E o' as the hypotenuse and the base twice the voltage VR2. It can be seen that the amplitude of the divided voltage output E o 'is the same as the amplitude of the input signal regardless of the frequency, and that the phase shift amount is expressed by ⁇ zi 2 shown in FIG.
  • a gain greater than 1 can be obtained by adjusting the values of R41 and R43, and the amplitude of the output voltage Eo is constant even if the frequency changes, as shown in Fig. 6, and only the phase is adjusted by a predetermined amount. Can be shifted.
  • phase of each of the two phase shift circuits 110C and 130C is shifted by a predetermined amount, and as shown in FIGS. 4 and 6, the phase of the entire tuning circuit 1 is changed.
  • the shift amount is 360 ° at a predetermined frequency.
  • the output of the subsequent phase shift circuit 130 C is taken out from the output terminal 192 as the output of the tuning circuit 1 as shown in FIG. 2, and the output of the phase shift circuit 130 C is divided by a voltage dividing circuit.
  • the signal passed through 160 is fed back to the input side of the previous phase shift circuit 110 C via the feedback resistor 170. Then, the signal that has been fed back and the signal that is input via the input resistor 174 are added, and the added signal is input to the phase shift circuit 110C at the preceding stage.
  • the total amount of phase shift at a predetermined frequency is 360 ° by the two phase shift circuits 110 C and 130 C, and at this time, the two phase shift circuits 110 C, 130 C,
  • the loop gain of the feedback loop by the voltage dividing circuit 160 and the feedback resistor 170 is set to 1 or less.
  • the gain can be given to the tuning circuit 1 itself.
  • the signal amplitude can be amplified simultaneously with the tuning operation.
  • FIG. 7 is a circuit diagram in which the entirety of the two phase shift circuits 110 C and 130 C and the voltage divider circuit 160 having the above-described configuration is replaced with a circuit having a transfer function K1, and the transfer function K1
  • a feedback resistor 170 having a resistor R0 is connected in parallel with a circuit having a resistor R0, and an input resistor 174 having a resistance value (nRO) n times as large as the feedback resistor 170 is connected in series.
  • FIG. 8 is a circuit diagram obtained by converting the circuit shown in FIG. 7 by Miller's theorem, and the transfer function A of the whole system after the conversion is
  • K2 ⁇ a, (1 ⁇ T, s) / (l + Tis)... (2)
  • the transfer function ⁇ 3 of the subsequent phase shift circuit 130 C is ⁇ 2
  • K3 a, (1 -T2 s) / (1 + T, s) ⁇ ⁇ ⁇ ⁇ (3)
  • a 2 is the gain of the phase shift circuit 130C
  • a 2 (1 + R41 / R43)> 1.
  • the signal amplitude is 1 / a through the voltage divider circuit 160! Assuming that it attenuates to a 2, the overall transfer function K1 when two phase shift circuits 110 C and 130 C and a voltage divider circuit 160 are cascaded is
  • K1 - ⁇ 1 + (T s) 2 - 2 T s ⁇ / ⁇ 1 + (Ts) 2 +2 T s ⁇
  • phase shift circuit 1 1 1 by changing each resistance value of the variable resistor 1 16 in the preceding phase shift circuit 110 C and the variable resistor 1 36 included in the subsequent phase shift circuit 130 C, the phase shift circuit 1 1 1 1
  • the time constant of each CR circuit included in 0 C and 130 C can be changed, and the tuning frequency ⁇ can be changed arbitrarily within a certain range.
  • a voltage dividing circuit is formed by the feedback resistor 170 and the input impedance of the all-pass circuit.
  • the loop gain of the feedback loop including the all-pass circuit is smaller than the absolute value of the transfer function K1.
  • the input impedance of the all-pass circuit is the input impedance of the previous stage phase shift circuit 110 C, which consists of the input resistance 1 18 of the operational amplifier 1 12 and the variable resistance 1 16 and the capacity 1 1 4 This is nothing but the input impedance formed by connecting the series impedance of the CR circuit in parallel. Therefore, to compensate for the loss of the loop gain of the feedback loop due to the input impedance of the all-pass circuit, it is necessary to set the gain of the all-pass circuit itself to 1 or more.
  • the gain when the phase shift circuit 1 10 C operates as an inverting amplifier is — R 20 no R 18,
  • the gain is always 1 irrespective of the resistance ratio of resistor 118 and resistor 120, so the resistance ratio of resistor 118 and resistor 120 is not 1.
  • phase shift circuit 110 C it is possible to set the gain of the phase shift circuit 110 C to 1 or more while maintaining the resistance ratio of the resistors 1 18 and 120 to 1.
  • a voltage divider consisting of resistors 141 and 1443 is added to the output side of the phase shifter 130C, and feedback to the inverting input terminal of the operational amplifier 132 is performed via this voltage divider. This makes it possible to set the gain of the phase shift circuit 130 C to 1 or more while maintaining the resistance ratio of the resistances 1338 and 140 to 1.
  • ⁇ 2 tan ⁇ 2 ⁇ 2 / (1 - ⁇ 2 ⁇ , 2 ) ⁇ ⁇ ⁇ ⁇ (7)
  • FIG. 10 is a diagram showing the phase relationship between the signals input to and output from the two phase shift circuits 110C and 130C, and the signals input to the preceding phase shift circuit 110C. This shows the case where the frequency is equal to the tuning frequency.
  • FIG. 11 is a diagram showing the phase relationship between input and output signals of each phase shift circuit when the tuning frequency is higher than the frequency of the signal input to the preceding phase shift circuit 110C.
  • the case where the tuning frequency is higher than the frequency of the signal input to the preceding phase shift circuit 110C is the case where the frequency of the input signal is relatively lower than the tuning frequency.
  • the phase shift amount 0 1 of the first-stage phase shift circuit 110 C is smaller than 270 °
  • the phase shift amount of the second-stage phase shift circuit 130 C is 130 °.
  • the shift amount 02 is smaller than 90 °. Therefore, 0 1 and 02 are represented as shown in Fig. 11 (A) and Fig. 11 (B), respectively, and when two phase shift circuits 110 C and 130 C are connected in cascade. As shown in FIG. 11 (C), the sum of the phase shift amounts becomes smaller than 360 °.
  • FIG. 2 is a diagram showing the phase relationship between input and output signals of each phase shift circuit when the tuning frequency is lower than the signal frequency input to the preceding phase shift circuit 110C.
  • the case where the tuning frequency is lower than the frequency of the signal input to the preceding phase shift circuit 110C is the case where the frequency of the input signal is relatively higher than the tuning frequency.
  • the phase shift amount 0 1 of the preceding phase shift circuit 110 C is 270.
  • the phase shift amount 02 of the subsequent phase shift circuit 130 C becomes larger than 90 °. Therefore, 0 1 and 02 are represented as shown in Fig. 12 ( ⁇ ) and Fig. 12 ( ⁇ ), respectively, and when two phase shift circuits 1 1 0 C and 1 3 0 C are cascaded.
  • the sum of the phase shift amounts of the two is shown in Fig. 12 (C). Thus, it is larger than 360 °.
  • the absolute values of 01 and 02 described above may be reduced, and more specifically, the tuning shown in FIG.
  • the voltage VR1 across the resistor 1 16 and the voltage VR2 across the variable resistor 1 36 may be reduced.
  • the variable resistors 1 16 and 1 36 are formed by n-channel FETs, it is sufficient to increase the gate voltage and reduce the channel resistance.c
  • the tuning circuit 1 described above Set the resistance values of the resistors 118 and 120 in the phase shift circuit 110C to the same value, and set the resistance of the resistor 130 and the resistor 140 in the phase shift circuit 130C to the same value.
  • the values are set to the same value, it is possible to prevent amplitude fluctuations when the tuning frequency is changed, and to obtain a tuning output having a substantially constant amplitude.
  • the amplitude fluctuation of the tuning output it is possible to increase the value of Q of the tuning circuit 1 by increasing the resistance ratio n described above.
  • the resistance ratio n cannot be set to a very large value to prevent such oscillation, and the value of Q of the tuning circuit 1 also becomes small.
  • the tuning output of the tuning circuit 1 since the tuning output of the tuning circuit 1 does not cause amplitude fluctuation even if the resistance ratio n is set to a large value, the resistance value n is increased and the value of Q is increased. can do.
  • a signal attenuated through the voltage dividing circuit 160 is used as a feedback signal, and a signal before being input to the voltage dividing circuit 160 is taken out as an output of the tuning circuit 1 so that a predetermined signal can be selected from the input signals.
  • a predetermined amplification can be performed on the extracted signal.
  • one of the voltage dividing circuits connected to the output terminals of the operational amplifiers 112 and 132 in each phase shift circuit included in the tuning circuit 1 One of the voltage dividing circuits may be omitted, or the voltage dividing ratio may be set to 1.
  • the output terminal of the operational amplifier 112 may be directly connected to one end of the resistor 120 without omitting the voltage dividing circuit in the phase shift circuit 110C.
  • the voltage divider is omitted for one of the two cascaded phase shifters.
  • a gain setting of 1 Te by setting the gain of the other phase shift circuit 1 1 0 C to a value greater than 1, c
  • the same tuning operation as the tuning circuit 1 shown in FIG. 2 is performed, If the amplification operation is not required, the voltage dividing circuit 160 at the subsequent stage of the phase shift circuit 130 C may be omitted, and the output of the phase shift circuit 130 C may be directly fed back to the preceding stage.
  • the voltage division ratio may be set to 1 by making the resistance value of the resistor 162 in the voltage dividing circuit 160 extremely small.
  • FIG. 13 is a circuit diagram showing the configuration of the frequency control circuit 2, and shows the detailed configurations of the phase difference detection circuit 3 and the control voltage generation circuit 4 included in the frequency control circuit 2.
  • the phase difference detection circuit 3 shown in FIG. 13 includes a buffer 30 such as a source follower, two voltage comparators 31 and 32, and an EX-OR (exclusive OR) gate 33. It is configured.
  • the inverting input terminals of the two voltage comparators 31 and 32 are both grounded, and the non-inverting input terminal of one of the voltage comparators 31 has a signal output from the control output terminal 196 of the tuning circuit 1.
  • the input signal of the subsequent phase shift circuit 130 C is input through the buffer 30, and the non-inverting input terminal of the other voltage comparator 32 is the control output terminal 19 9 7 of the tuning circuit 1.
  • Output signal of the subsequent phase shift circuit 130 C is input.
  • Each of the voltage comparators 31 and 32 outputs a square wave signal having a positive or negative voltage level depending on whether the voltage level of the signal input to the non-inverting input terminal is higher or lower than 0 V. That is, the voltage comparators 31 and 32 respectively output rectangular wave signals having the same frequency and phase as the signals output from the control output terminals 196 and 197 of the tuning circuit 1.
  • EX—OR gate 33 receives the square wave signals output from each of the voltage comparators 31 and 32 as inputs, and sets the positive voltage level of each square wave signal to logic H and negative polarity The voltage level of these two inputs is made to correspond to logic L, and the exclusive OR of these two inputs is calculated.
  • the control voltage generation circuit 4 shown in FIG. 13 includes a low-pass filter including a resistor 40 and a capacitance 41, a variable resistor 42 for generating a predetermined bias voltage, an operational amplifier 44, and a resistor. And an amplifier including a resistor 45 and a resistor 46.
  • the low-pass filter removes high-frequency components from the square wave signal output from the EX-OR gate 33 according to the time constant determined by the resistor 40 and the capacity 41. Therefore, the output voltage of the low-pass filter gradually increases when the duty ratio of the square wave signal output from the EX-OR gate 33 is larger than 50% (when the relative ratio of logic H is large). When the duty ratio of the square wave signal output from the EX-OR gate 33 is smaller than 50% (when the relative ratio of logic L is large), it gradually decreases.
  • the single-pass filter shown in FIG. 13 is inserted before the amplifier, it may be formed integrally with the amplifier by connecting a capacitor in parallel with the feedback resistor of the amplifier.
  • a resistor 45 is connected between the output terminal of the operational amplifier 44 and the inverting input terminal, and the inverting input terminal is grounded via the resistor 46.
  • the operational amplifier 44 functions as an amplifier having an amplification degree corresponding to the resistance ratio of the resistors 45 and 46.
  • the voltage amplified by the operational amplifier 44 is added to a predetermined bias voltage to generate a control voltage as described below, and then input to the tuning circuit 1.
  • a movable terminal of a variable resistor 42 having two fixed terminals connected to a positive power supply Vdd and a negative power supply V ss is connected via a resistor 43. Therefore, the bias circuit including the variable resistor 42 sets the voltage at the output terminal of the operational amplifier 44 to a predetermined bias voltage.
  • this variable resistance 42 is actually formed on a semiconductor substrate, it can be formed using an active element such as FET.
  • This bias circuit matches the tuning frequency of tuning circuit 1 with the frequency of the input signal.
  • the variable resistor 1 16 included in one phase shift circuit 110 C of the tuning circuit 1 and the variable resistor 13 included in the other phase shift circuit 130 C of the tuning circuit 1 It is provided to set the voltage to be applied to each gate of No. 6.
  • variable resistors 1 16 and 1 36 are configured using FETs, even if the same gate voltage is applied to each FET, if the source potential of each FET is different, the resistance values will be equal. May not be. For this reason, when actually constructing a circuit, the distributor 5 that generates two kinds of gate voltages that can be varied in conjunction with each other according to the output voltage of the control voltage generator 4 is synchronized with the control voltage generator 4. It is desirable to connect between circuit 1. Alternatively, the FETs may be selected so that the resistance values become equal when the same gate voltage is applied, and if such a selection is performed, the distributor 5 shown in FIG. 13 can be omitted. .
  • the frequency control circuit 2 of the present embodiment has such a detailed configuration. Next, the detailed operation will be described with different cases.
  • Fig. 14 is a timing chart when the tuning frequency of the tuning circuit 1 is higher than the frequency of the signal input to the tuning circuit 1, and shows the input / output timing of each component in the frequency control circuit 2.
  • 13A to 13F correspond to reference numerals A to F shown in the circuit diagram of FIG.
  • the phase shift amount 02 of the subsequent phase shift circuit 130 C becomes smaller than 90 °. Therefore, the two signals output from the two control output terminals 196 and 197 of the tuning circuit 1 are the control output ⁇ ⁇ shown in Fig. 14 (A) and the control output 1 shown in Fig. 14 (B), respectively. It has a phase relationship like the control output ⁇ shown in Fig. 1.
  • One voltage comparator 31 in the phase difference detection circuit 3 outputs an H-level signal when the voltage level of the control output ⁇ ⁇ is higher than 0 V. Therefore, the voltage comparator 31 outputs a signal having the same frequency and phase as the control output 1 as shown in FIG. 14 (C), that is, an H level when the voltage level of the control output ⁇ is positive, Conversely, when the voltage level of the control output ⁇ is negative, a rectangular wave signal that becomes L level is output. Similarly, the other voltage comparator 32 in the phase difference detection circuit 3 outputs an H-level signal when the voltage level of the control output is higher than 0 V. Therefore, from the voltage comparator 32, as shown in FIG.
  • EX—OR gate 33 outputs a square wave signal that goes high when the logic of each output of the two voltage comparators 31 and 32 is different, and goes low when the logic of each output is the same. .
  • the tuning frequency is higher than the frequency of the input signal of the tuning circuit 1
  • the phase shift amount 2 of the subsequent phase shift circuit 130 C becomes smaller than 90 °, and therefore, FIG. As shown in the figure, a rectangular wave signal with a duty ratio smaller than 50% is output.
  • the square-wave signal output from the EX-OR gate 33 is input to the non-inverting input terminal of the operational amplifier 44 via a single-pass filter composed of a resistor 40 and a capacitor 41 in the control voltage generating circuit 4. Is done.
  • This low-pass filter is used to remove high-frequency components from the input rectangular wave signal. If the duty ratio of the input rectangular wave signal is smaller than 50%, the low-pass filter shown in FIG. As shown in (F), the output voltage of the low-pass filter is lower than 0 V.
  • the output voltage of this low-pass filter is amplified at a predetermined amplification degree by an amplifier including an operational amplifier 44, and a predetermined bias voltage set by the variable resistor 42 is added. Then, by applying the added voltage to the distributor 5, each control voltage applied to the control input terminals 194 and 195 of the tuning circuit 1 is generated. Therefore, when the duty ratio of the rectangular wave signal output from the EX-OR gate 33 is smaller than 50%, these control voltages also change to lower ones.
  • Fig. 15 is a timing diagram when the tuning frequency of the tuning circuit 1 is lower than the frequency of the signal input to the tuning circuit 1, and shows the input / output timing of each component in the frequency control circuit 2. Have been. Similarly to FIG. 14, FIGS. 15 (A) to 15 (F) correspond to reference numerals A to F shown in the circuit diagram of FIG.
  • the phase shift amount 02 of the subsequent phase shift circuit 130C becomes larger than 90 ° as shown in FIG. Therefore, when observing the two signals output from the two control output terminals 196 and 197 of the tuning circuit 1, the control output ⁇ ⁇ shown in Fig. 15 (A) and the control output 1 shown in Fig. 15 (B) The phase relationship is like the control output 2 shown in Fig.
  • the voltage comparator 31 in the phase difference detection circuit 3 outputs a square wave signal which becomes H level when the voltage level of the control output ⁇ ⁇ is higher than 0 V (FIG. 15 (C)).
  • the voltage comparator 32 outputs a square wave signal which becomes H level when the voltage level of the control output ⁇ ⁇ is higher than 0 V (FIG. 15 (D)).
  • the EX-OR gate 33 outputs a rectangular wave signal which becomes H level when the logic of each output of these two voltage comparators 31 and 32 is different, and which becomes L level when the logic is the same. Therefore, when the tuning frequency is lower than the frequency of the input signal of the tuning circuit 1, the phase shift amount 2 of the subsequent phase shift circuit 130 C is 90. As shown in FIG. 15 (E), the duty ratio of the square wave signal output from the EX-OR gate 33 becomes larger than 50%.
  • the output voltage of the single-pass filter in the control voltage generation circuit 4 becomes higher than 0 V as shown in FIG. 15 (F), and the control voltage generation circuit 4 passes through the distributor 5 accordingly. Therefore, the control voltage applied to the tuning circuit 1 also changes to a higher value.
  • the tuning frequency of the tuning circuit 1 is changed to a higher value. Such control is repeated until there is no difference between the frequency of the input signal of the tuning circuit 1 and the tuning frequency, and after a predetermined time, the tuning frequency matches the frequency of the input signal.
  • control is performed such that the phase difference between the input and output signals of one phase shift circuit 13 ° C. of the tuning circuit 1 is 90 °.
  • the number always changes according to the frequency of the input signal, and both frequencies always match. Therefore, when the tuning mechanism of this embodiment is applied to, for example, a superheterodyne receiver, the tuning frequency can be easily matched to the frequency of a carrier such as an input broadcast wave.
  • the tuning circuit 1 and the frequency control circuit 2 included in the tuning mechanism of the present embodiment are configured by a voltage comparator, a gate, an operational amplifier, a capacitor, a resistor, and the like. Therefore, the entire tuning mechanism or the entire tuning mechanism and its peripheral circuits can be integrated on a semiconductor substrate.
  • the tuning frequency of the tuning circuit 1 changes so as to follow an input signal having a predetermined frequency, so that even if the characteristics of the circuit elements vary, the actual tuning characteristics are not affected, and are always Stable tuning characteristics are obtained.
  • the human control signal is always output. Since the control is performed so as to match the frequency, appropriate feedback is applied even when various element constants change, and the difference between the frequency of the human input signal and the tuning frequency is eliminated.
  • the phase difference detection circuit 3 in the frequency control circuit 2 whose detailed configuration is shown in FIG. 13 is configured using the EX-0 R gate 33, but may be configured using other elements. it can.
  • FIG. 16 is a detailed circuit diagram showing another configuration example of the frequency control circuit, which has a configuration in which the phase difference detection circuit 3 shown in FIG. 13 is replaced with a phase difference detection circuit 3A.
  • the phase difference detection circuit 3A shown in FIG. 16 has a buffer 30, two voltage comparators 31 and 32, and a tri-state circuit whose operation is controlled according to the output of one of the voltage comparators 31. And an external buffer 34.
  • This phase difference detection circuit 3A replaces the EX-OR gate 33 in the phase difference detection circuit 3 shown in FIG. 13 with a tri-state buffer 34, and also uses two voltage comparators 32 It has a configuration in which the connections of the input terminals are interchanged.
  • the tri-state buffer 34 may be replaced with an analog switch.
  • FIG. 17 is a timing chart in the case where the tuning frequency is higher than the frequency of the signal input to the tuning circuit 1 shown in FIG. 16, and the phase difference detection circuit 3 constituting the frequency control circuit is shown in FIG. The input / output timing of each of the configuration of the A and the control voltage generation circuit 4 is shown. 17 (A) to (F) correspond to reference signs A to F shown in the circuit diagram of FIG.
  • FIGS. 17 (A) to (C) The timing shown in FIGS. 17 (A) to (C) is the same as the timing shown in FIGS. 14 (A) to (C), and the timing of the tristate buffer 34 will be mainly described below. A description will be given focusing on the operation.
  • the output signal of one voltage comparator 31 is input to the control terminal of the tri-state buffer 34, and the tri-state buffer 34 is connected to the voltage comparator 32 according to the voltage level of this control terminal. Pass or cut off the output. For example, when the output signal of the voltage comparator 31 is at the H level, the signal output from the other voltage comparator 32 is passed as it is, and when the output of the voltage comparator 31 is at the L level, It goes into an impedance state.
  • the tristate buffer 34 operates as a buffer, that is, when the output of one of the voltage comparators 31 is at the H level
  • the output of the other voltage comparator 32 is longer in the L level period than in the H level period.
  • the output of the tristate buffer 34 is longer in the L level period than in the H level period.
  • the output voltage of the single-pass filter composed of the resistor 40 and the capacity 41 in the control voltage generation circuit 4 becomes lower than 0 V as shown in FIG. 17 (F). Accordingly, the control voltage fed back to the tuning circuit 1 also changes to a lower value.
  • the output of the tri-state buffer 34 is always 0 V in one half of one cycle, the output is detected as compared to the case using the EX-OR gate 33 as shown in Fig. 13.
  • the sensitivity is low, and the response speed of the control is slow.
  • FIG. 18 is a timing chart when the tuning frequency is lower than the frequency of the signal input to the tuning circuit 1 shown in FIG. 16, and the phase difference detection circuit 3 A constituting the frequency control circuit is shown in FIG. Also, the input / output timing of each configuration of the control voltage generation circuit 4 is shown. 18 (A) to 18 (F) correspond to reference signs A to F shown in the circuit diagram of FIG.
  • the output level of the tristate buffer 34 when the output of the voltage comparator 31 is at the H level is different from that described above. That is, when the output of the voltage comparator 31 is at the H level, the output of the tristate buffer 34 is longer in the H level period than in the L level period. When the output of the voltage comparator 31 is at the L level, the output of the tristate buffer 34 is always 0 V.
  • the output of the tristate buffer 34 is longer in the H level period than in the L level period.
  • the output voltage of the low-pass filter composed of the resistor 40 and the capacitor 41 becomes higher than 0 V as shown in Fig. 18 (F), and is fed back to the tuning circuit 1 accordingly.
  • the control voltage also changes to the higher one.
  • the control voltage to be fed back decreases and the tuning frequency is changed to a lower value.
  • the control voltage to be fed back increases and the tuning frequency is changed to a higher value. Therefore, the control is performed so that the tuning frequency always matches the frequency of the input signal.
  • this control voltage includes the same frequency component as the frequency change of the input signal of the tuning circuit 1, that is, the FM signal when the FM signal is considered as the input signal.
  • this frequency component is extracted as an FM detection signal.
  • FIG. 19 is a diagram showing a configuration of a tuning mechanism that also serves as FM detection.
  • the control voltage generation circuit 4 in the frequency control circuit 2 shown in FIG. 1 is replaced with a control voltage generation circuit 4A, and control is performed so that the control voltage generation circuit 4A feeds back to the tuning circuit 1.
  • the FM detection signal is extracted in parallel with the voltage.
  • FIG. 20 is a circuit diagram showing a detailed configuration of the frequency control circuit 2 shown in FIG. 19 c. A detailed configuration of the phase difference detection circuit 3 forming the frequency control circuit 2 is shown in FIG. The configuration of the control voltage generation circuit 4A is slightly different from that of the control voltage generation circuit 4 shown in FIG.
  • the control voltage generating circuit 4 A includes a port formed by a resistor 40 and a capacitor 41, a path-fill circuit, an operational amplifier 44, and an amplifier formed by resistors 45 and 46,
  • the point that the bias voltage of the control voltage applied to the tuning circuit 1 from the control voltage generating circuit 4 A can be arbitrarily changed by operating the variable resistor 42 is the same as the control voltage generating circuit 4 shown in FIG. .
  • the control voltage generation circuit 4A has the same configuration as the control voltage generation circuit shown in FIG. 13 and additionally has a second port-pass filter composed of a resistor 47 and a capacity 48. And a second amplifier composed of an operational amplifier 49 and resistors 50 and 51.
  • the first oral pass filter composed of the resistor 40 and the capacity 41 is provided for removing high-frequency components from the rectangular wave signal output from the phase difference detection circuit 3. From the first mouth-to-pass filter, a signal whose DC voltage level changes gradually according to the duty ratio of the rectangular wave signal described above is output.
  • the second low-pass filter composed of the resistor 47 and the capacity 48 is about 20 kHz or more from the square wave signal output from the phase difference detection circuit 3. Is provided to remove the high frequency components of From the second low-pass fill, an FM modulation signal such as an FM sound is output as an FM detection signal.
  • This FM detection signal is amplified by an amplifier including an operational amplifier 49 and the like, and is taken out of the control voltage generation circuit 4A.
  • FIG. 21 is a diagram showing a configuration of an FM receiver using the tuning mechanism shown in FIG.
  • the FM receiver shown in FIG. 21 is composed of the tuning circuit 1 and the frequency control circuit 2, the high-frequency amplifier circuit 10, the low-frequency amplifier circuit 12, and the spin circuit 1 shown in FIGS. 19 and 20. —Consists of force 14 and antenna 16.
  • the high frequency amplifier circuit 10 amplifies the FM wave received by the antenna 16 at a high frequency and inputs the amplified FM wave to the tuning circuit 1.
  • the tuning circuit 1 controls the tuning frequency to match the frequency of the input FM wave according to the control voltage from the frequency control circuit 2.
  • the low-frequency amplification circuit 12 performs low-frequency amplification on the FM detection signal output from the control voltage generation circuit 4A in the frequency control circuit 2, and outputs sound from the speaker 14. Instead of using the speaker 14, the sound may be converted into a sound by an earphone or the like.
  • the FM receiver shown in Fig. 21 uses the tuning circuit 1 to directly extract the FM wave of the desired frequency without using an LC circuit with a variable condenser and a single antenna at the input from the antenna 16.
  • the design of the input part becomes easy. Therefore, the antenna 16 can be formed of a short rod-shaped or string-shaped conductive material, and FM waves can be received efficiently. Specifically, it is possible to receive a desired FM wave with high sensitivity simply by forming an antenna 16 with a rod antenna used for a car radio or using the lead of an earphone as the antenna 16.
  • the bar antenna which has been indispensable in the past, can be eliminated.
  • the FM receiver since it is not necessary to use a bar antenna, almost all the components of the FM receiver including the tuning circuit 1, the frequency control circuit 2, the high-frequency amplifier circuit 10, etc. can be integrated on a semiconductor substrate. This makes it possible to form constituent circuits on one chip. Thus, by adjusting the time constant of the low-pass filter included in the control voltage generation circuit 4 A, it is possible to easily extract only the FM modulation signal from the FM-modulated signal input to the tuning circuit 1. If the tuning mechanism shown in Fig. 19 is applied to an FM receiver, an FM detection circuit separately provided after the tuning mechanism is not required, and the circuit configuration can be simplified.
  • a limiting circuit was provided between the tuning mechanism and the FM detection circuit to remove the effect of amplitude fluctuations and then perform FM detection, but the tuning mechanism shown in Fig. 20 Since the two voltage comparators in the phase difference detection circuit 3 convert the signal into a rectangular wave signal, there is no influence of the amplitude fluctuation, and the limit circuit that was conventionally required is not required.
  • FIGS. 19 and 20 illustrate the case where the FM detection signal is extracted from the control voltage generation circuit 4A in the frequency control circuit 2, but naturally, as in the case of the conventional receiver, the tuning is performed.
  • a limiter circuit and an FM detection circuit using various detection methods may be connected to the subsequent stage of the circuit 1 so as to obtain an FM detection signal.
  • the tuning circuit 1 of the present embodiment performs a total of 360 ° phase shift by the entire two phase shift circuits 110 C and 130 C during tuning. Therefore, by performing synchronous rectification on the input signal using the output signal of the tuning circuit 1 as a reference signal, only the same frequency component as the tuning frequency is extracted from various frequency components included in the input signal, and this synchronous rectified output is obtained. It can be used as an AM detection signal.
  • FIG. 22 is a diagram showing a configuration of a tuning mechanism using AM detection by synchronous rectification.
  • the tuning mechanism shown in the figure includes a synchronous rectifier circuit 6 and a low-pass filter (LPF) 6 connected to the subsequent stage in addition to the tuning circuit 1 and the frequency control circuit 2 shown in FIG. I have.
  • LPF low-pass filter
  • an operation of switching an input signal in synchronization with a certain reference signal can be said to be equivalent to mixing the reference signal and the input signal.
  • the frequency of the reference signal be: fr.
  • Performing synchronous rectification on an input signal using such a reference signal is equivalent to multiplying each signal that can be expressed by a trigonometric function.
  • the frequencies fl and f2 of the input signal and the frequency of the reference signal are obtained.
  • f 1 + fr the frequency components of f 1 one fr appears by multiplying the first signal in the input signal and the reference signal, the input signal
  • fl + Af + fr and f1 + ⁇ -fr frequency components appear.
  • each frequency component of 2 f 1 and 0 appears by multiplying the first signal by the reference signal, and 2 f + by multiplying the second signal by the reference signal.
  • the component of the frequency “0_ is a DC component, and since this DC component actually contains a modulation signal, this DC component and the other AC components (2 f + Af, 2 fl, ⁇ f ) To extract only the DC component, detection using synchronous rectification and tuning separation can be performed simultaneously.
  • FIG. 23 is a diagram showing a detailed configuration of the synchronous rectifier circuit 6 shown in FIG.
  • the synchronous rectifier circuit 6 shown in the figure includes a voltage comparator 60 and an analog switch (AS) 61.
  • the voltage comparator 60 In the voltage comparator 60, the inverting input terminal is grounded, and the output signal of the tuning circuit 1 is input to the non-inverting input terminal. Therefore, the voltage comparator 60 has a predetermined positive voltage when the output signal of the tuning circuit 1 is at a voltage level higher than 0 V, and has a predetermined negative voltage when the output signal is at a voltage level lower than 0 V. Outputs a rectangular wave signal with voltage.
  • the analog switch 61 switches the switching state according to the voltage level of the rectangular wave signal output from the voltage comparator 60. That is, output from the voltage comparator 60
  • the input rectangular wave signal has a predetermined positive voltage
  • the input signal of the tuning circuit 1 is passed, and when the input rectangular wave signal has a predetermined negative voltage, the input signal of the tuning circuit 1 is cut off.
  • the output of the analog switch 61 is input to the mouth-pass filter 7, and only the frequency component equal to the tuning frequency is extracted by the low-pass filter 7, and an AM detection signal is obtained.c
  • the tuning circuit 1 used in this embodiment is As described with reference to the detailed configuration shown in FIG. 2, the signal amplitude is theoretically not attenuated, and an output signal having a constant amplitude can always be obtained even when the tuning frequency changes.
  • the output amplitude slightly changes due to the change in the tuning frequency, and the type and variable FET of the variable resistors 1 16 and 1 36 Depending on the width, the output signal may be distorted.
  • the influence on the AM detection signal due to amplitude fluctuation and distortion caused by passing through the tuning circuit 1 is eliminated.
  • An AM detection signal having a good SN ratio can be extracted.
  • the tuning mechanism shown in Fig. 22 is particularly effective when integrated.
  • FIG. 24 is a diagram showing a configuration of an AM receiver using the tuning mechanism shown in FIG.
  • the AM receiver shown in Fig. 24 consists of a tuning circuit 1, a frequency control circuit 2, a synchronous rectifier circuit 6 and a low-pass filter 7, and a high-frequency amplifier circuit 10 and a single-pass filter 7 shown in Fig. 22. , Including low frequency amplifier circuit 12, speaker 14 and antenna 16 It is composed of
  • the AM wave received by the antenna 16 is high-frequency amplified by the high-frequency amplifier circuit 10 and then input to the tuning circuit 1.
  • the tuning frequency of the tuning circuit 1 is controlled by the frequency control circuit 2.
  • synchronous rectification is performed using the signal output from the tuning circuit 1, and the AM detection signal is output from the low-pass filter 7.
  • This AM detection signal is output from the speaker 14 after being amplified by the low frequency amplifier circuit 12.
  • each of the phase shift circuits 110C and 130C was configured to include a CR circuit, but the CR circuit was replaced with an LR circuit consisting of a resistor and an inductor.
  • a tuning circuit can also be configured using a phase circuit.
  • FIG. 25 is a circuit diagram showing another configuration of the phase shift circuit including the LR circuit, showing a configuration that can be replaced with the phase shift circuit 110C preceding the tuning circuit 1 shown in FIG. I have.
  • the phase shift circuit 110L shown in the figure is a CR circuit consisting of the capacitor 114 and the variable resistor 116 in the phase shift circuit 110C shown in FIG. 3, and is composed of a variable resistor 116 and an inductor 117. It has a configuration replaced with an LR circuit.
  • the relationship between the input / output voltage and the like of the phase shift circuit 110 L shown in FIG. 25 is obtained by changing the voltage VC1 shown in FIG.
  • the voltage VR1 shown in FIG. 4 can be replaced by the voltage VR1 shown in FIG.
  • FIG. 27 is a circuit diagram showing another configuration of the phase shift circuit including the LR circuit, and shows a configuration that can be replaced with the phase shift circuit 130C at the subsequent stage of the tuning circuit 1 shown in FIG. .
  • the phase shifter 130L shown in the figure replaces the CR circuit consisting of the variable resistor 136 and the capacitor 134 in the phase shifter 130C shown in Fig. 5 with an LR circuit consisting of an inductor 137 and a variable resistor 136. Configuration.
  • the voltage VC2 shown in Fig. 6 is applied to the voltage VR2 across the variable resistor 136, and the voltage VR2 shown in Fig. 6 is applied to the voltage VL2 across the inductor 137. You can think of it as a replacement.
  • each of the phase shift circuit 110 L shown in FIG. 25 and the phase shift circuit 130 L shown in FIG. 27 is different from the phase shift circuit 110 C, 130 L shown in FIG. 3 or FIG.
  • the phase shift circuit 110 C of the preceding stage is replaced with the phase shift circuit 110 L shown in FIG.
  • the tuning frequency of the tuning circuit including the phase shift circuits 1 10L and 130L is, for example, proportional to the reciprocal R / L of the time constant of the LR circuit in each phase shift circuit 110L and 130L. Since the inductance L can be easily reduced by integration, etc., the tuning frequency can be increased by integrating the entire tuning circuit including the two phase shifters 110 L and 130 L. It will be easier.
  • phase shift circuits 110 C and 130 C shown in FIG. 2 are replaced with the phase shift circuit 110 L shown in FIG. 25 and the phase shift circuit 130 L shown in FIG. 27, respectively.
  • the gate voltage of the FETs forming resistors 1 16 and 136 is changed, the direction of change of each phase shift amount is opposite, so the EX-OR gate in phase difference detection circuit 3 shown in Fig. 13 It is necessary to reverse the direction of the control voltage change by replacing 33 with an EX-NOR (exclusive. NOR) gate or exchanging one of the two inputs of either of the voltage comparators 31 and 32 shown in Fig. 13. There is.
  • EX-NOR exclusive. NOR
  • phase shift circuits 110 C and 130 C in the tuning circuit 1 shown in FIG. 2 are replaced with phase shift circuits 110 L and 130 L, the operation in each phase shift circuit is performed. Either of the voltage dividing circuits connected to the output terminal of the amplifier 112 or 132 may be omitted. Alternatively, omitting both voltage dividers and adjusting the resistance ratio of resistors 118 and 120 and the resistance ratio of resistors 138 and 140 Thus, the loss generated in the feedback loop of the tuning circuit 1 may be compensated.
  • the voltage dividing circuit 160 in the subsequent stage of the subsequent phase shift circuit may be omitted, and the output of the subsequent phase shift circuit may be directly fed back to the previous stage.
  • the voltage division ratio may be set to 1 by making the resistance value of the resistor 162 in the voltage dividing circuit 160 extremely small.
  • FIG. 29 is a circuit diagram showing a second modification of the tuning circuit.
  • the tuning circuit 1A shown in the figure has two shifts in which a phase shift of a total of 360 ° is performed at a predetermined frequency by shifting a phase of an input AC signal by a predetermined amount.
  • Phase circuit 210 C, 230 C, feedback resistor 170 and input resistor 174 (input resistor 174 has n times the resistance of feedback resistor 170)
  • the output (feedback signal) of the subsequent phase shift circuit 230 C and the signal (input signal) input to the input terminal 190 are added at a predetermined ratio by passing through each of these.
  • an adder circuit for performing the operation is performed.
  • the resistance of the input AC signal is set by setting the resistances of the resistors 118 and 120 in the preceding phase shift circuit 110C to the same value.
  • the gain of the phase shift circuit 110 It is set to a large value.
  • the gain of the phase shift circuit 210C is set to a value greater than 1 by setting the resistance of the resistor 120 'to a large value.
  • the gain of the phase shift circuit 230 C is increased. It is set to a value greater than 1.
  • the output terminal of the phase shift circuit 230 C is connected to the feedback resistor 170, the output terminal 192, and the resistor 178.
  • the output of the subsequent phase shift circuit 230C is directly fed back, but the voltage divider circuit is provided further downstream of the subsequent phase shift circuit 230C. And the divided output may be fed back via the feedback resistor 170.
  • the phase shift circuit 210C becomes an inverting amplifier, so the gain at this time is -m times (m is the resistance ratio between the resistors 120 'and 118'), and the input is
  • the gain of the phase shift circuit 210C also changes, and the amplitude of the output signal fluctuates.
  • Such amplitude fluctuations can be suppressed by connecting a resistor 119 to the inverting input terminal of the operational amplifier 112 and matching the gains when the frequency of the input signal is low and high.
  • the resistance value of the resistance 1 18 ′ is r and the resistance value of the resistance 1 20 ′ is mr
  • the resistance value of the resistance 1 19 is set to mr / (m ⁇ 1). Accordingly, the gains of the phase shift circuit 210C when the frequency of the input signal is 0 and infinity can be matched.
  • the phase shift circuit 230C by connecting the resistor 139 having a predetermined resistance value to the inverting input terminal of the operational amplifier 132, the amplitude fluctuation of the output signal can be suppressed.
  • one end of the resistors 119 and 139 may be connected to a fixed potential other than the ground level.
  • FIG. 30 is a circuit diagram showing a configuration of a phase shift circuit including an LR circuit, and shows a configuration that can be replaced with the phase shift circuit 210C preceding the tuning circuit 1A shown in FIG. It has been.
  • the phase shift circuit 210L shown in the figure is a CR circuit consisting of the capacitor 114 and the variable resistor 116 in the preceding phase shift circuit 210C shown in FIG. It has a configuration in which it is replaced with an LR circuit consisting of 1 16 and inductor 1 17.
  • FIG. 31 is a circuit diagram showing another configuration of the phase shift circuit including the LR circuit, which can be replaced with the phase shift circuit 230 C at the subsequent stage of the tuning circuit 1 A shown in FIG.
  • the configuration is shown.
  • the phase shift circuit 230 L shown in FIG. It has a configuration in which the CR circuit consisting of the variable resistor 1336 and the capacitor 1334 in the path 230C is replaced by an LR circuit consisting of an inductor 1337 and a variable resistor 1336.
  • the phase shift circuit 210L shown in FIG. 30 is equivalent to the phase shift circuit 210C of the preceding stage shown in FIG. 29, and is provided in the stage preceding the tuning circuit 1A shown in FIG.
  • phase shift circuit 210C With the phase shift circuit 210L shown in FIG.
  • phase shift circuit 230 L shown in FIG. 31 is equivalent to the phase shift circuit 230 C of the subsequent stage shown in FIG. 29, and the tuning circuit 1 A shown in FIG. It is possible to replace the subsequent phase shift circuit 230C with the phase shift circuit 230L shown in FIG.
  • phase shift circuits 2 10 C and 230 C are replaced with phase shift circuits 210 L and 230 L, the entire tuning circuit is integrated to increase the tuning frequency. It becomes easy to frequency.
  • phase shift circuits 210 C and 230 C shown in FIG. 29 are respectively connected to the phase shift circuit 210 L shown in FIG. 30 and the phase shift circuit 230 L shown in FIG. 31.
  • the EX-OR gate 33 in the phase difference detection circuit 3 is replaced with an EX-NOR (exclusive NOR) gate, or one of the two voltage comparators 31 1 and 3 2 shown in Fig. 13 is used. It is necessary to reverse the direction of the change in the control voltage by, for example, changing the input.
  • the tuning circuit 1A shown in Fig. 29 can adjust the tuning frequency by connecting two phase shift circuits, 210C and 230C, and a resistor 11 9 or 13 9 to it.
  • the tuning circuit can be configured by removing the above-mentioned resistors 119 and 139.
  • a tuning circuit can be formed by removing only one of the resistors 11 9 or 13 9.
  • the loss of the loop gain of the feedback loop composed of the entire area passing circuit including the two phase shift circuits 110C and the feedback resistor 170 is caused by the phase shift circuit 1 1 Because it is caused by the input impedance such as 0 C, the phase shift circuit in the preceding stage such as 110 C Further, a follower circuit by a transistor may be inserted in the previous stage, and the signal to be fed back may be input to the preceding phase shift circuit (for example, 110 C or 110 L) through the follower circuit. .
  • FIG. 32 is a circuit diagram showing an example of a tuning circuit including a follower circuit therein.
  • the tuning circuit 1B shown in the figure differs from the tuning circuit 1 shown in FIG. 2 in that a follower circuit 150 using a transistor is inserted in the preceding stage of the phase shifting circuit 110C in the preceding stage.
  • the follower circuit 150 shown in FIG. 32 is constituted by a so-called source follower circuit, but may be constituted by an emitter follower circuit.
  • FIG. 32 by setting the voltage dividing ratio of the voltage dividing circuit 160 to 1, or omitting the voltage dividing circuit 160 itself, the amplification operation is not performed by the entire tuning circuit, and the voltage is simply increased. Only the tuning operation may be performed.
  • a hologram circuit 150 composed of transistors is connected in cascade to the preceding stage of the preceding phase shift circuit 11 ⁇ C, etc., compared with the tuning circuit 1 etc. in FIG.
  • the resistance value of the input resistance 174 can be increased.
  • the entire tuning circuit is integrated on a semiconductor substrate, if the resistance value of the feedback resistor 170 is reduced, the area occupied by the element must be increased. It is desirable that the value is large. Therefore, it is effective to connect a follower circuit 50 as shown in FIG.
  • the combined phase shift amount of the two phase shift circuits 110 C and 130 C is 360 °, but the phase shift circuit 1 1 A tuning circuit may be constructed by connecting a non-inverting circuit that does not shift the phase to 0 C and 130 C.
  • FIG. 33 is a circuit diagram showing a configuration of a tuning circuit 1C in which a non-inverting circuit 350 is connected in front of two phase shift circuits.
  • the tuning circuit 1C is composed of a phase shift circuit 310C having a configuration in which the resistors 121 and 123 are omitted from the phase shift circuit 110C shown in FIG.
  • the phase shift circuit 330C having a configuration in which the resistors 141 and 144 are omitted from the phase shift circuit 130C shown in FIG. 5 and a phase shift circuit 310C connected in front of the phase shift circuit 310C.
  • the phase shift circuit 3 10 C shown in Fig. 33, 3 0 C is the operational amplifier 1 1 2 or 1
  • the non-inverting circuit 350 has an operational amplifier 3502 in which an AC signal is input to the non-inverting input terminal and the inverting input terminal is grounded via a resistor 350, and an inverting input terminal of the operational amplifier 3502 and an output. It is composed of a resistor 356 connected to the terminal.
  • the operational amplifier 352 has a predetermined amplification determined by the resistance ratio of the two resistors 354, 356.
  • the gain of the phase shift circuit 310C is 1 because the resistances of the resistors 118 and 120 are the same.
  • the gain of the phase shift circuit 33 0 C is 1 because the resistances of the resistors 1 38 and 140 are the same. Therefore, in the above-mentioned tuning circuit 1C, the gain of the above-mentioned non-inverting circuit 350 is set to a value larger than 1 instead of gaining each phase shift circuit.
  • the non-inverting circuit 350 having such a configuration outputs the input signal without changing the phase, and by adjusting the gain, the signal amplitude is attenuated by the voltage dividing circuit 16 ° and is generated in the feedback loop. It is easy to make up for the loss.
  • the non-inverting circuit 350 also functions as a buffer connected to the preceding stage of the preceding phase shifting circuit 310C, similarly to the above-described transistor-based hollow circuit.
  • the non-inverting circuit 350 shown in FIG. 33 may be connected to the preceding stage of the tuning circuits 1 and 1 A shown in FIGS. 2 and 29, and the like.
  • FIG. 34 is a circuit diagram showing a sixth modification of the tuning circuit.
  • a phase shift circuit 310 C is connected in place of the phase shift circuit 330 C in the latter stage of FIG.
  • a phase inversion circuit 380 is connected in place of the inversion circuit 350.
  • the phase inverting circuit 380 includes an operational amplifier 382 in which an input AC signal is input to an inverting input terminal via a resistor 384 and a non-inverting input terminal is grounded. It is composed of a resistor 386 connected between the inverting input terminal and the output terminal.
  • a signal having an inverted phase is output from the output terminal of the operational amplifier 382.
  • the signal is input to the preceding phase shift circuit 310C.
  • the phase inversion circuit 380 has a predetermined amplification determined by the resistance ratio of the two resistors 384 and 386, and the resistance 380 is determined by the resistance value of the resistor 384. A gain greater than 1 can be obtained by increasing the resistance value of.
  • the phase shift circuit 310 C shifts clockwise from 180 ⁇ to 360 ° with reference to the input voltage E i.
  • the phase shift amount in each case is 270 °.
  • the gain of the phase inverting circuit 380 is set to a value larger than 1 instead of gaining each phase shift circuit. It is easy to compensate for the signal amplitude attenuation due to 60 and the loss generated in the feedback loop (
  • the tuning circuit 1 D shown in FIG. 34 shows an example in which the phase shift circuits 3 10 C are cascaded, but the phase shift circuit 3 D shown in FIG. 33 is cascaded. In this case, the tuning operation can be performed.
  • FIG. 35 is a circuit diagram showing a seventh modification of the tuning circuit. Tuning shown in the figure The path 1E is a cascade connection of the phase shift circuit 330C in place of the phase shift circuit 310C in FIG.
  • the phase shift circuit 330 C shifts from 0 ° to 180 ° clockwise with respect to the input voltage E i.
  • phase inverting circuit 380 connected in front of the two phase shift circuits 330 C, and the phase shifts as a whole to reduce the phase shift amount by 36
  • the signal at 0 ° is output from the subsequent phase shift circuit 330C.
  • the gain of the phase inversion circuit 3 The value is set to a value, which makes it easy to compensate for the attenuation of the signal amplitude due to the voltage dividing circuit 160 and the loss generated in the feedback loop.
  • the tuning circuits 1C, 1D, and IE shown in FIGS. 33 to 35 each have two phase shift circuits that include a CR circuit, but are configured to include an LR circuit. May be used.
  • the preceding phase shift circuit 310 C is replaced with the phase shift circuit 110 L shown in FIG.
  • the subsequent phase shift circuit 330C may be replaced with a phase shift circuit in which the voltage dividing circuit is omitted from the phase shift circuit 130L shown in FIG.
  • a voltage dividing circuit 160 May be omitted. Further, a voltage dividing circuit may be connected to at least one output terminal of the operational amplifier in the two phase shift circuits. For example, in the tuning circuit 1 C shown in FIG.
  • the configuration is the same as the configuration in which the non-inverting circuit 350 is connected further to the preceding stage of the phase shifting circuit 110 C of the preceding stage in the tuning circuit 1 shown in FIG. Become.
  • the tuning circuits 1C, 1D, IE, etc. shown in FIGS. 33 to 35 are composed of two phase shift circuits and a non-inverting circuit, or two phase shifting circuits and a phase inverting circuit.
  • a predetermined tuning operation is performed by setting the total phase shift to 360 ° at a predetermined frequency by a total of the three connected circuits. Therefore, focusing only on the amount of phase shift, there is a certain degree of freedom in the order in which the three circuits are connected, and the connection order can be determined as necessary.
  • All of the first to seventh modifications of the tuning circuit described above include an op-amp inside the phase shift circuit, but it is also possible to configure the phase shift circuit using transistors instead of the operational amplifier. is there.
  • the tuning circuit 1F shown in FIG. 36 has a phase shift of a total of 360 ° at a predetermined frequency by shifting the phase of the input AC signal by a predetermined amount.
  • a voltage divider circuit 16 composed of resistors 16 2 and 16 4 provided at the subsequent stage of 45 0, a feedback resistor 17 0 and an input resistor 17 4 (input resistor 1 ⁇ 4 is a feedback resistor 17 It is assumed that it has a resistance value that is n times as large as 0), through which the divided voltage output of the voltage divider circuit 160 (feedback signal) and the signal input to the input terminal 190 (input And an adder circuit for adding the signals at a predetermined ratio.
  • Both the capacitor 170 connected in series with the feedback resistor 170 and the capacitor 170 inserted between the input resistor 170 and the input terminal 190 are used to block DC current.
  • the impedance is extremely small at the operating frequency, that is, has a large capacitance.
  • FIG. 37 shows an extracted configuration of the phase shift circuit 410C in the preceding stage shown in FIG.
  • the phase shift circuit 410C at the front stage shown in the figure is composed of a FET 412 whose gate is connected to the input terminal 122, and a capacitor connected in series between the source and drain of this FET 412. E 4 1 4 and the variable resistor 4 16, the resistor 4 18 connected between the drain of the FET 4 12 and the positive power supply, and the source of the FET 4 1 2 and ground. And a resistor 420 connected therebetween. Note that at least one of the FET 412 and the FET 432 described later may be replaced with a bipolar transistor.
  • the resistance values of the two resistors 418 and 420 connected to the source and the drain of the FET 412 are set to be substantially equal, and when focusing on the AC component of the input voltage applied to the input terminal 122, the phase is The matched signal is output from the source of the FET 412, and the signal whose phase is inverted (the phase is shifted by 180 °) is output from the drain of the FET 412.
  • the resistor 426 in the phase shift circuit 410 shown in FIG. 36 is for applying an appropriate bias voltage to the FET 412.
  • the variable resistor 416 uses a channel formed between the source and drain of a junction type FET as a resistor, as shown in FIG. 37, for example, and varies the gate voltage to change the resistance value. Can be arbitrarily changed within a certain range.
  • phase shift circuit 410C having such a configuration, when a predetermined AC signal is input to the input terminal 122, that is, when a predetermined AC voltage (input voltage) is applied to the gate of the FET 412, the source of the FET 412 In this case, an AC voltage having the same phase as the input voltage appears, and an AC voltage having a phase opposite to that of the input voltage and having the same amplitude as the voltage appearing at the source appears at the drain of the FET 412.
  • the amplitude of the AC voltage appearing at the source and drain is Ei.
  • FIG. 38 is a vector diagram showing the relationship between the input / output voltage of the preceding phase shift circuit 410C and the voltage appearing in the capacity and the like.
  • the potential difference between the source and the drain (AC component) is 2Ei.
  • the voltage VC1 appearing across the capacitor 414 and the voltage VR1 appearing across the variable resistor 416 are 90 ° out of phase with each other. The vectorwise combination of these is equal to the source-drain voltage 2 Ei of the FET 412.
  • the double side of the voltage Ei is defined as the hypotenuse
  • the voltage VC1 across the capacitance 414 and the voltage VR1 across the variable resistor 416 form a right-angled triangle forming two sides orthogonal to each other. Become. For this reason, when the amplitude of the input signal is constant and only the frequency changes, the voltage VC1 across the capacitor 414 and the voltage VR1 across the variable resistor 416 are determined along the circumference of the semicircle shown in FIG. Changes.
  • this output voltage Eo starts from the center point in the semicircle shown in FIG. It can be represented by a vector ending at a point on the circumference where voltage VC1 and voltage VR1 intersect, and its magnitude is equal to the radius Ei of the semicircle. Moreover, even if the frequency of the input signal changes, the end point of this vector merely moves on the circumference, so that a stable output whose output amplitude does not change according to the frequency can be obtained.
  • the phase difference between the input voltage applied to the gate of the FET 412 and the voltage VR1 is theoretically As the frequency ⁇ changes from 0 to ⁇ , 270 clockwise with respect to the voltage Ei in phase with the input voltage. To 360 °. Then, the phase shift amount 05 of the entire phase shift circuit 410C changes from 180 ° to 360 ° according to the frequency. Moreover, by varying the resistance value of the variable resistor 416, the phase shift amount 05 can be changed.
  • FIG. 39 shows only the configuration of the subsequent phase shift circuit 430C shown in FIG. 36.
  • the subsequent phase shift circuit 430 C shown in the figure is a FET 432 whose gate is connected to the input terminal 142 and the source and drain of this FET 432.
  • the resistor 446 in the phase shift circuit 430 C shown in FIG. 36 is for applying an appropriate bias voltage to the FET 432.
  • the capacitor 148 provided on the input side of the phase shift circuit 430 C is for blocking DC current that removes the DC component from the output of the phase shift circuit 410 C, and only the AC component is input to the phase shift circuit 430 C. Is done.
  • the phase shift circuit 430 C having such a configuration, when a predetermined AC signal is input to the input terminal 142, that is, when a predetermined AC voltage (input voltage) is applied to the gate of the FET 432, At the source, an AC voltage having the same phase as this input voltage appears.
  • an AC voltage having a phase opposite to that of the input voltage and equal in amplitude to the voltage appearing at the source appears.
  • the amplitude of the AC voltage appearing at the source and drain is Ei.
  • FIG. 40 is a vector diagram showing a relationship between the input / output voltage of the subsequent phase shift circuit 430C and the voltage appearing in the capacity and the like.
  • the source and the drain of the FET 432 show an AC voltage having the same and opposite phases as the input voltage and the voltage amplitude of Ei, the potential difference between the source and the drain is 2 Ei. Also, the voltage VR2 appearing at both ends of the variable resistor 436 and the voltage VC2 appearing at both ends of the capacitor are 90 ° out of phase with each other, and the vectorwise addition of these results in a difference between the source and drain of the FET432. Is equal to 2 Ei. Therefore, as shown in Fig. 40, twice the voltage Ei is the hypotenuse, and the variable resistance 4
  • the voltage VR2 between both ends 36 and the voltage VC2 between both ends of the capacitor 434 form a right-angled triangle forming two orthogonal sides. For this reason, when the amplitude of the input signal is constant and only the frequency changes, the voltage VR2 across the variable resistor 436 and the voltage between the capacitor 1 34 along the circumference of the semicircle shown in FIG. The voltage between both ends VC2 changes.
  • this output voltage Eo is the center point of the semicircle shown in Fig. 40.
  • the end point of this vector only moves on the circumference, so that a stable output whose output amplitude does not change according to the frequency can be obtained.
  • the input voltage applied to the gate of the FET 432 and the voltage VC2 changes from 0 ° to 90 ° as the frequency ⁇ changes from 0 to ⁇ .
  • the phase shift amount 06 of the entire phase shift circuit 430C changes from 0 ° to 180 ° according to the frequency.
  • the shift amount ⁇ 6 is also the same as 02 shown in the above equation (7).
  • the phase is shifted by a predetermined amount in each of the two phase shift circuits 410C and 4300C, and is shifted to a predetermined frequency as shown in FIGS. 38 and 40.
  • a signal having a total phase shift amount of 360 ° is output by the entire two phase shift circuits 410C and 430C.
  • the non-inverting circuit 450 shown in FIG. 36 has a resistor between the drain and the positive power supply.
  • 4 5 4 is a FET 4 52 with a resistor 4 56 connected between the source and ground, and a base is connected to the drain of the FET 4 52 and the collector is a resistor. It is configured to include a transistor 458 connected to the source of the FET 452 via an anti-460 and a resistor 462 for applying an appropriate bias voltage to the FET 452. .
  • the capacitor 164 provided before the non-inverting circuit 450 shown in FIG. 36 is for blocking DC current that removes the DC component from the output of the subsequent phase shift circuit 430C. Yes, only the AC component is input to the non-inverting circuit 450.
  • F ET 452 When an AC signal is input to the gate, F ET 452 outputs a signal of the opposite phase from the drain. Also, when the opposite phase signal is input to the base of the transistor 458, the transistor 458 is further inverted in phase, that is, the in-phase signal is considered based on the phase of the signal input to the gate of the FET 452. Is output from the collector, and this in-phase signal is output from the non-inverting circuit 450.
  • the output of the non-inverting circuit 450 is taken out from the output terminal 192 as the output of the tuning circuit 1F, and the output of the non-inverting circuit 450 is passed through the voltage dividing circuit 160 to generate a signal.
  • the signal is fed back to the input side of the phase shift circuit 410 C in the preceding stage via the feedback resistor 170. Then, the feedback signal and the signal input via the input resistor 174 are added, and the voltage of the added signal is input to the input terminal of the preceding phase shift circuit 410C (FIG. 37). Is applied to the input terminals 1 2 2
  • the gain of the above-described non-inverting circuit 450 is determined by the resistance values of the above-described resistors 45 4, 45 6, and 46 0. Compensates for the attenuation caused by the two phase shift circuits 4 10 C, 4 3 0 C or the voltage divider circuit 160 shown in the figure, and the loss generated in the feedback loop, and reduces the gain of the entire tuning circuit to 1 or less. It is set as follows.
  • the gain is applied to the tuning circuit 1F itself.
  • the signal amplitude can be amplified simultaneously with the tuning operation.
  • the tuning circuit shown in Fig. 36 includes a CR circuit inside each of the phase shift circuits 410C and 330C, but the CR circuit has been replaced with an LR circuit consisting of a resistor and an inductor. It is also possible to configure a tuning circuit using a phase shift circuit.
  • FIG. 41 is a circuit diagram showing a configuration of a phase shift circuit including an LR circuit.
  • a configuration that can be replaced with the phase shift circuit 410C preceding the tuning circuit 1F shown is shown.
  • the phase shift circuit 410 L shown in the figure is a CR circuit comprising the capacity 414 and the variable resistor 416 in the preceding phase shift circuit 410 C shown in FIG. 36, and an LR comprising the variable resistor 416 and the inductor 417.
  • the circuit is replaced with a circuit, and the resistances of the resistor 418 and the resistor 420 are set to the same value.
  • the capacitor 419 inserted between the inductor 417 and the drain of the FET 412 is for blocking DC current.
  • the relationship between the input / output voltage and the like of the phase shift circuit 410 L described above is obtained by replacing the voltage VC1 shown in FIG. 38 with the voltage VR1 across the variable resistor 416,
  • the voltage VR1 shown in (1) can be replaced with the voltage VL1 across the inductor 417.
  • phase shift circuit 410 L shown in FIG. 41 is basically equivalent to the phase shift circuit 410 C shown in FIG. 37, and the phase shift circuit 410 C shown in FIG. It can be replaced by the phase shift circuit 410 L shown.
  • FIG. 43 is a circuit diagram showing another configuration of the phase shift circuit including the LR circuit, and shows a configuration that can be replaced with the phase shift circuit 430C after the tuning circuit 1F shown in FIG. 36. I have.
  • the resistance values of 438 and 440 are set to the same value.
  • a capacitor 439 inserted between the variable resistor 436 and the drain of the FET 432 is for blocking DC current.
  • the relationship between the input / output voltage and the like of the phase shift circuit 430 L described above is obtained by converting the voltage VR2 shown in FIG.
  • the voltage VC2 shown in FIG. 40 can be replaced with the voltage VR2 across the variable resistor 436.
  • T 2 L / R
  • L, (3) to K3 as it can be applied as shown formula (However, a 2 ° 1) the phase shift amount 08 shown in FIG. 44 also described above (7) It is the same as 02 shown in the formula.
  • phase shift circuit 430 L shown in FIG. 43 is basically equivalent to the phase shift circuit 430 C shown in FIG. 39, and the phase shift circuit 430 C shown in FIG. 39 is shown in FIG. 43.
  • Phase shift circuit 430 L Phase shift circuit 430 L.
  • phase shift circuits 410 C and 430 C shown in FIG. 36 With the phase shift circuits 410 L and 430 L shown in FIGS. 41 and 43. By integrating the entire tuning circuit, it is easy to increase the tuning frequency. Note that if the phase shift circuits 4 10 C and 430 C shown in FIG. 36 are replaced with the phase shift circuit 410 L shown in FIG. 41 and the phase shift circuit 430 L shown in FIG. 43, respectively, Since the direction of change of each phase shift amount when the gate voltage of the FET forming the variable resistors 4 16 and 436 is changed is opposite, the EX in the phase difference detection circuit 3 shown in Fig.
  • phase shift circuits 4 10 C and 430 C shown in FIG. 36 are replaced with phase shift circuits 410 L and 430 L, respectively, the voltage divider circuit 160 is omitted and the phase shift circuit in the subsequent stage is omitted. May be directly fed back to the preceding stage.
  • the resistor 162 in the voltage dividing circuit 160 may be removed and only the resistor 164 may be used. If the voltage dividing circuit 160 is omitted, or if the resistor 162 is removed, only the tuning operation can be performed.
  • FIG. 45 is a circuit diagram showing another modification of the tuning circuit.
  • the tuning circuit 1G shown in the figure is composed of two phase shift circuits 4 10 that perform a total of 180 ° phase shift at a predetermined frequency by shifting the phase of the input AC signal by a predetermined amount.
  • C the subsequent phase shift circuit 4 10 0
  • the phase inversion circuit 480 that further inverts the phase of the output signal of C, and the output from the phase inversion circuit 480 by passing through the feedback resistor 170 and the input resistor 1 ⁇ 4 And a signal (input signal) input to the input terminal 190 at a predetermined ratio.
  • each phase shift circuit 410C and the phase relationship between input and output are as described with reference to FIGS. 37 and 38.
  • the phase inverting circuit 480 has a predetermined resistance connected to the gate of the FET 482 and the FET 482 each having a resistor 484 connected between the drain and the positive power supply and a resistor 486 between the source and the ground. And a resistor 488 for applying a bias voltage.
  • a signal having a reversed phase is output from the drain of the FET 482.
  • the phase inversion circuit 480 has a predetermined gain determined by the resistance ratio of the two resistors 484 and 486. As described above, at a predetermined frequency, the phase is shifted by 180 ° by the two phase shift circuits 410C, and the phase is inverted by the phase inverting circuit 480 connected at the subsequent stage.
  • the total amount of phase shift is 360 °. Therefore, the output of the phase inversion circuit 480 is fed back to the input side of the previous phase shift circuit 4 10 C via the feedback resistor 170, and the signal input via the input resistor 1 ⁇ 4 is added to this feedback signal. At the same time, by adjusting the gain of the phase inversion circuit 480, the same tuning operation as that of the tuning circuit 1 shown in FIG. 2 is performed.
  • the output of the phase inversion circuit 480 was directly fed back via the feedback resistor 1 ⁇ 0, but like the tuning circuit 1F shown in FIG. 36, A voltage dividing circuit 160 may be connected to the subsequent stage of the phase inverting circuit 480 to return the divided voltage output.
  • FIG. 46 is a circuit diagram showing another modified example of the tuning circuit, which is configured to include the latter-stage phase shift circuit 4300 shown in FIG. 36 as opposed to FIG. 45. .
  • the tuning circuit 1H shown in FIG. 46 has a total of 180 at a predetermined frequency by shifting the phase of the AC signal to which it is input by a predetermined amount.
  • Two phase shift circuits 4300C that perform the phase shift of the following, a phase inversion circuit 480 that further inverts the phase of the output signal of the subsequent phase shift circuit 430C, and a feedback resistor 170 And a signal (feedback signal) output from the phase inversion circuit 480 and a signal (input signal) input to the input terminal 190 at a predetermined ratio by passing through each of the input resistors 174.
  • an adding circuit for adding is a signal for adding.
  • each phase shift circuit 430C and the phase relationship between input and output are as described with reference to FIGS. 39 and 40.
  • the phase is shifted by 180 ° by the two phase shift circuits 430 C, and the phase is inverted by the phase inverting circuit 480 connected at the subsequent stage.
  • the total phase shift amount is 360 °.
  • the output of the phase inversion circuit 480 is fed back to the input side of the preceding phase shift circuit 430 C via the feedback resistor 170, and the feedback signal is input via the input resistor 174.
  • a voltage dividing circuit 160 is connected downstream of the phase inverting circuit 480. Amplification may be performed simultaneously with tuning.
  • the various tuning circuits 1F, 1G, 1H, etc. described above are composed of two phase shift circuits and a non-inverting circuit or two phase shift circuits and a phase inverting circuit, and the three connected
  • a predetermined tuning operation is performed by setting the total phase shift amount to 360 ° at a predetermined frequency by the entire circuit. Therefore, focusing only on the amount of phase shift, the order in which the three circuits are connected is uncertain. There is a certain degree of freedom, and the connection order can be determined as necessary.
  • a CR circuit is included inside the phase shift circuit.
  • a phase shift circuit including an LR circuit is connected in cascade.
  • a tuning circuit instead of the two phase shift circuits 410C of the tuning circuit 1G shown in FIG. 45, a phase shift circuit 410L shown in FIG. 41 may be connected.
  • a phase shift circuit 430L shown in FIG. 43 may be connected in place of the two phase shift circuits 430C of the tuning circuit 1H shown in FIG.
  • phase shift circuit including the CR circuit when the phase shift circuit including the CR circuit is replaced with a phase shift circuit including the LR circuit, the amount of each phase shift when the gate voltage of the FET forming the variable resistors 416 and 436 is changed Since the direction of change is opposite, the EX-OR gate 33 in the phase difference detection circuit 3 shown in FIG. 13 is replaced with an EX-NOR (exclusive 'NOR) gate, or as shown in FIG. It is necessary to invert the direction of the control voltage change by exchanging one of the two inputs of the voltage comparator 31 or 32.c In the tuning circuits 1F, 1G, and 1H described above, although the phase shift circuit is configured using 12 or FET 432, the phase shift circuit may be configured using a bipolar transistor instead of FET.
  • FIG. 47 is a circuit diagram showing a twelfth modification of the tuning circuit.
  • the tuning circuit 1 J shown in the figure is composed of a non-inverting circuit 550 that outputs the input AC signal without changing the phase, and that shifts the phase of the input signal by a predetermined amount to obtain a total at a predetermined frequency.
  • Phase shift circuit that performs a 360 ° phase shift at 5 ° C. 5 C and 530 C, and a voltage divider 1 consisting of resistors 1 62 and 1 64 provided further downstream of the subsequent phase shift circuit 530 C 60 and the feedback resistor 170 and the input resistor 174 (the input resistor 174 has a resistance value n times as large as the feedback resistor 170).
  • the non-inverting circuit 550 is, for example, ⁇ It is composed of a circuit and a source follower circuit. When the element constants of each element such as the feedback resistor 170 are selected so as to minimize the loss and the like when directly connected, the non-inverting circuit 550 is omitted and the tuning circuit is configured. May be.
  • FIG. 48 shows a configuration extracted from the phase shift circuit 5100 at the preceding stage shown in FIG.
  • the phase shift circuit 510C at the preceding stage shown in the figure is a differential amplifier 511 that amplifies the differential voltage of two inputs with a predetermined amplification and outputs the amplified signal, and a signal input to the input terminal 122. Shifts the phase of the signal by a predetermined amount, and inputs the same to the non-inverting input terminal of the differential amplifier 512. It is configured to include resistors 518 and 520 which divide the voltage level to about 1/2 without any change and input to the inverting input terminal of the differential amplifier 5122.
  • variable resistor 516 uses a channel formed between the source and the drain of a junction type FE as a resistor, as shown in FIG. 48, for example, and the gate voltage is varied by changing the gate voltage.
  • the resistance value can be arbitrarily changed within a certain range.
  • the signal appearing at the connection point between the capacitor 5 14 and the variable resistor 5 16 is input to the non-inverting input terminal of the differential amplifier 5 12. Is done. Since an input signal is input to one end of the CR circuit composed of the capacitance circuit 5 14 and the variable resistor 5 16, the voltage of the signal obtained by shifting the phase of the input signal by a predetermined amount by this CR circuit is different. It is applied to the non-inverting input terminal of the operational amplifier 5 1 2.
  • the differential amplifier 512 outputs a signal obtained by amplifying the difference between the voltages applied to the two input terminals at a predetermined amplification degree in this manner.
  • FIG. 49 is a vector diagram showing the relationship between the input / output voltage of the phase shift circuit 510 C shown in FIG. 48 and the voltage appearing in the capacity and the like.
  • the voltage VR1 appearing at both ends of the variable resistor 516 and the voltage VC1 appearing at both ends of the capacitor 514 are 90 ° out of phase with each other.
  • the result is the input voltage E i. Therefore, when the amplitude of the input signal is constant and only the frequency changes, the variable resistance is set along the circumference of the semicircle shown in Fig. 49.
  • the voltage VR1 between both ends of 516 and the voltage VC1 between both ends of the capacitor 514 change.
  • the voltage applied to the non-inverting input terminal of the differential amplifier 5 12 (voltage VR1 across the variable resistor 5 16) is applied to the voltage applied to the inverting input terminal (voltage E i / 2 across the resistor 5 20). ) Is the difference voltage E o '.
  • This differential voltage E 0 ′ is represented by a vector whose center point is the start point and whose end point is a point on the circumference where voltage VR1 and voltage VC1 intersect in the semicircle shown in FIG. 49. And its size is equal to the radius of the semicircle E i / 2.
  • the output voltage Eo of the differential amplifier 512 is obtained by amplifying the difference voltage Eo 'with a predetermined amplification factor. Therefore, in the above-described phase shift circuit 5110C, the output voltage E0 is constant regardless of the frequency of the input signal, and operates as an all-pass circuit. Further, as is clear from FIG. 49, since the voltage VR1 and the voltage VC1 intersect at right angles on the circumference, the phase difference between the input voltage Ei and the voltage VR1 varies from the frequency ⁇ of 0 to ⁇ . Then, the angle changes from 270 ° to 360 ° in the clockwise direction (phase lag direction) based on the input voltage E i. Then, the phase shift amount 09 of the entire phase shift circuit 5110C changes from 180 ° to 360 ° according to the frequency.
  • FIG. 50 shows a configuration extracted from the phase shift circuit 530C at the subsequent stage shown in FIG. 47.
  • the phase shift circuit 530C at the subsequent stage shown in the figure is a differential amplifier 532 that amplifies the differential voltage of the two inputs at a predetermined amplification level and outputs the amplified signal, and a signal that is input to the input terminal 142.
  • the variable resistor 5336 and the capacitor 5334 input to the non-inverting input terminal of the differential amplifier 532 after shifting the phase of the signal by a predetermined amount, and the phase of the signal input to the input terminal 1422 And the resistors 538 and 540 which divide the voltage level to about 1/2 without changing the voltage and input to the inverting input terminal of the differential amplifier 532.
  • the voltage E i applied to the input terminal 14 2 is connected to the inverting input terminal of the differential amplifier 5 32 by a resistor.
  • a voltage divided to about 172 is applied by 538 and the resistor 540.
  • the signal appearing at the connection point between the variable resistor 5 36 and the capacitor 5 34 is input to the non-inverting input terminal of the differential amplifier 5 32. Is done. Since an input signal is input to one end of the CR circuit composed of the variable resistor 536 and the capacitor 5334, the phase of the input signal is determined by this CR circuit. The voltage of the signal that has been shifted is applied to the non-inverting input terminal of the differential amplifier 532. The differential amplifier 532 outputs a signal obtained by amplifying the difference between the voltages applied to the two input terminals at a predetermined amplification degree in this manner.
  • FIG. 51 is a vector diagram showing the relationship between the input / output voltage of the phase shift circuit 530 C and the voltage appearing in the capacity and the like.
  • the voltage VC2 appearing at both ends of the capacitor 534 and the voltage VR2 appearing at both ends of the variable resistor 536 are 90 degrees out of phase with each other.
  • the sum is the input voltage E i. Therefore, when the amplitude of the input signal is constant and only the frequency changes, the voltage VC2 across the capacitor 534 and the voltage across the variable resistor 536 along the circumference of the semicircle shown in Fig. 51 VR2 changes.
  • the voltage applied to the non-inverting input terminal of the differential amplifier 532 (the voltage VC2 across the capacitor 534) is applied to the voltage applied to the inverting input terminal (the voltage E i / 2 across the resistor 540).
  • the vector obtained by subtracting the vector is the differential voltage E o '.
  • the difference voltage E o ' is represented by a vector whose center point is the starting point and whose end point is a point on the circumference where voltage VC2 and voltage VR2 intersect in the semicircle shown in Fig. 51. And its size is equal to the radius of the semicircle E i / 2.
  • the output voltage Eo of the differential amplifier 532 is obtained by amplifying the difference voltage Eo 'with a predetermined amplification factor. Therefore, in the above-described phase shift circuit 530 C, the output voltage E 0 is constant regardless of the frequency of the input signal, and operates as an all-pass circuit.
  • the phase difference between the input voltage Ei and the voltage VC2 varies from a frequency ⁇ of 0 to ⁇ . The angle changes from 0 ° to 90 ° as required. Then, the phase shift amount 010 of the entire phase shift circuit 530C is 0 according to the frequency. To 180 °.
  • phase of each of the two phase shift circuits 510C and 530C is shifted by a predetermined amount, and as shown in FIGS. 49 and 51, at a predetermined frequency.
  • a signal having a total phase shift amount of 360 ° is output by the entire two phase shift circuits 510C and 530C.
  • the output of the subsequent phase shift circuit 530 C is taken out from the output terminal 192 as the output of the tuning circuit 1 J, and the output of the phase shift circuit 530 C is divided by the voltage divider circuit 16
  • the signal passed through 0 is fed back to the input side of the non-inverting circuit 550 via the feedback resistor 170.
  • the feedback signal and the signal input via the input resistor 174 are added, and the added signal is supplied to the preceding phase shift circuit 510 C via the non-inverting circuit 550. Has been entered.
  • the two phase shift circuits 510C, 530C It is set so that the attenuation caused by the voltage divider circuit 160 and the loss generated in the feedback loop are compensated, and the loop gain of the entire tuning circuit is 1 or less.
  • the non-inverting circuit 550 may have a gain of 1 or more and adjust this value.
  • the output of the phase shift circuit 530 C before being input to the voltage dividing circuit 160 is taken out from the output terminal 1992 of the tuning circuit 1 J, the gain is given to the tuning circuit 1 J itself. Therefore, the signal amplitude can be amplified simultaneously with the tuning operation.
  • the voltage divider circuit 160 may be omitted and the output of the phase shift circuit 530C may be directly fed back to the preceding stage. Good.
  • the voltage division ratio may be set to 1 by making the resistance value of the resistor 162 in the voltage dividing circuit 160 extremely small.
  • each of the phase shift circuits 510C and 530C was configured to include a CR circuit, but the CR circuit was replaced with an LR circuit consisting of a resistor and an inductor.
  • a tuning circuit can also be configured using a phase shift circuit.
  • FIG. 52 is a circuit diagram showing another configuration of the phase shift circuit including the LR circuit, and is a configuration that can be replaced with the phase shift circuit 510 C preceding the tuning circuit 1 J shown in FIG. 47. It is shown.
  • the phase shift circuit 5 10 L shown in the figure is a CR circuit consisting of the capacity 5 1 4 and the variable resistor 5 16 in the phase shift circuit 5 10 C shown in FIG. It has a configuration in which it is replaced with an LR circuit consisting of 6 and Inductor 5 17.
  • the capacitor 5 19 connected in series with the inductor 5 17 is for blocking DC current, and its impedance is set to be extremely small at the operating frequency, that is, it has a large capacitance. I have.
  • FIG. 53 is a vector diagram showing the relationship between the input / output voltage of the phase shift circuit 5101 L and the voltage appearing in the inductor and the like.
  • FIG. 54 is a circuit diagram showing another configuration of the phase shift circuit including the LR circuit, and shows a configuration that can be replaced with the phase shift circuit 530C at the subsequent stage of the tuning circuit 1J shown in FIG.
  • the phase shift circuit 53 0 L shown in the figure is a CR circuit consisting of the variable resistor 536 and the capacitor 534 in the phase shift circuit 530 C shown in FIG. 50, and an LR consisting of the inductor 53 7 and the variable resistor 536. It has a configuration replaced with a circuit.
  • the capacitor 539 connected in series with the inductor 537 is for blocking DC current, and its impedance is set to be extremely small at the operating frequency, that is, it has a large capacitance.
  • FIG. 55 is a vector diagram showing the relationship between the input / output voltage of the phase shift circuit 530 L and the voltage appearing in the inductor and the like.
  • the phase shift circuits 510 C and 530 C shown in FIG. 47 are replaced with the phase shift circuit 510 L shown in FIG. 52 and the phase shift circuit 530 L shown in FIG.
  • each of the phase shift circuit 510 L shown in FIG. 52 and the phase shift circuit 530 L shown in FIG. 54 is different from the phase shift circuit 510 L shown in FIG. 48 or FIG. 530 C in the tuning circuit 1 J shown in FIG. 47, and the phase shift circuit 510 C of the preceding stage is shifted to the phase shift circuit 510 L shown in FIG. Route 530 C fifth 4 are possible which it replaces it in the phase shift circuit 5 3 0 L shown in FIG. C 2 two phase shifting circuits 5 1 0 C, 5 3 0 C 0 phase shift circuit 5 1 both L
  • the tuning frequency can be easily increased by integrating the entire tuning circuit.
  • the tuning circuit 1 J shown in FIG. 47 includes two phase shifting circuits having different phase shift directions from each other, but a tuning circuit is formed by combining two phase shifting circuits having basically the same configuration. You can also.
  • FIG. 56 is a circuit diagram showing another configuration of the tuning circuit.
  • the tuning circuit 1K shown in the figure is composed of a phase inverting circuit 580 that inverts the phase of an input AC signal and outputs the inverted signal, and a phase shift circuit that shifts the phase of the input AC signal by a predetermined amount.
  • Two phase shift circuits 510 C that perform a total of 180 ° phase shift at a predetermined frequency, and resistors 16 2 and 16 that are provided further downstream of the subsequent phase shift circuit 510 C
  • the voltage divider circuit 160 consists of four components, the feedback resistor 170 and the input resistor 174 pass through the voltage divider circuit 160 (divided output (feedback signal) and input terminal 190).
  • c of the signal which is input (input signal) is configured to include an adder circuit for adding at a predetermined ratio to
  • the detailed configuration of the two phase shift circuits 5 10 C and the phase relationship between the input and output signals are as described with reference to FIGS. 48 and 49.
  • the two phase shift circuits 5 At a predetermined frequency, the two phase shift circuits 5 The total phase shift amount of the entire 100 C is 180 °.
  • an emitter ground circuit ⁇ source as this c realized by a circuit that combines a ground circuit or an operational amplifier resistor, at a predetermined frequency, phase by two phase shifting circuits 5 1 0 C is 1 8 0 ° shifted, it is further connected to the preceding stage
  • the phase is inverted by the phase inverting circuit 580, and the total phase shift amount of the three circuits as a whole is 360 °.
  • the output of the subsequent phase shift circuit 5100C is taken out from the output terminal 1992 as the output of the tuning circuit 1K, and the output of the subsequent phase shift circuit 5100C is divided by the voltage divider circuit 160 Through the feedback resistor 170 to the input side of the phase inverter 580 Have been.
  • the signal that is fed back and the signal that is input via the input resistor 174 are added, and the added signal is input to the phase inversion circuit 580.
  • the output of the voltage dividing circuit 160 is fed back to the input side of the phase inverting circuit 580 via the feedback resistor 170, and the signal input via the input resistor 174 is applied to this feedback signal.
  • the gain of the two phase shift circuits 5 10 C may be adjusted.
  • the voltage divider circuit 160 is omitted, and the output of the phase shift circuit 5100C is directly fed back to the previous stage. Is also good.
  • the voltage division ratio may be set to 1 by making the resistance value of the resistor 162 in the voltage dividing circuit 160 extremely small.
  • FIG. 57 is a circuit diagram showing another modification of the tuning circuit, which is configured to include a subsequent-stage phase shift circuit 530C shown in FIG. 47 contrary to FIG. .
  • the tuning circuit 1L shown in Fig. 57 has a total of 180 ° phase shift at a given frequency by shifting the phase of the input AC signal by a given amount.
  • each phase shift circuit 530 C and the phase relationship between the input and output are as described with reference to FIGS. 50 and 51.
  • the phase is shifted by 180 ° by the two phase shift circuits 530C at a predetermined frequency, and furthermore, The phase is inverted by the phase inverting circuit 580 connected in the preceding stage, and the total phase shift amount of the three circuits as a whole is 360 °.
  • the above-mentioned tuning circuit 1 L feeds back the output of the voltage dividing circuit 160 to the input side of the phase inverting circuit 580 via the feedback resistor 170, and adds the input resistor 1 74 to this feedback signal.
  • the signals input via the input terminals are added together, and the gain of the two phase shift circuits 530 C is adjusted to adjust the gain of the voltage divider circuit 160 and the connection between the feedback resistor 1 ⁇ 0 and the input resistor 174, etc.
  • the same tuning operation and amplification operation as those of the tuning circuit 1K shown in FIG. 56 can be performed.
  • the tuning circuits 1K and 1L shown in Fig. 56 and Fig. 57 are connected in cascade with a phase shift circuit that includes a CR circuit, but the LR circuit is internally connected for both phase shift circuits. May be included.
  • the two phase shift circuits 5100C may be replaced with the phase shift circuit 5101L shown in FIG.
  • the two phase shift circuits 530C may be replaced with the phase shift circuit 530L shown in FIG.
  • the various points when the gate voltage of the FE ⁇ that forms the variable resistor 116 or 136 are changed Since the direction of the phase shift change is opposite, the EX-OR gate 33 in the phase difference detection circuit 3 shown in FIG. 13 can be replaced with an EX-NOR (exclusively NOR) gate. It is necessary to reverse the direction of change of the control voltage by exchanging either of the two inputs of the voltage comparators 31 and 32 shown in FIG.
  • the tuning circuits 1 J, 1 K, and 1 L described above include a non-inverting circuit and two phase shifting circuits or a phase inverting circuit and two phase shifting circuits, and are connected to three connected circuits.
  • phase shift circuit including the CR circuit when replacing the phase shift circuit including the CR circuit with the phase shift circuit including the LR circuit, only one of the two cascade-connected phase shift circuits is connected to the LR It may be replaced with a phase shift circuit including a circuit.
  • the control direction of the resistance value of the variable resistor 116 in the preceding phase shift circuit is opposite to the control direction of the resistance value of the variable resistor 116 in the subsequent phase shift circuit. Therefore, it is necessary to slightly modify the circuit, such as inverting the output level of the distributor 5 shown in FIG.
  • phase shift circuit including the CR circuit and the phase shift circuit including the LR circuit are cascaded to form a tuning circuit, and when the entire tuning circuit is integrated, the tuning frequency due to temperature change is reduced. So-called temperature compensation that prevents fluctuations is possible.
  • the phase difference between the input and output signals of the subsequent phase shift circuit is detected, but the phase difference between the input and output signals of the preceding phase shift circuit may be detected.
  • the direction of change of the phase shift amount is opposite to that in the case where the phase difference between the input and output signals of the subsequent phase shift circuit is detected.
  • variable resistors 1 16 in the two phase shift circuits constituting the tuning circuit are formed by using the junction type FET.
  • the variable resistor may be formed of another element.
  • the tuning circuit 1M shown in Fig. 58 is a variable circuit in which the variable resistors 1 16 and 1 36 in the phase shift circuits 110 C and 130 C shown in Fig. 3 are formed by MOS type FETs. These are replaced by resistors 1 1 5 and 1 3 5 respectively.
  • a channel formed between the source and the drain of the MOS FET can be used as a resistor. In this case, since the channel resistance of the FET can be changed by changing the control voltage applied to the gate, the tuning frequency of the tuning circuit 1 can be arbitrarily changed within a certain range.
  • phase shift circuit 110C and the like are connected in series with the capacity 114 and the like.
  • the overall tuning frequency was changed by changing the phase shift amount by changing the resistance value of the variable resistor 116 etc., but the overall tuning was changed by changing the capacitance of the capacitor 114 etc. The frequency may be changed.
  • FIG. 59 is a diagram showing the configuration of a tuning circuit in which the overall tuning frequency is changed by changing the capacitance of the capacitance.
  • the tuning circuit 1N shown in the figure is configured based on the phase shift circuits 110C and 130C shown in FIG. 2, but the various phase shift circuits shown in FIG. 29 and FIG. 46 etc. You may comprise based on a circuit.
  • the capacitors 128 and 148 connected in series to the variable capacitance diodes 127 and 147 are for blocking DC current when applying a reverse bias voltage to the variable capacitance diodes, and the impedance thereof is extremely low at the operating frequency. It is small, that is, has a large capacitance.
  • the capacitance was varied using a variable capacitance diode as a variable capacitance element, but the gate capacitance could be changed within a certain range according to the control voltage applied to the gate Any FET may be used as the variable capacitance element.
  • FIG. 60 is a circuit diagram showing an example in which an element other than FET is used as a variable resistor in the phase shift circuits 110 C and 130 C shown in FIG.
  • the phase shift circuit 110C ⁇ shown in FIG. 60 includes a variable resistor 116 formed by using the FET in the phase shift circuit 110C shown in FIG. 2, and a CdS comprising a CdS photosensor and a light emitting diode. It has a configuration replaced with an S-photo power brush 177.
  • the CdS photosensor included in the photo-force bra 177 has such a characteristic that the resistance value decreases as the amount of light emitted from the light-emitting diode increases, so that such a CdS photo-bra 177 is externally controlled. It can be used as a variable resistor whose resistance value can be changed according to the current.
  • phase shift circuit 130 C ⁇ shown in FIG. 60 includes a variable resistor 136 formed using FET in the phase shift circuit 130 C shown in FIG. 2, and a CdS photosensor and a light emitting diode.
  • control voltage generating circuit 4 B shown in c FIG. 60 having a structure obtained by replacing the CdS photo force bra 179 made from, have a configuration in which a control voltage generation circuit 4 shown in FIG. 13 partially deformed Variable resistance to the control voltage generation circuit 4. The difference is that the bias circuit including the resistor 42 and the resistor 43 is removed.
  • the voltage-to-current conversion circuit 200 shown in FIG. 60 includes an operational amplifier 204 in which the control voltage output from the control voltage generation circuit 4B is input to the inverting input terminal via the resistor 202. And a variable resistor 206 used to generate a variable bias voltage.
  • the two light emitting diodes in the photocouplers 1777 and 1779 described above are connected in series between the output terminal and the inverting input terminal, and the non-inverting input terminal is grounded. . Therefore, when the output voltage (control voltage) of the control voltage generation circuit 4B is determined, a predetermined current determined by the resistance ratio between the resistor 202 and the variable resistor 206 is generated by the photovoltaic motors 17 7 and 17
  • the CdS photosensor that flows to each light emitting diode in the light emitting diode 9 and forms a pair with this light emitting diode has a certain resistance value corresponding to the light emission amount of the light emitting diode.
  • the tuning frequency of the tuning circuit shown in FIG. Conversely, by increasing the output voltage of the control voltage generation circuit 4B, the value of the current flowing through the light emitting diode increases, the amount of light emission increases, and the resistance value of the CdS photosensor decreases. Tuning frequency increases. This relationship is the same as the relationship between the variable resistor formed by FET and the control voltage described above, and the tuning frequency of the tuning circuit 1 can be made to match the frequency of the input signal by exactly the same control procedure.
  • the tuning circuit that realizes the tuning mechanism of the above-described embodiment can also be configured by using the photo power blurs 1777 and 179 as the variable resistors.
  • the photo power blurs 1777 and 179 are used as variable resistors, a constant resistance value is always obtained regardless of the voltage at both ends of the variable resistor, so that a tuning output with little distortion can be easily obtained.
  • the photocouplers 177 and 179 connect individual components to connection lines and the like. Will be used for connection.
  • a phase shift circuit 110 C using an operational amplifier Although high stability can be achieved by configuring the tuning circuit 1 with 130 C, offsetting is required when using the phase shift circuits 110 C and 130 C of the present embodiment. Since a high-performance voltage and voltage gain are not required, a differential amplifier having a predetermined amplification may be used instead of the operational amplifier in each phase shift circuit.
  • FIG. 61 is a circuit diagram in which a part necessary for the operation of the phase shift circuit is extracted from the configuration of the operational amplifier, and the whole operates as a differential amplifier having a predetermined amplification degree.
  • the differential amplifier shown in the figure includes a differential input stage 100 composed of FETs, a constant current circuit 102 for supplying a constant current to the differential input stage 100, and a constant current circuit 102.
  • a differential input stage 100 connected to a differential input stage 100, and a bias circuit 104 for applying a predetermined bias voltage to the differential input stage 100.
  • the multistage amplifier circuit for gaining the voltage gain included in the actual operational amplifier is omitted, so that the configuration of the differential amplifier can be simplified and a wider band can be achieved.
  • the upper limit of the operating frequency can be increased.
  • the upper limit of the tuning frequency of the tuning circuit 1 configured using this differential amplifier must be increased accordingly. Can be.
  • the present invention is not limited to the various embodiments described above, and various modifications can be made within the scope of the present invention.
  • the tuning circuit 1 whose detailed configuration is shown in Fig. 2 uses a feedback resistor 170 as a feedback impedance element and an input resistor 174 as an input impedance element. Since it is sufficient that the signals can be added without changing the phase relationship of the input signals, the feedback impedance element and the input impedance element are formed by a capacitor instead of a resistor, or the real number of impedance is formed by combining a resistor and a capacitor. The ratio of the minute and the imaginary number may be adjusted simultaneously. Further, at least one of the feedback resistor 170 and the input resistor 174 may be constituted by a variable resistor so that the tuning bandwidth in the tuning amplifier 1 or the like can be varied.
  • variable resistor 1 16 is composed of one FET, but the p-channel FET and the n-channel FET are connected in parallel.
  • One variable resistor may be configured.
  • the tuning control method of the present invention performs feedback control of the tuning frequency of the tuning circuit so that there is no deviation between the frequency of the input signal of the tuning circuit and the tuning frequency. Can be reliably matched. Therefore, when the entire tuning mechanism is integrated, the tuning characteristics do not vary even if the frequency characteristics vary among the manufactured chips. In addition, the tuning frequency does not change even if the element constant of each element that determines the tuning frequency fluctuates due to temperature or the like, so that it is suitable for integration.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Networks Using Active Elements (AREA)
  • Amplifiers (AREA)

Abstract

Un mécanisme d'accord comporte un circuit d'accord (1) constitué par la connexion en cascade de deux circuits déphaseurs et par un circuit (2) de commande de fréquence qui comprend un circuit (3) détecteur de déphasage et un circuit (4) générateur de tensions de commande. Le circuit (3) convertit les signaux d'entrée et de sortie de l'un ou l'autre des deux circuits déphaseurs en signaux à ondes rectangulaires, calcule le OU exclusif de ces derniers et le transmet au circuit (4). Le circuit (4) lisse et amplifie le signal de sortie du circuit (3) et ajoute une tension de polarisation prescrite au signal de sortie amplifié pour produire une tension de commande servant à déterminer la fréquence d'accord du circuit d'accord (1). La tension de commande est amenée à l'entrée des deux circuits de déphasage. Le circuit (1), maintenant l'égalité des constantes de temps des circuits déphaseurs, règle la base du déphasage sur le signal de commande et rend la fréquence d'accord égale à la fréquence du signal d'entrée du circuit d'accord (1).
PCT/JP1996/001097 1995-11-09 1996-04-23 Systeme de commande d'accord WO1997017759A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
AU53481/96A AU5348196A (en) 1995-11-09 1996-04-23 Tuning control system
JP51804597A JP3764483B2 (ja) 1995-11-09 1996-04-23 同調制御方式
KR1019980703018A KR100350400B1 (ko) 1995-11-09 1996-04-23 동조제어방식
HK99100745A HK1015979A1 (en) 1995-11-09 1999-02-24 Tuning control system

Applications Claiming Priority (12)

Application Number Priority Date Filing Date Title
JP31612195 1995-11-09
JP31739495 1995-11-09
JP7/316122 1995-11-09
JP7/317394 1995-11-09
JP7/316121 1995-11-09
JP31612295 1995-11-09
JP34665895 1995-12-13
JP7/346658 1995-12-13
JP8/38881 1996-02-01
JP3888196 1996-02-01
JP3887896 1996-02-01
JP8/38878 1996-02-01

Publications (1)

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WO1997017759A1 true WO1997017759A1 (fr) 1997-05-15

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PCT/JP1996/001097 WO1997017759A1 (fr) 1995-11-09 1996-04-23 Systeme de commande d'accord

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JP (1) JP3764483B2 (fr)
KR (1) KR100350400B1 (fr)
CN (1) CN1113462C (fr)
AU (1) AU5348196A (fr)
HK (1) HK1015979A1 (fr)
WO (1) WO1997017759A1 (fr)

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JP2011066733A (ja) * 2009-09-18 2011-03-31 Mitsumi Electric Co Ltd スーパーヘテロダイン方式の受信装置及び受信方法、並びに受信装置用半導体集積回路
EP3126916A1 (fr) * 2014-03-31 2017-02-08 Telefonaktiebolaget LM Ericsson (publ) Boucle de compensation d'alimentation en mode commuté
CN106680594B (zh) * 2016-12-14 2019-01-01 浙江大学 一种用于lc振荡器特征参数的非接触式测量方法
CN106972487B (zh) * 2017-04-26 2020-06-02 广东电网有限责任公司电力科学研究院 一种电抗器及其实现方法

Citations (5)

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Publication number Priority date Publication date Assignee Title
JPS5660116A (en) * 1979-10-22 1981-05-23 Tech Res & Dev Inst Of Japan Def Agency Synchronous oscillation afc system
JPS6290016A (ja) * 1986-06-25 1987-04-24 Nippon Columbia Co Ltd 周波数特性補正回路
JPH03178205A (ja) * 1989-12-07 1991-08-02 Matsushita Electric Ind Co Ltd 移相型ｃｒ発振装置
JPH0575387A (ja) * 1991-09-17 1993-03-26 Sanyo Electric Co Ltd 可変遅延回路
JPH05183406A (ja) * 1991-12-27 1993-07-23 Nec Eng Ltd 自動位相補正回路

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5660116A (en) * 1979-10-22 1981-05-23 Tech Res & Dev Inst Of Japan Def Agency Synchronous oscillation afc system
JPS6290016A (ja) * 1986-06-25 1987-04-24 Nippon Columbia Co Ltd 周波数特性補正回路
JPH03178205A (ja) * 1989-12-07 1991-08-02 Matsushita Electric Ind Co Ltd 移相型ｃｒ発振装置
JPH0575387A (ja) * 1991-09-17 1993-03-26 Sanyo Electric Co Ltd 可変遅延回路
JPH05183406A (ja) * 1991-12-27 1993-07-23 Nec Eng Ltd 自動位相補正回路

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CN1113462C (zh) 2003-07-02
KR100350400B1 (ko) 2002-12-18
HK1015979A1 (en) 1999-10-22
JP3764483B2 (ja) 2006-04-05
AU5348196A (en) 1997-05-29
KR19990067078A (ko) 1999-08-16
CN1201567A (zh) 1998-12-09

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