Classifications

• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
  • G01S3/00—Direction-finders for determining the direction from which infrasonic, sonic, ultrasonic, or electromagnetic waves, or particle emission, not having a directional significance, are being received
  • G01S3/80—Direction-finders for determining the direction from which infrasonic, sonic, ultrasonic, or electromagnetic waves, or particle emission, not having a directional significance, are being received using ultrasonic, sonic or infrasonic waves
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R21/00—Arrangements for measuring electric power or power factor
  • G01R21/133—Arrangements for measuring electric power or power factor by using digital technique
  • G01R21/1331—Measuring real or reactive component, measuring apparent energy
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R21/00—Arrangements for measuring electric power or power factor
  • G01R21/133—Arrangements for measuring electric power or power factor by using digital technique

Definitions

• the present invention converts the voltage and current of the analog input ft to digital values and processes them! : Subordinate watt-hour meter.
• Figure 34 shows the block diagram HI of a circuit that calculates the power of a conventional electronic watt-hour meter.
• 71 is a first successive approximation type AZD converter that receives an analog current signal
• 72 is a second successive approximation type AZD converter that receives an analog voltage signal
• 73 is This is a multiplier that receives digital data corresponding to the voltage value and the current value from the successive approximation AD converters 71 and 72 as inputs.
• a conventional electronic watt-hour meter uses a first and second successive approximation type as a means for converting analog amounts of voltage and current into de, ':.'
• a / D converters 7 1 and 2 are provided, and their digital outputs are calculated by a multiplier 73 to obtain an electric energy w).
• successive approximation type AZD converters 71 and 72 have digital values that increase the output discretely with equal resolution for analog input signals! : Due to the coca, it is necessary successive approximation ⁇ Bruno D converter of a high resolution to obtain an absolute precision for low-level input:
• the quantization noise becomes wider.
• the spectrum is dispersed in the band and the level of each frequency component spectrum decreases.
• the signal frequency 6 O H'z
• the noise level of the signal frequency component is about 2 1
• a successive approximation type AZD converter having a resolution of 11.1, 12 bits is required in this case.
• the present invention has been made to solve the above problems, and has as its object to obtain a highly accurate electronic dynamometer with a simple circuit configuration. Disclosure of the invention
• the invention according to claim 1 of the present application is directed to a first and second analog ⁇ digital conversion means for quantizing an alternating current and an alternating voltage, respectively, and the above-mentioned quantum (converted alternating current and alternating current).
• the first and second moving average m means for moving the pressure respectively, the first multiplying means for multiplying the moving average processed current and AC voltage, and the outputs from the multiplying means are integrated.
• an integrating means for performing
• the invention according to claim 2 of the present application is the invention according to claim 1 in which a ratio of 1, 11 (n ⁇ 1) is obtained from a sampling value sequence of the quantized AC current and AC voltage after moving average. And a thinning-out means.
• the invention according to claim 1 or 2 includes an analog ⁇ digital conversion means for integrating an analog input value with an integrator, outputting a digital value through a comparator, and outputting the digital value.
• Sigma that delays DZA conversion and feeds the input to the integrator.
• switching means for switching a plurality of inputs at a predetermined cycle and sequentially inputting to the sigma-delta modulation circuit; and the integrator sequentially in synchronization with the switching cycle of the switching means.
• Holding means for holding an integrated value to be integrated corresponding to each of the plurality of inputs.
• the invention according to claim 4 of this application is the invention according to any one of claims 1 to 3, wherein the output of the first and second moving average processing means is an output of 8 bits or less.
• the invention according to claim 5 of the present application is characterized in that the first analog-to-digital conversion means for quantizing an alternating current, the second analog-to-digital conversion means for quantizing an AC voltage, First and second digital ⁇ -bus filters for low-passing AC current and AC voltage, respectively, from the sampled values of quantized AC current and AC voltage after low-pass A thinning-out means for thinning out at a rate of 1 no'm (m is the first ⁇ second person's digital mouth one pass per ⁇ / number of lettering delay means), AC current and AC voltage from this thinning means
• the first to ride The multiplication means and the means for multiplying the output from the multiplication means were panicked.
• the invention according to claim 7 of this application is based on claims 1, 2, and 5. : One cycle of the current and AC pressure is detected by zero-cross of the AC voltage, and the AC current and AC voltage quantized based on the output of the zero-cross detection means are integrated for one cycle each. First and second integrating means, second multiplying means for multiplying the outputs from the respective integrating means, and subtracting means for subtracting the output of the second multiplying means from the output of the first multiplying means And with.
• the invention according to claim 8 of this application is based on the fact that the input multi-element AC current and AC! : Switching means for sequentially extracting the AC current and AC voltage of each corresponding element from the pressure at a predetermined cycle, the first analog-to-digital conversion means for sequentially quantizing the AC current and AC voltage of each element from this switching means And second analog / digital conversion means, first and second digital one-pass filters, which sequentially pass the quantized AC current and AC voltage of each of the K-elements at a low frequency, and a low frequency From the sequence of sampling values of the AC current and AC voltage of each quantized element after passing, 1, m ( ⁇ .
• the invention according to claim 9 of the second application is the invention according to claim 5 or 8.
• the first and second digital one-pass filters are connected to each other by 8 bits. A powerful filter.
• the invention related to claim 11 of this application is based on the invention of claim 8, and is provided with a method for subtracting a force value of. Things.
• the invention according to claim 12 of the present application is directed to any one of claims 1, 2, and 511 according to any one of the first to second inventions, wherein a desired analog-to-digital conversion means and a second digital low-pass filter are provided. is provided with a delay hand stage delay time is obtained u
• the invention according to claim 13 of this application is the invention according to any one of claims 1, 2, and 5 to 12 ', wherein the first analog-to-digital conversion means and the first digital port-to-bus bus are provided.
• a delay means for obtaining a desired delay time between filters is provided.
• the invention according to claim 14 of this application is the invention according to claim 12 or 13, wherein the delay means is a shift register capable of shifting a desired number of shifts. is there.
• the invention according to claim 15 of the present application is the invention according to any one of claims 1, 2, and 5 to 14, in which a multi-element input to which an AC current and an AC voltage of an ⁇ element are input is provided.
• any one of claims ⁇ 1, 2,--1 ⁇ is reset every time the integrated value of the quantized power value exceeds a preset rating reference value. : ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇
• a light-load adjuster (even if 3 ⁇ 4 is used) that applies a predetermined light-load adjustment value to the quantized power value at least when the load is light.
• the invention according to claim 19 of the present application is the invention according to any one of claims 1, 2, 5, and 8 ⁇ , wherein the power value that operates at a predetermined operation frequency ⁇
• the third digital signal / L ⁇ —basic / one that passes the low-pass through the third digital port, and the output value that has passed through the third digital one-pass filter is recorded.
• a second register which operates at a frequency of ⁇ , a frequency of ⁇ ′) ⁇ times a frequency, adds and stores the value of the first register 11 times, and stores the second Comparing means for comparing the register value with a preset rated reference value at an operating clock frequency n times the frequency of f, and sending out an output that measures the amount of power each time the rated reference value is exceeded It is.
• the invention according to claim 20 of this application is human-powered by the invention of claim 1.2, 5-1Q.
• a rating adjustment means that outputs the power as a corrected power based on the rated reference value.
• the invention according to claim 21 of the present application is a switching means for sequentially switching and outputting each of the first phase, the second phase, and the third phase input current and input voltage at a predetermined cycle.
• Phase alternating current and alternating current! The first and second analog-to-digital converters ⁇ that quantize the pressure respectively, the first and second analog-to-digital converters that pass the quantized AC current and AC voltage of each phase in the low band, respectively.
• Second digital robes i / letters after passing the low pass ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇
• the analog and analog input values are input as the second current and voltage input, and the output of the third digital single-port pass at this time is set as w, and the current and voltage input of the first phase are to enter the analog value, at this time of the ⁇ third de; the output of the 'digital Ropasufu filter and w 0 3,
• B3-w / w.
• Balance adjustment means for setting the value of 3 in the second balance adjustment register.
• reference power reference voltage ⁇ calculation precision multiplied by reference current, rating reference value-calculation value (constant) that determines the number of pulses per power amount
• a light load adjustment register is provided to add the set light load adjustment value to the output value of the third digital port and one pass filter.
• Light load adjuster to be set in the register ⁇ 3 ⁇ 4.
• This register specifies the number of shifts in the evening, ⁇ 1, ⁇ 2. ⁇ 3.
• ⁇ 3 ⁇ ( ⁇ , X 0.5) — w.
• the value f is set in the shift register in [1] above,
• Phase adjusting means for adjusting the phase by shifting the phase of each phase to the values of P 1, ⁇ 2, P 3 in sequence by the register and the register in synchronization with the switching means.
• at least one of the adjusting means of the above 0) 234 is provided.
• the first and second analog / de- The values of the AC current and the AC voltage are measured as it I, and the quantized signal is subjected to the moving average processing by the first and second moving average processing means K.
• the ft number corresponding to the power by multiplying the Accumulate the high-precision power S,
• the operation of thinning at a rate of 1 il thinning means (ii 1) is performed by the following method. Perform and reduce the number of performances!
• a plurality of inputs are sequentially input to the digital circuit by the switching means ⁇ in a predetermined cycle m, and the signals are sequentially input to the digital data conversion circuit by:
• the analog input e is integrated by an integrator, the digital value is output through a comparator, and the output is delayed and D / A converted, and a feedback signal is input to the input side of the integrator. Click.
• the integrated values sequentially divided by the integrator in synchronization with the switching cycle of the switching means are respectively held in correspondence with the plurality of inputs.
• the integration by the integrator and the integration by the holding means for each input of the number of rafts are successively performed at the predetermined cycle, and are output.
• Delta modulation circuit supports multiple inputs.
• the first and second moving average processing means can measure the electric energy with a predetermined accuracy ⁇ with an output of 8 bits or less.
• the first analog-to-digital conversion means quantizes the alternating current
• the second analog-to-digital conversion means quantizes the AC voltage
• the first and second digital-to-digital conversion means Digital mouth per pass filter
• the above quantized exchange! The current and the AC voltage are each passed through the low-pass, and 1'in (m is the first and second Decimation at a rate of 1 ⁇ -the number of pass-field delay means or more). Multiplying the AC current and the AC voltage from the vehicle by the first multiplying means, and integrating the output from the multiplying means by the integrating means to obtain a high-precision force
• the quantized alternating current and alternating current are integrated for one cycle by the first and second subdividing means.
• the output is converted by the p-multiplier. Squared TL.
• the second from the output of the first vehicle The output of the multiplication means is subtracted by the subtraction means to reduce the power calculation error due to the shadow of the DC component.
• the AC current and the AC voltage of each corresponding element are sequentially extracted from the element AC current and the AC voltage inputted by the switching means at a predetermined period, and each element from the switching means is taken out.
• the AC current and the fluid pressure are sequentially quantized by the first analog-to-digital conversion means and the second analog-to-digital conversion means, so that the first and second digital ports—pass filters To sequentially pass through the low frequency band, and thin out to 1 in (where in is the number of delay means of the first and second digital low-pass filters) by the thinning means, which corresponds to multi-element input from the thinning means.
• the AC current and the AC voltage are multiplied, respectively, and the sum of the multiplication results is obtained by the calculating means.
• the output of the sum is integrated by the integrating means to obtain the electric energy.
• the first and second digital filters perform a power measurement within a predetermined accuracy with an output of 8 bits or less.
• a power of about 7 sets is calculated from the quantum-corrected offset current and the offset voltage obtained by inputting the reference current and the reference pressure. ': Set the offset adjustment means as ⁇ , and reduce the quantized power value or offset power value to make offset adjustment.
• the reference current and the reference pressure are inputted in a predetermined cycle, and the quantum (offset offset: current and size) calculated from the pressure is used to calculate the offset power. Then, the result of this operation is set to the offset adjustment method by the offset value at the predetermined cycle, and set to iT. ⁇ Offset force value reduced from child force value ⁇ Off 7
• the phase difference is corrected by adjusting the current phase angle by the delay hand ⁇ .
• the phase angle is adjusted by the shift register capable of shifting the desired number of shifts and the phase angle error is corrected, according to the invention of claim 15.
• the first, second, third,... , ⁇ The reference current and reference voltage are applied to the input of each element, and the quantized power value
• the output passing through the third i-th digital robus filter is prevented from escaping, and the input power is not increased.) The measurement error is further reduced.
• a predetermined light load adjustment value is added to the quantized power value at least when the load is light, and the measurement error at the light load is reduced.
• Claim ⁇ Q Operate at a predetermined motion ⁇ knock' knock frequency ' -1 "
• the second nig digital's power is passed through the-- 7 /1 unit and the force ⁇ . Is passed through and stored in the first register.
• the operating clock frequency is ⁇ C and operates at 11 times the frequency of U1 disk.
• the reference current and the reference pressure, and the actual reference values, and the reference current and the reference voltage! Correct the rated reference set previously set according to the power value and the g> ratio of the calculation obtained by multiplying by, and use this corrected rated reference value as the fixed adjuster rating ⁇ standard value.
• the set value is output as a corrected power amount input at the rated reference value, and the output is processed to calculate an accurate power amount.
• the first and second analog currents and input voltages are sequentially switched and output at a predetermined cycle by the conventional means, and the first and second analogs are output.
• the first and second digital low-pass filters are low-passed, and the quantized AC current and AC voltage of each phase after the low-pass L. 1 / "m from the value sequence, multiply each phase AC and AC voltage from the thinning means, and calculate the sum of the multiplication results, and output the sum. Is passed through the third digital / 1 ⁇ -sigma, and is integrated by the integrating means.
• the first phase is the flow and pressure input, and the upper pi value is output. '-... 2 ⁇ :
• the output of the third digital low-pass filter is w. ; I
• B 2 w. ,, 'vv. Set 185 of 2 as the first balance adjustment register.
• B 3 vv., W ⁇ is changed to the second balance: balance adjustment level '-';;: 15 is adjusted by balance adjustment means.
• a light load adjustment register is provided that adds the set light load adjustment value to the output value of the third digital ⁇ -pass filter.
• the value of 1 / ⁇ (11 ⁇ 1) of the current analog value input in step (1) above was input as the current input for the first phase, and was also input in step (1) above! :
• the pressure analysis value 1, "'m (m ⁇ 1) is input as the current input of the second phase, and the output of the third digital port, one pass, ", And the value of L. (V, non-in) -v: is used as the light-load adjustment value, and is adjusted by the light-load adjustment means set in the light-load adjustment register.
• the effective value is the same as the input -Input the manalogs of 0 and 5 (E is input, and the second data of ⁇ is input to it; the output of the .pi.
• P 3 K (w. I :,.: 0.5)
• One w 0 or: 3 is set in the register of P 1 above,
• phase of each phase is shifted to the values of the primary FM, P2, and P3 by the above-mentioned registers, and the phase is adjusted by the phase adjusting means.
• FIG. 1 shows a power calculation unit of a sub watt-hour meter according to Embodiment 1 of the present invention.
• [214 is a graph showing an example of the cloth: 1.1 / 1
• Hi 5 is the D-filter that constitutes the D-filter.
• FIG. 18 is a block diagram of a power calculation of the electronic watt-hour meter according to the third embodiment of the present invention.
• FIG. 9 is a block diagram of a power calculation unit of an electronic watt-hour meter according to Embodiment 4 of the present invention.
• FIG. 10 is a block diagram of a power calculation unit of the electronic watt-hour meter according to Embodiment 5 of the present invention.
• FIG. 11 is a block diagram of the first-order sigma ⁇ de-geometric modulation circuit ⁇ ⁇ ⁇ used in the fifth embodiment, G of the present invention.
• FIG. 12 is a block diagram of a power 'calculation unit of an electronic watt-hour meter according to Embodiment 6 of the present invention.
• FIG. 13 is a block diagram of a power operation unit of an electronic power meter according to Embodiment 7 of the present invention.
• FIG. 14 is a block diagram of a power calculation unit of an electronic watt-hour meter according to Embodiment 8 of the present invention.
• FIG. 15 is an explanatory diagram of the operation of FIG.
• FIG. 16 is an explanatory diagram of the operation of FIG.
• FIG. 17 is a block diagram of a power calculation unit of an electronic watt-hour meter according to Embodiment 9 of the present invention.
• FIG. 18 is an operation explanatory diagram of FIGS. 17 and 19.
• FIG. 20 is an explanatory diagram of the operation of the embodiment 11 of the present invention.
• FIG. 21 is a block diagram of the electric power calculation unit of the electronic watt-hour meter according to the embodiment 12 of the present invention.
• ! 122 is a block diagram of a power operation unit of the electronic watt-hour meter according to Embodiment 13 of the present invention.
• FIG. 24 shows the results of Example 15 of the present invention. : The total force is c
• Embodiment 1G of the present invention! Child type dynamometer ⁇ ⁇ This is a block diagram of the power performance section.
• .XI 27 is, HI 2 5, 2 (a valiant ⁇ Description u
• E28 is a blanking opening-click view of a child-type dynamometer force calculation unit that by the implementation ⁇ 1 8 of the present invention u
• ⁇ 29 is a diagram showing the output characteristics of the C-th.
• FIG. 30 is a block diagram of a power calculation unit of an electronic dynamometer according to Embodiment 19 of the present invention.
• FIG. 31 shows an electronic power! According to Embodiment 20 of the present invention! : Block diagram of the power calculator of the meter.
• FIG. 32 is a block diagram of a power calculation unit of an electronic watt-hour meter according to embodiment 21 of the present invention.
• FIG. 33 is a flowchart showing the adjustment operation of FIG. Figure 34 shows the block ⁇ ':' of the power calculator of the conventional electronic watt-hour meter.
• 10 is the first sigma that uses the analog current signal i as the manual power.
• Data / L data tuning, 11 is the second sigma that receives the analog pressure signal V as input.
• 1 2 is '-... F) 1 (:. »Tap moving average data / 1 filter, and the output of the first sigma' delta modulation circuit 10] is '', ⁇ (Referred to below as 16 tabs) and the moving average is calculated-).
• the 4 is a second 16-tap moving average digital filter connected to the first moving average digital filter # 12, and 13 is a second gamma digital filter.
• the 3rd 16-ta that performs the moving average of the output of the data modulation circuit 1 1 with the 'ma' 'Sop moving average digital filter, 15 is the 3rd 16-ta' A fourth 16-tap moving average digital filter connected to the 'moving average digital' filter 13.
• the first and second 16-tap moving average disc filters 12 and 14 constitute first moving average processing means, and the third and fourth 16-tap moving average processing means are constituted.
• the moving average digital filters 13 and 15 constitute the second moving average processing means.
• Reference numeral 16 denotes a first one-cycle moving average digital filter, which is connected in parallel with the first 16-tap moving average digital filter 12.
• Reference numeral 17 denotes a two-period moving average digital filter connected in parallel with the third 16-minute moving average digital filter 13.
• the first and second one-cycle moving average digital filters 1 and 17 constitute the first and second rice growing means.
• 18 is the first multiplication, and outputs the outputs of the second and fourth 16 taps' moving average digital / ref> ⁇ -ta] -1 and 15; !, 1 means that only one of the eight data items is thinned out and input.
• IQ is the second multiplier, the first and second one-period moving average data; 1 (:, 1 output, 1 output, 1 output S 1 1 6 1, — (One brain, one brain.) 20 is a subtractor, which calculates the difference between the output of the first multiplier 18 and the output of the second multiplier ⁇ 1! : The force data w is calculated 30: The counter that calculates the force data w.
• Figure 2 shows the first-and% 2 'ma delta reconciliations at 0 1
• the input X (z) is taken into the adder 31 in the unit of the sampling frequency ( ⁇ s>).
• the output of the adder? '1 is: Connected, and outputs the output of the integral 32 as 1-bit logic ( ⁇ ) by the comparator 33.
• This output data is output via the delay means 35. 1) '.'! L), the heating 31 is inverted by the ⁇ converter 34, and one step is performed.
• the above configuration is what is called a primary sigma delta modulation circuit.
• X (z) appears as it is in the output Y (z), and is information obtained by adding the noise Q ( ⁇ ) as output data.
• the above is an example of the first-order sigma-delta modulator.
• the 1211 second and first sigma-delta modulation circuits 10 and 11 are represented by the second-order sigma-data shown in FIG. ⁇ Adjust by adjusting ⁇ .
• the adders 41 and 6 and the integrators 42 and 7 are each composed of two, and the other components are shown in FIG. This is similar to that of the first-order sima-delta modulation circuit.
• H3 shows 2; missing human data ⁇ ⁇ ⁇ circuit is expressed by equation (4).
• Y (z) X (z H (1-Z-Q. (z,. ⁇ -(4;
• Q ⁇ 2 is the quantum (noise generated by arsenic)
• Equation (4) is also primary .. '1 ⁇ ⁇ II type ⁇ circuit (z) appears directly in the output Y (z), and as the output data, the information to which the noise Q (z) has been added is-.
• the difference between the G) and () equations is due to the noise (: Q (z)), which is the second digit in each equation.
• Fig. 4 shows the distribution vector of the quantization noise generated by the tuning operation of the second-order sigma 'delta' tuning ⁇ .
• ⁇ 4 the quantization noise in the ⁇ frequency region is small and the quantization noise in the high frequency region is large.
• the same is true for the first-order sigma-delta modulation circuit shown in Fig. 2 above: The distribution of the quantization noise is shown, but the second-order sigma-delta modulation circuit shown in Fig. 3 has the feature that the quantization noise in the lower frequency range is smaller.
• the sampling frequency ⁇ 's-122.88 ⁇ 2 the first and second sigma ⁇
• the delta modulator circuits 10 and 11 are represented by the second-order sigma delta shown in FIG. The operation will be described assuming that a modulation circuit is used.
• the outputs of the first and second sigma-delta modulation circuits 10 and 11 are obtained by adding the quantized noise to the input signal, and are sampled.
• the link rate is 122.88 ⁇ Hz, 1-bit serial logic data.
• the first and third 16-tap moving average digital filters 12 and 13 shown in Fig. 1 function as low-pass filters that attenuate quantization noise in the high-frequency range.
• the digital filter includes delay means 51, 52, 53, multipliers 54, 55, 56, 57 and adders 58, 59, 60. Is elliptical.
• ⁇ ( ⁇ ) (1 ⁇ 2 ⁇ -—-3 ⁇ -, .. ⁇ Ma + 2 ⁇ - 2 ⁇ + ⁇ - 3 ")
• the coefficient a indicates (1, 2, 3,-,..., 3, 2, 1), and the digital filter shown in FIG. It can be seen that ⁇ is equivalent to a moving plane digital filter.
• the second and fourth 1G tap moving average data shown in Fig. 1 are the same as those of 1a, 1filter, 13 and 15a.
• FIG. 6 shows the distribution spectrum of the output quantization noise after passing through 14 and 15.
• the 8-bit data of the jitter filter '15' and the 'note width' output data are 1/8 thinners ⁇ 3 ⁇ 4 ⁇ 4 1, 15 1
• the power is performed by the first multiplier 18. Therefore, when examining the accuracy of the power, the input to the first multiplication 3 ⁇ 4 18
• the voltage data V and current data I are given by Eqs. (5) and (6).
• I I,- ⁇ I:; (I s is the input ft, I H is the quantized sound for each frequency) (6)
• the first and second sigma-delta modulator circuits 10 and 11 are connected to the first and second sigma-delta modulation circuits 10 and 11 in order to remove the DC component generated by the offset of K 10 and 11.
• the second one-cycle moving average digital filters 16 and 17 perform a one-cycle (A ⁇ ) moving average, that is, the average value for one cycle is obtained.
• the DC component VDCIDC of voltage and current is extracted more.
• the output data of the first and second one-cycle moving average digital filters 16 and 17 are divided into eight output data by 18 decimation means 16 1 and 17 1, respectively. In other words, the interrogation operation for outputting one output data is performed, and the second multiplication ⁇ ⁇
• FIG. 7 shows another embodiment of the present invention.
• reference numerals 22 and 24 denote first and second up-counts, which are connected to the output side of the first and second sigma-delta modulation circuits 10 and 11 respectively.
• the first and second up-down counters 22 and 24 are connected to the 1-bit logic output of the first and second kuma delta ⁇ I times ⁇ 1 0 and 1 1. Then logic
• the gap count value is the DC of the current and voltage signals. in the present embodiment becomes that you have to extract the components, even if the frequency of the input voltage signal fluctuates, those having the advantage of operating effectively, zero-cross detector 2 6 and 1, kappa 2 frequency divider 27, one-period signal of the input voltage signal is generated, and for each one-period signal, the outputs of the first and second up-down counters 22 and 24 are sent to the latch registers 23 and 25.
• the other refinement is the same as that of the first embodiment of the figure. Even if the frequency of the input voltage signal fluctuates, the power calculation operation in which the power difference due to the DC components of the current and the voltage is reduced is possible.
• FIG. 8 shows still another embodiment.
• This embodiment differs from the HI embodiment in that the first and second one-period moving average digital filters 16, ⁇ 7 and 1, S thinning means 14 1, 15 1, 16 1 , 17 1, the second multiplier 1 °, and the subtractor 20 are omitted, and the first multiplier 18 a obtains the data of the power w shown in the above equation (7). This is multiplied by Cow: 0 to obtain the electric energy WH.
• FIG. 11 shows the internal configuration of the sigma-delta modulation circuit 10 used in this embodiment.
• the sigma-delta modulation circuit 10 is the first-order sigma-data modulation shown in Fig. 2 described above. This is a modification of the circuit, and is configured to be selectively connected to the integrator 32 by the capacitors ci, c, i.-. SW1 and SW4.
• the delta modulation circuit 10 receives the current signal i and the voltage signal V alternately by the switch SW1.
• the switches SW 3 and SW 4 are connected to the capacitor C i side so that the value is held in the capacitor C, and the switch SW 2 is connected to the second side.
• When taking in the voltage signal V as an input connect the switches SW 3 and SW 4 to the capacitor C 2 side to hold the value in the capacitor C 2 , and connect the switch SW 2 to the third and third Connect to the fourth 16-tap moving average digital filters 13 and I5.
• the switches SW 1, SW 2, SW 3, and SW 4 are switched synchronously according to ⁇ 3.
• the use of one sigma-delta modulation circuit 10 in a time-sharing manner has the effect of simplifying the circuit configuration.
• the means for holding the integrated value is not limited to a capacitor, but may be any means for holding the integrated value.
• a register with A, 'D conversion, L) / A conversion may be used.
• Fig. 12 shows an embodiment in the case of a two-element watt hour meter that measures the electric energy of a single-phase three-wire or three-phase three-wire.
• first and second sigma-delta modulation circuits 10 a and 10 b are primary sigma-delta modulation circuits each having the same configuration as that shown in FIG. one sigma-delta ⁇ circuit 1 ⁇ a., the sweep rate Tsu Ri by the switch SW 1 a, Ri taken at time division 1 line side of the current signal i t and 3-wire side current signal i 2 alternating And the values are alternately stored in capacitors c 1 and c 2 shown in FIG.
• switch SW 2a When taking in the current signal, the switch SW 2a is connected to the first and second 16-tap moving average digital filters 12a and 1 side, and the current ft signal i When importing the:: switch SW2a is the fifth .6th 16th tap moving average digital filter 12 and is connected to the 14b side. Second Shima ⁇ Data Moving Average Data
• Multiplier that calculates the force by multiplying the pressure data V, and, 18 1 is based on the flow signal 1 and the pressure signal V: ⁇ ;
• the flow data 'I 2 is multiplied by the voltage data V:
• a multiplication unit ⁇ ⁇ , 50 for calculating the power W 2 is an adder for adding the outputs of the multiplications 1 S a 1, 18 b 1 to obtain a power value w.
• the first sigma-delta modulator 10a takes in the current data i
• the second sigma-delta modulator 10b generates the voltage data Y
• the voltage data V: is taken.
• the power of the single-phase three-wire system or the three-phase three-wire system is obtained by adding the outputs ⁇ 1 and W, of the multipliers 18a1 and 181, by the adder 50.
• Data w is obtained, and this is integrated by the counter 30 to obtain the power amount WH.
• FIG. 13 shows another embodiment. This embodiment has only one stage of moving average filters connected to the first and second sigma-delta modulation circuits 10 and 11 respectively.
• the first and second 256-tap with the number of moving average taps of 256 are composed of the moving average digital figure 1 2 1 and 1 3 1 .
• the outputs of the first and second 25 (:> tap moving average digital filters 12 1 and 13 1) are 8-bit outputs.
• the first and second moving The output of the average digital filter 1 2 1, 1 3 1 is reduced by 1 3 2 decimation means 1 4 1 a, 1 5 1 a in the case of 1 ⁇ per 32, and multiplied. It is led to 18a, and the signal corresponding to the electric power, and this is integrated by Cunk? 0 to obtain the power WH.
• the moving average data is a combination of eta and digital data.
• the D-conversion has a smaller bit width than the conventional bit-type successive approximation ⁇ / D conversion. Multiplication is possible, and a high-precision ⁇ : force performance can be achieved with a multiplier having a small circuit scale.
• the analog section is only a sigma-delta modulation circuit, and the other circuits are data loops, and the analog circuit is a small ⁇ ; jitter) circuit. Therefore, it becomes an oval suitable for monolithic ICs, and can be expected to have a very large effect when large production is performed.
• a multiplier in the digital filter is not required, and a simple pass filter can be realized.
• This embodiment provides an electronic watt-hour meter slightly different from the configuration of the first embodiment.
• FIG. 14 shows this embodiment, and shows the case of a two-element power amount for measuring the power amount of a single-phase three-wire or three-phase three-wire.
• FIG. 15 is an explanatory diagram of the operation
• FIG. 16 is an explanatory diagram of the operation in which the time axis of HI 5 is enlarged.
• the first and second sigma-delta modulation circuits are shown in FIG. Is the sigma shown in Fig. 3 ⁇ Delta modulation circuit.
• the first digital / original pass filter 80 and the second digital / original pass filter are digital digital / original pass filters shown in FIG. 5, and include n delay means.
• Yes to have , question the pull-tab stage 1 8 1 1 8 2 cormorant line 1 Roh m decimation u it should be noted that the value of m is squid equal to n, is a great value Ri by it.
• the switch SW 5 takes in i, and the ⁇ , switch ':' ?? W 6 captures V i.
• the switch SW7 is connected to the register i, and the switch SWS is connected to the register V;
• a first digital; a ⁇ -sphere,) i through a -th sigma T / 1 modulator circuit 10 outputs a series of sample values of the alternating current. scan 1 Tsu the pull tab stage 1 S 1 - -.
• y 5 VSWG is selected ⁇ , the m ffi B J Bed n
• the value sequence is loaded into i;
• the second sigma ' ⁇ ⁇ ⁇ ⁇ 1 ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ in 2, off, i ,,, ⁇ blood SW 6 and SW 8 has been selected, in th: to the operation to fetch the flop 'Roh ⁇ value column in V t register.
• the eighth i is decimated and stored as i, then i, in register 191, and V, for input V,
• the eighth V, 7 in the sample value sequence of V is thinned out and stored as ⁇ ′ ⁇ , t in V; register 201.
• i, a , inn, i, c, ' ⁇ , v.v, t ., ⁇ ,,' are sequentially taken in.
• the quantized data (i, a 2, i 2, ⁇ 0, ⁇ ,, ⁇ 2 )
• the first and second digital mouth-pass filters 10 and 11 are 11
• This embodiment provides an electronic watt-hour meter provided with an offset adjusting means capable of adjusting the offset. See Figure 18.
• First and second sigma ⁇ Delta modulation circuit 10 0, 1 1,? ? -And the second digital ⁇ -pass filters 80, 81, and the interrogators f3 ⁇ 418], 182 have the same configuration as in the eighth embodiment, and a new i offset disk 19 3, V offset register 203, subtractors 21a, 2I ⁇ :, 111, 21d are provided.
• the GND signal which is the reference potential
• the register 193 and the V offset are respectively obtained.
• Data is stored in the memory register 203 and stored.
• i,, i2 are alternately captured on the current side
• v,, V :: are alternately captured on the voltage side.
• the offset power is corrected by subtracting the offset power from the power before the offset adjustment.
• FIG. 19 shows a modification of the ninth embodiment.
• This embodiment is a modification of the ninth embodiment and the tenth embodiment.
• the switch SW9 is connected to GND, i,, i2 and the second- order repetition, and is switched.
• SW 10 takes in GND, V,, V: sequentially and repeatedly.
• the switches SW11 and SW12 are sequentially switched, including the i offset register 193 and the Y offset register 203.
• FIG. 20 is an explanatory diagram of the operation, in which the offset current, the offset current, and the offset voltage are sequentially measured at that time, and are used for adjustment.
• the effect of this embodiment is that since the i offset and the V offset are always taken in, the DC offset of the analog circuit is hardly affected by fluctuations due to temperature, aging, etc. A watt-hour meter can be realized.
• This embodiment has a delay means that can adjust the voltage phase angle! : Provides a sub watt-hour meter.
• Figure 21 shows a block diagram. This configuration is the same as that of Embodiment 8 except that the second sigma ⁇ delta modulation circuit 11 and the second digital port A P-stage shift register 211 is provided between one pass filter, and a P 1 register 211 and a P 2 register 211 which determine the number of P-stage shifts are provided. It is provided. Then, the thinning means 18 1 and the thinning means 18 2 perform thinning of 1. (m-P). Note that the value of in is equal to or greater than 11 (n is the number of digital openings per pass' in Fig. 5).
• the effect of this embodiment is that the AC signal is generally detected by CT, and the AC voltage signal is generally detected by V
• the ⁇ -stage shift register 2 1 1 and the ⁇ 1 register 2 1 2 And ⁇ 2 register 2 13 makes it possible to eliminate the phase angle error of C ⁇ and V ⁇ , and to obtain a highly accurate electronic watt-hour meter with a small circuit scale .
• This embodiment provides an electronic watt-hour meter provided with a delay means capable of adjusting the current phase angle, and a block diagram is shown in FIG. 22. , ⁇ -stage shift register 211 and ⁇ 1 register 215 and ⁇ 2 register:! 1 C 'is provided on the current side.
• the AC signals i and i can delay the religion by the number of shift register stages of the P-stage shift register.
• Example 14 an electronic watt-hour meter provided with a balance adjusting means capable of performing a balance adjustment for multi-element measurement such as single-phase three-wire, three-phase three-wire, three-phase four-wire, etc.
• FIG. 23 shows a block diagram in the case of a three-element watt-hour meter that measures the power of a three-phase four-wire system.
• Embodiment 15- This embodiment provides an electronic watt-hour meter provided with balance adjusting means capable of performing balance adjustment as in Embodiment 14; The figure is shown.
• Embodiment 16- This embodiment provides an electronic watt-hour meter provided with anti-dive means for preventing start-up when there is no input, and FIG. 25 measures the electric energy of a single-phase two-wire system.
• a block diagram for a one-element watt hour meter is shown.
• Figure 27a shows the operation waveform.
• the first and second sigma-delta modulation circuits 10 and 11 are the same as the sigma-delta modulation circuit shown in FIG. 2 or FIG. 3, and the first and second digital low-pass circuits
• the filters 80 and 81 are the same as the digital port-and-pass filters shown in FIG.
• the AC current signal i and the current / voltage signal V are A / D converted by the sigma-delta modulation circuits 10 and 11 and the first and second digital-port single-pass filters 80 and 81. .
• the A / D-converted current data and voltage data are multiplied by a multiplier 50 to calculate instantaneous power data.
• the output values w,., Of the registers are compared with the rated reference value set in the rated reference value setting device 2 3 4 and
• One pulse is output from the magnitude comparator 23 3 (Fig. 27 a2), and the value (w ⁇ ⁇ -rated reference value) is set to the register 23 2.
• One-side magnitude comparator 23 3 Fig. 27 a2
• the pulse output from 2 3 3 is compared with the starting reference value (S) of the starting reference value setting device 2 3 6 in the pulse period detecting circuit 2 3 5
• the output of the AND gate 237 has a pulse output of ⁇ and ° for a pulse period smaller than the starting reference value, and no pulse is output for a pulse period of ⁇ and ⁇ for longer than the starting reference value.
• 2 7 a4) u This pulse is cumulatively added at cow: 30 to obtain the electric energy. That is, if the amount of power per hour is small, the power is not counted.
• the effect of this embodiment is that the starting current is detected by outputting a pulse from the accumulator 231, the register 23, and the magnitude comparator 23, and detecting the pulse period. By doing so, it has a dive prevention function to prevent unnecessary weighing due to the DC component of the analog section when there is no flow.
• Embodiment 7 This embodiment provides an electronic watt-hour meter provided with anti-dive means for preventing starting when there is no input, as in Embodiment 1'G. phase
• the process diagram for the one-element watt-hour meter that measures the electric energy of two wires is shown below.
• Figure 27b shows the operation waveforms.
• This embodiment provides an electronic watt-hour meter provided with light-load adjusting means for adjusting at light load.
• FIG. 28 shows a block diagram.
• the configuration is the same as that shown in FIG. 25 of the first embodiment except that a horizontal load adjustment setting device (register) 24 1 and an adder 50 for adding the vertical load adjustment value are provided.
• the light load adjustment value L in the light load adjustment setting unit 24 1 is added to the quantized power value output from the multiplier 18 j to perform light load adjustment.
• the reason for performing this light load adjustment is that when using the CT that is the AC current detection element, as shown in Fig. 29, there is a tendency for negative errors to occur in a small current region.
• the CT error is corrected by adding the constant value L in step (1).
• This light load adjustment value is added as a constant value not only in the light load but also in other regions other than the light load, but since this value is small, the ratio as an error in other regions can be ignored. Become so .
• the effect of this invention is to correct the CT error at light load, Can get a meter
• the light load adjustment value is applied to the region other than the light load condition, but in this embodiment, the light load adjustment value is applied only at the light load condition.
• FIG. 30 shows this embodiment.
• SW 1 7 is a sweep rate pitch which is opened and closed by the comparator 2 4 2 u
• the current value from the first digital port-to-pass filter 80 indicates that when this current value is light load and is equal to or less than the reference current value, the comparator 2 4 2 Does not operate, switch SW17 is connected to the light load adjustment setting unit, and the light load adjustment value is added.
• comparator 2 42 is activated.
• switch SW 17 is not connected to the light load adjustment setting device, and the light load adjustment value is not added.
• the operation after the addition of the light load adjustment value is the same as that of the embodiment 16.
• the effect of this embodiment is the same as that of the embodiment 18, but the light load adjustment value is added only at the time of the light load. Therefore, a more accurate electronic watt-hour meter can be provided.
• This embodiment provides an electronic watt-hour meter that can measure measurement accuracy in a very small current range in a short time.
• a third digital port-pass filter 82 Between the adder 18 j and the adder 50, a third digital port-pass filter 82, the adder 50 and the accumulator.
• the first register 251 which stores the value of w u + L, is provided between each 31 and the register on the output side of the accumulator 2 31 is the second register 25 2.
• the addition of the third digital port-to-pass filter 82 and the vertical load is the operating clock (CLK) frequency ⁇ synchronization.
• the register is stored in the-21st register 21.
• the accumulator 2? .1 I "'.
• the operation frequency is ⁇ "' (r and K).
• the register (i.g.) register The value (w,- : L) written in i 51 is added u times. , D> memorized in the 25 2. Thereafter, the magnitude code:.). ', And the recorder 23 3 3 perform the same operation as in the embodiment 18 and obtain the cumulative addition L and the electric energy by the counter 3 C)). ing .
• the effect of this embodiment is that the output interval time from the magnitude comparator to the power source is shortened, and the measurement accuracy can be measured in a short time especially in a small watershed.
• 26 1 is a display for displaying the integrated electric energy
• 260 is an arithmetic control circuit that controls the overall arithmetic control
• 270 is the entire electronic watt-hour meter
• 301 is the reference. It is an analog reference generator that inputs an input.
• L is light load! ! (Light load set value to set E L 3 ⁇ 4 In meter 24,
• F is the rated reference value setting 2 34 to set the rated reference value F.
• the operation is performed in the control mode.
• the following operation is performed with the adjustment mode:.
• ⁇ Ding Input the same number ⁇ to, VT2:, ⁇ ⁇ ;, Ding 1. ⁇ 3, V ⁇ 1, V ⁇ ? 0 Operate the entire circuit in that state.
• the reference power is a calculated value multiplied by the voltage and current from the analog reference generator 301
• the rated reference value is a calculated value that determines the number of pulses per power S (Constant).
• F is the revised rating reference value and is set as the new rating reference value. That is, the input electric energy (the value of the register 2 32) becomes the electric energy (the output of the magnitude comparator) corrected based on F, and the accurate electric energy (the value of the counter 3 (3 ) Is weighed ⁇ ,
• ⁇ 3 ⁇ ⁇ (w. No 2 — vv. P 3 ) w. , / 2 are set in the P3 register 2 17. ( ⁇ is a constant)
• FIG. 33 shows the ⁇ -tip of this adjustment operation, and the points (1) to (4) in the figure correspond to the adjustments (1) to (4) described above.
• the alignment work can be performed automatically with such a function.
• the constant ⁇ determined by ( ⁇ ) is. Assuming that I is a constant determined by the ring frequency r-quotient frequency ⁇ , the phase angle error is 1 minute, and the power is about 0.05%.
• the first and second moving average processing means can perform a power measurement within a predetermined accuracy with an output of 8 bits or less.
• the output of the analog-to-digital conversion means is subjected to a moving average of one cycle, so that there is an effect that the power calculation error due to the influence of the DC component can be reduced.
• the zero-crossing detecting means detects the zero-crossing of the AC voltage, and based on this, the quantized AC current and the current pressure for one cycle are detected. As a result, the effect of the DC component of the current and the voltage can always be removed even if the frequency and the motion are changed.
• each of the first and ⁇ nik) ⁇ -pass finos has an effect of being able to perform within a predetermined ⁇ degree ⁇ : power ⁇ with an output of S bits or less. .
• the offset power value can be corrected and the measurement accuracy can be improved by providing the adjusting means.
• the calculation of the offset ⁇ force is determined by a predetermined value.
• the offset value is always corrected, so that the measurement accuracy can be further improved.
• the phase angle error is corrected by adjusting the current phase angle by the delay means, so that the measurement accuracy can be improved.
• the phase angle is adjusted by the shift register capable of shifting a desired number of shifts so as to correct the phase angle IS difference. Therefore, there is an effect that the measurement accuracy can be improved.
• the balance is adjusted by providing balance adjusting means. Therefore, there is an effect that the measurement accuracy can be improved.
• the anti-dive means is provided to reduce the measurement error when there is no input electric energy, the measurement accuracy can be improved. effective.
• a light load adjusting means is provided so that a predetermined light load adjustment value is added at least when the load is light.
• the operation clock frequency is measured at the n frequency
• the electric energy is measured at X frequency, so that the measurement of i-5Ti, degree ⁇ can be performed in a short time. This makes it possible to measure the measurement accuracy particularly in a small watershed in a short time.
• a rating adjusting means is provided to output a power value corrected by the rating reference value: ''. is there .
• each adjustment value is set and stored as a digital numerical value, automatic setting without manual setting is possible, and it is possible to produce with an automation line, and the inexpensive sub power i Total effect 1 ⁇ ') o

Landscapes

• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• General Physics & Mathematics (AREA)
• Power Engineering (AREA)
• Radar, Positioning & Navigation (AREA)
• Remote Sensing (AREA)
• Measurement Of Current Or Voltage (AREA)
• Analogue/Digital Conversion (AREA)

Priority Applications (3)

Applications Claiming Priority (4)

Publications (1)

Family

ID=26333468

Family Applications (1)

Country Status (6)

Cited By (1)

Families Citing this family (71)

Citations (5)

Family Cites Families (22)

• 1993
  • 1993-12-15 JP JP05314689A patent/JP3080207B2/ja not_active Expired - Fee Related
  • 1993-12-24 TW TW082110957A patent/TW289088B/zh active
• 1994
  • 1994-01-06 US US08/295,872 patent/US5764523A/en not_active Expired - Lifetime
  • 1994-01-06 WO PCT/JP1994/000008 patent/WO1994016334A1/ja not_active Application Discontinuation
  • 1994-01-06 EP EP94904001A patent/EP0634662A4/en not_active Withdrawn
  • 1994-09-06 KR KR1019940703119A patent/KR950700548A/ko not_active Ceased

Patent Citations (5)

Non-Patent Citations (1)

Also Published As

Similar Documents

Legal Events