Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
  • H01L21/3105—After-treatment
  • H01L21/31051—Planarisation of the insulating layers
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
  • H01L21/3105—After-treatment
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
  • H01L21/76819—Smoothing of the dielectric
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
  • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
  • H01L23/5329—Insulating materials
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

• the present invention relates to a method for manufacturing a semiconductor device, and more particularly to a semiconductor device having a multilayer wiring structure in which a conductor layer is formed in a plurality of layers via an insulating layer.
• the present invention relates to a method for manufacturing a semiconductor device in which a method for flattening the surface of an interlayer insulating film between layers is improved.
• a multilayer structure is adopted for a wiring layer of the semiconductor device. That is, an electrode layer connected to each circuit element portion is formed on a semiconductor substrate on which a number of various circuit elements are formed, and an insulating film is formed on the electrode layer. Then, a first wiring layer is formed on the insulating film. In addition, a structure is adopted in which an interlayer insulating film is formed on the first wiring layer and a second wiring layer is formed on the insulating film. . In the case of such a multilayer wiring structure, it is very important to flatten the surface of the interlayer insulating film on which each wiring layer is formed in order to increase the reliability of each wiring layer. O
• an interlayer insulating film still has irregularities due to the wiring pattern present thereunder.
• a gate oxide film 12 is interposed on the surface of the semiconductor substrate 11.
• the semiconductor substrate 11 including the gate electrode film 13 is formed.
• An insulating film 14 is formed on the surface of the substrate.
• a high melting point silicide film 15 constituting the first wiring is formed on the insulating film 14 to form a first layered film 16.
• an interlayer insulating film 17 is further formed as a second laminated film, and a second wiring is formed on the interlayer insulating film 17.
• an aluminum film 18 is formed, and a two-layer wiring structure is obtained.
• a gate electrode 13 is protruded from the surface of the semiconductor substrate 11 and is formed so as to cover the gate electrode 13.
• the high melting point silicide film 15 is formed so as to protrude on the insulating film 14, and large irregularities are formed in the base portion of the interlayer insulating film 17. Therefore, there is a step due to large unevenness on the surface of the interlayer insulating film 17 forming the metal wiring layer made of the aluminum film 18. Become so . Since the aluminum film 18 was formed in the state where the steps exist, the coatability and workability of the aluminum film at the steps were remarkable. It is damaged and the wiring reliability cannot be obtained. Therefore, it is necessary to take measures to alleviate the step due to the unevenness appearing on the surface of the interlayer insulating film 17 ⁇
• the interlayer insulating film 17 is formed by using a PSG (linkage glass) film or a BPSG (boro-linkage glass) film by a CVD method. After the interlayer insulating film 17 is deposited, a heat treatment at 900, for example, is performed to flow (reflow). It is also called a flow) and flattens the surface of the interlayer insulating film 17.
• a heat treatment at 900 for example, is performed to flow (reflow). It is also called a flow) and flattens the surface of the interlayer insulating film 17.
• Such a heat treatment is performed, for example, in a steam atmosphere or a phosphorus oxychloride (POC 13) atmosphere, so that the flow can be performed at a relatively low temperature.
• a steam atmosphere or a phosphorus oxychloride (POC 13) atmosphere
• POC 13 phosphorus oxychloride
• the wiring strength is reduced by the gate electrode film 13 and the silicide film 15, and the distance between the wirings is reduced. It gets worse. Further, due to processing requirements of a metal wiring layer formed by being laminated on the first layered film 16, the metal wiring (the aluminum film 18) is formed. It is required that the surface of the interlayer insulating film 17 before the formation is further planarized.
• the interlayer insulating film 17 is formed in a single process so as to have a desired thickness. Due to the lowering of the circuit structure of the semiconductor device, the shape of the base and the poor coverage at the time of forming the interlayer insulating film 17 correspond to the wiring between the base wiring parts. A gap may be formed at the stepped portion, and a short circuit may occur between the wiring layer and the lower wiring layer in the upper wiring device, and sufficient reliability cannot be obtained.
• FIG. 4 shows that pseudo steps 191 and 192 made of polysilicon are formed on the surface of a semiconductor substrate 11, and the interlayer insulating film 20 made of a PSG film is formed by a CVD method. Since the cross-sectional structure is shown in a state of being accumulated in the gap, the gap 21 is formed between the two pseudo steps 191 and 192. The void 21 expands or ruptures in the step of flattening the interlayer insulating film 20 to form a hole 22 having a diameter of several meters in the interlayer insulating film 20 as shown in FIG. To be able to do so.
• a metal wiring film is formed on an interlayer insulating film 20 and a pseudo step in which the metal wiring becomes a lower wiring in a hole 22 portion.
• Contact with 191 and 192 may cause an electrical short-circuit.
• the cavities 23 remain in the interlayer insulating film 20 as shown in FIG. Is not desirable in terms of the reliability of the semiconductor device.
• the surface of the interlayer insulating film is also required. Although flatness is desired, but as described above, the width of the underlying wiring is narrow and the spacing between wirings is also narrow, and the conventional interlayer insulation In the film manufacturing process, a short circuit may occur between the underlying wiring and the upper wiring, and the reliability of the semiconductor device may be impaired, for example, a cavity may be left in the insulating film. There is a problem.
• the invention of the present invention has been considered as described above, and when forming an interlayer insulating film on a miniaturized wiring layer, the insulating material corresponding to the space between the underlying wiring portions is formed.
• the formation of voids in the film can be reliably prevented, the surface is flattened by the heat treatment process, and the wiring of the upper layer is further facilitated.
• a step of forming an interlayer insulating film on the surface of a semiconductor substrate and then flattening the insulating film by flowing the insulating film is performed. Then, the step of forming the insulating film and the step of planarizing are repeatedly performed a plurality of times so that an interlayer insulating film having a desired thickness is finally formed.
• a first laminated structure composed of, for example, a gate oxide film, an insulating film, and a metal silicide film is formed on a main surface of a semiconductor substrate.
• a step between the underlying wirings is formed. After forming a thin insulating film with a thickness that does not allow voids to form in the substrate, it is allowed to flow through the above heat treatment process, for example, at 700, and the surface of this insulating film is flattened and used as a base. Relieve the existing step shape.
• an insulating film having a thickness that does not allow a void to be formed again is laminated, and the surface is flattened by a heat treatment step. This is repeated. As a result, an interlayer insulating film having a desired thickness is formed.
• FIG. 1A to FIG. 1D are cross-sectional views for sequentially explaining the steps of manufacturing a semiconductor according to one embodiment of the present invention, in particular, the steps of manufacturing an interlayer insulating film using pseudo steps.
• FIG. 2 is a diagram showing the relationship between the distance between the underlying wiring and the deposited film thickness after the deposition of the insulating film for planarization and the distance between the steps of the deposited film
• FIG. 3 is a diagram showing the conventional semiconductor device.
• FIGS. 4 to 6 are cross-sectional views showing a multilayer wiring portion, and are cross-sectional views for explaining the problems in the conventional manufacturing method using pseudo steps.
• a semiconductor substrate having a pseudo step formed on the surface is used as an underlayer, and the underlayer is used as an underlayer.
• a planarization insulating film composed of BPSG is deposited by CVD, and trials are performed by changing the conditions such as the thickness of this insulating film and the interval between pseudo steps. went. This is described below as an example O
• a pseudo step 22 corresponding to an underlying wiring formed of a 0.8-m-high polysilicon is used on the surface of the semiconductor substrate 21. 1, 2 and 2 are formed.
• a first planarizing insulating film 23 is formed, and thus the first insulating film 23 is formed.
• the film thickness t of 23 is configured to be sufficiently thin as compared with the required thickness of the interlayer insulating film.
• the thickness t is limited to a small value, and at least 0.1 m so as to prevent the interval Y from becoming "0".
• the film thickness t at which the interval Y is set is selected.
• the thickness of the insulating film growing on the sides of the pseudo steps 221 and 222 is about 12 of the deposited film thickness t, and accordingly, the difference between the pseudo steps 221 and 222 is large.
• the thickness t of the first insulating film 23 is selected in relation to the interval X. For example, "t.
• the width of the wiring portion formed by the pseudo steps 221 and 222 is W
• the wiring interval is X
• the interval Y is changed.
• the horizontal axis indicates the wiring interval X (equivalent to the wiring width W)
• the vertical axis indicates the measured value of the interval Y (m) after the insulating film (BPSG) is deposited.
• the parameter is the deposited film thickness t of the insulating film
• curves A, B, and C are the thickness t forces of 0.2 ⁇ m, 0.4 m, and 0, respectively.
• a gap is generated in the insulating film when the value of the vertical axis Y becomes “0”.
• the thickness of the insulating film 23 where no void is formed is determined with reference to FIG.
• the first insulating film 23 is formed in this way, as shown in FIG. B, for example, heat treatment is performed for 900 minutes in an atmosphere of N 2, and a constant 2 S And flatten its surface. In this case, no void is formed in the first insulating film 23, but the surface thereof has unevenness of the underlying portion, and both the flatness and the insulating property are insufficient. . Therefore, the same steps as those for forming the first insulating film 23 are repeated until the film thickness becomes sufficient as the interlayer insulating film.
• the film 24 is deposited.
• heat treatment was performed for 90 minutes and 30 minutes in a steam atmosphere, and the insulating films 23 and 24 were flowed and flattened. So that a simplified interlayer insulating film 25 can be obtained 0
• a planarization insulating film is deposited on a base on which a pseudo wiring is formed on the surface of a semiconductor substrate. It was flattened by heat treatment. Based on the data of such an embodiment, for example, when an actual semiconductor device as shown in FIG. 3 was manufactured, the embodiment described with pseudo wiring was used. Comparable results were obtained.
• a BPSG film formed by an atmospheric pressure CVD method was used for a planarizing insulating film, but a PSG film or a PSG film formed by an atmospheric pressure CVD method was used.
• a BPSG film or a PSG film may be formed by a film forming method such as low-pressure CVD or plasma CVD.
• similar results can be obtained by using a flattened coating film such as spin glass.
• the heat treatment step instead of the N 2 atmosphere or the steam atmosphere shown in the embodiment, another atmosphere such as POC 12 or oxygen is used. Rabbit annealing and high-pressure heat treatment can also be used as the heat treatment step.
• the number of repetitions of the process of depositing the insulating film and flattening by heat treatment is shown as two in the embodiment, but this is the fineness of the wiring part.
• the number of times of re-turning can be increased as appropriate.
• an interlayer insulating film is formed on a fine wiring layer formed in a semiconductor substrate shape.
• an insulating film is deposited and formed so as to prevent generation of voids or the like in the insulating film, and the surface thereof is planarized. Therefore, this insulating film It is easy to further form a wiring layer on top of this, and a highly reliable semiconductor device can be formed. In other words, a highly integrated semiconductor device can be reliably manufactured in a more reliable state.

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• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Manufacturing & Machinery (AREA)
• Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
• Formation Of Insulating Films (AREA)

Applications Claiming Priority (2)

Publications (1)

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Citations (3)

• 1990
  • 1990-01-18 JP JP916390A patent/JPH03212958A/ja active Pending
• 1991
  • 1991-01-17 WO PCT/JP1991/000040 patent/WO1991011023A1/ja active Application Filing
  • 1991-01-17 DE DE19914190089 patent/DE4190089T1/de not_active Ceased

Patent Citations (3)

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