WO1991011023A1 - Method of producing semiconductor devices - Google Patents

Method of producing semiconductor devices Download PDF

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Publication number
WO1991011023A1
WO1991011023A1 PCT/JP1991/000040 JP9100040W WO9111023A1 WO 1991011023 A1 WO1991011023 A1 WO 1991011023A1 JP 9100040 W JP9100040 W JP 9100040W WO 9111023 A1 WO9111023 A1 WO 9111023A1
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WO
WIPO (PCT)
Prior art keywords
insulating film
film
thickness
wiring
interlayer insulating
Prior art date
Application number
PCT/JP1991/000040
Other languages
French (fr)
Japanese (ja)
Inventor
Akimitu Yonekura
Original Assignee
Kabushiki Kaisha Toshiba
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Publication date
Application filed by Kabushiki Kaisha Toshiba filed Critical Kabushiki Kaisha Toshiba
Publication of WO1991011023A1 publication Critical patent/WO1991011023A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a method for manufacturing a semiconductor device, and more particularly to a semiconductor device having a multilayer wiring structure in which a conductor layer is formed in a plurality of layers via an insulating layer.
  • the present invention relates to a method for manufacturing a semiconductor device in which a method for flattening the surface of an interlayer insulating film between layers is improved.
  • a multilayer structure is adopted for a wiring layer of the semiconductor device. That is, an electrode layer connected to each circuit element portion is formed on a semiconductor substrate on which a number of various circuit elements are formed, and an insulating film is formed on the electrode layer. Then, a first wiring layer is formed on the insulating film. In addition, a structure is adopted in which an interlayer insulating film is formed on the first wiring layer and a second wiring layer is formed on the insulating film. . In the case of such a multilayer wiring structure, it is very important to flatten the surface of the interlayer insulating film on which each wiring layer is formed in order to increase the reliability of each wiring layer. O
  • an interlayer insulating film still has irregularities due to the wiring pattern present thereunder.
  • a gate oxide film 12 is interposed on the surface of the semiconductor substrate 11.
  • the semiconductor substrate 11 including the gate electrode film 13 is formed.
  • An insulating film 14 is formed on the surface of the substrate.
  • a high melting point silicide film 15 constituting the first wiring is formed on the insulating film 14 to form a first layered film 16.
  • an interlayer insulating film 17 is further formed as a second laminated film, and a second wiring is formed on the interlayer insulating film 17.
  • an aluminum film 18 is formed, and a two-layer wiring structure is obtained.
  • a gate electrode 13 is protruded from the surface of the semiconductor substrate 11 and is formed so as to cover the gate electrode 13.
  • the high melting point silicide film 15 is formed so as to protrude on the insulating film 14, and large irregularities are formed in the base portion of the interlayer insulating film 17. Therefore, there is a step due to large unevenness on the surface of the interlayer insulating film 17 forming the metal wiring layer made of the aluminum film 18. Become so . Since the aluminum film 18 was formed in the state where the steps exist, the coatability and workability of the aluminum film at the steps were remarkable. It is damaged and the wiring reliability cannot be obtained. Therefore, it is necessary to take measures to alleviate the step due to the unevenness appearing on the surface of the interlayer insulating film 17 ⁇
  • the interlayer insulating film 17 is formed by using a PSG (linkage glass) film or a BPSG (boro-linkage glass) film by a CVD method. After the interlayer insulating film 17 is deposited, a heat treatment at 900, for example, is performed to flow (reflow). It is also called a flow) and flattens the surface of the interlayer insulating film 17.
  • a heat treatment at 900 for example, is performed to flow (reflow). It is also called a flow) and flattens the surface of the interlayer insulating film 17.
  • Such a heat treatment is performed, for example, in a steam atmosphere or a phosphorus oxychloride (POC 13) atmosphere, so that the flow can be performed at a relatively low temperature.
  • a steam atmosphere or a phosphorus oxychloride (POC 13) atmosphere
  • POC 13 phosphorus oxychloride
  • the wiring strength is reduced by the gate electrode film 13 and the silicide film 15, and the distance between the wirings is reduced. It gets worse. Further, due to processing requirements of a metal wiring layer formed by being laminated on the first layered film 16, the metal wiring (the aluminum film 18) is formed. It is required that the surface of the interlayer insulating film 17 before the formation is further planarized.
  • the interlayer insulating film 17 is formed in a single process so as to have a desired thickness. Due to the lowering of the circuit structure of the semiconductor device, the shape of the base and the poor coverage at the time of forming the interlayer insulating film 17 correspond to the wiring between the base wiring parts. A gap may be formed at the stepped portion, and a short circuit may occur between the wiring layer and the lower wiring layer in the upper wiring device, and sufficient reliability cannot be obtained.
  • FIG. 4 shows that pseudo steps 191 and 192 made of polysilicon are formed on the surface of a semiconductor substrate 11, and the interlayer insulating film 20 made of a PSG film is formed by a CVD method. Since the cross-sectional structure is shown in a state of being accumulated in the gap, the gap 21 is formed between the two pseudo steps 191 and 192. The void 21 expands or ruptures in the step of flattening the interlayer insulating film 20 to form a hole 22 having a diameter of several meters in the interlayer insulating film 20 as shown in FIG. To be able to do so.
  • a metal wiring film is formed on an interlayer insulating film 20 and a pseudo step in which the metal wiring becomes a lower wiring in a hole 22 portion.
  • Contact with 191 and 192 may cause an electrical short-circuit.
  • the cavities 23 remain in the interlayer insulating film 20 as shown in FIG. Is not desirable in terms of the reliability of the semiconductor device.
  • the surface of the interlayer insulating film is also required. Although flatness is desired, but as described above, the width of the underlying wiring is narrow and the spacing between wirings is also narrow, and the conventional interlayer insulation In the film manufacturing process, a short circuit may occur between the underlying wiring and the upper wiring, and the reliability of the semiconductor device may be impaired, for example, a cavity may be left in the insulating film. There is a problem.
  • the invention of the present invention has been considered as described above, and when forming an interlayer insulating film on a miniaturized wiring layer, the insulating material corresponding to the space between the underlying wiring portions is formed.
  • the formation of voids in the film can be reliably prevented, the surface is flattened by the heat treatment process, and the wiring of the upper layer is further facilitated.
  • a step of forming an interlayer insulating film on the surface of a semiconductor substrate and then flattening the insulating film by flowing the insulating film is performed. Then, the step of forming the insulating film and the step of planarizing are repeatedly performed a plurality of times so that an interlayer insulating film having a desired thickness is finally formed.
  • a first laminated structure composed of, for example, a gate oxide film, an insulating film, and a metal silicide film is formed on a main surface of a semiconductor substrate.
  • a step between the underlying wirings is formed. After forming a thin insulating film with a thickness that does not allow voids to form in the substrate, it is allowed to flow through the above heat treatment process, for example, at 700, and the surface of this insulating film is flattened and used as a base. Relieve the existing step shape.
  • an insulating film having a thickness that does not allow a void to be formed again is laminated, and the surface is flattened by a heat treatment step. This is repeated. As a result, an interlayer insulating film having a desired thickness is formed.
  • FIG. 1A to FIG. 1D are cross-sectional views for sequentially explaining the steps of manufacturing a semiconductor according to one embodiment of the present invention, in particular, the steps of manufacturing an interlayer insulating film using pseudo steps.
  • FIG. 2 is a diagram showing the relationship between the distance between the underlying wiring and the deposited film thickness after the deposition of the insulating film for planarization and the distance between the steps of the deposited film
  • FIG. 3 is a diagram showing the conventional semiconductor device.
  • FIGS. 4 to 6 are cross-sectional views showing a multilayer wiring portion, and are cross-sectional views for explaining the problems in the conventional manufacturing method using pseudo steps.
  • a semiconductor substrate having a pseudo step formed on the surface is used as an underlayer, and the underlayer is used as an underlayer.
  • a planarization insulating film composed of BPSG is deposited by CVD, and trials are performed by changing the conditions such as the thickness of this insulating film and the interval between pseudo steps. went. This is described below as an example O
  • a pseudo step 22 corresponding to an underlying wiring formed of a 0.8-m-high polysilicon is used on the surface of the semiconductor substrate 21. 1, 2 and 2 are formed.
  • a first planarizing insulating film 23 is formed, and thus the first insulating film 23 is formed.
  • the film thickness t of 23 is configured to be sufficiently thin as compared with the required thickness of the interlayer insulating film.
  • the thickness t is limited to a small value, and at least 0.1 m so as to prevent the interval Y from becoming "0".
  • the film thickness t at which the interval Y is set is selected.
  • the thickness of the insulating film growing on the sides of the pseudo steps 221 and 222 is about 12 of the deposited film thickness t, and accordingly, the difference between the pseudo steps 221 and 222 is large.
  • the thickness t of the first insulating film 23 is selected in relation to the interval X. For example, "t.
  • the width of the wiring portion formed by the pseudo steps 221 and 222 is W
  • the wiring interval is X
  • the interval Y is changed.
  • the horizontal axis indicates the wiring interval X (equivalent to the wiring width W)
  • the vertical axis indicates the measured value of the interval Y (m) after the insulating film (BPSG) is deposited.
  • the parameter is the deposited film thickness t of the insulating film
  • curves A, B, and C are the thickness t forces of 0.2 ⁇ m, 0.4 m, and 0, respectively.
  • a gap is generated in the insulating film when the value of the vertical axis Y becomes “0”.
  • the thickness of the insulating film 23 where no void is formed is determined with reference to FIG.
  • the first insulating film 23 is formed in this way, as shown in FIG. B, for example, heat treatment is performed for 900 minutes in an atmosphere of N 2, and a constant 2 S And flatten its surface. In this case, no void is formed in the first insulating film 23, but the surface thereof has unevenness of the underlying portion, and both the flatness and the insulating property are insufficient. . Therefore, the same steps as those for forming the first insulating film 23 are repeated until the film thickness becomes sufficient as the interlayer insulating film.
  • the film 24 is deposited.
  • heat treatment was performed for 90 minutes and 30 minutes in a steam atmosphere, and the insulating films 23 and 24 were flowed and flattened. So that a simplified interlayer insulating film 25 can be obtained 0
  • a planarization insulating film is deposited on a base on which a pseudo wiring is formed on the surface of a semiconductor substrate. It was flattened by heat treatment. Based on the data of such an embodiment, for example, when an actual semiconductor device as shown in FIG. 3 was manufactured, the embodiment described with pseudo wiring was used. Comparable results were obtained.
  • a BPSG film formed by an atmospheric pressure CVD method was used for a planarizing insulating film, but a PSG film or a PSG film formed by an atmospheric pressure CVD method was used.
  • a BPSG film or a PSG film may be formed by a film forming method such as low-pressure CVD or plasma CVD.
  • similar results can be obtained by using a flattened coating film such as spin glass.
  • the heat treatment step instead of the N 2 atmosphere or the steam atmosphere shown in the embodiment, another atmosphere such as POC 12 or oxygen is used. Rabbit annealing and high-pressure heat treatment can also be used as the heat treatment step.
  • the number of repetitions of the process of depositing the insulating film and flattening by heat treatment is shown as two in the embodiment, but this is the fineness of the wiring part.
  • the number of times of re-turning can be increased as appropriate.
  • an interlayer insulating film is formed on a fine wiring layer formed in a semiconductor substrate shape.
  • an insulating film is deposited and formed so as to prevent generation of voids or the like in the insulating film, and the surface thereof is planarized. Therefore, this insulating film It is easy to further form a wiring layer on top of this, and a highly reliable semiconductor device can be formed. In other words, a highly integrated semiconductor device can be reliably manufactured in a more reliable state.

Abstract

False steps (211, 222) corresponding to a first wiring are formed on a semiconductor substrate (21) maintaining a gap of 1 νm, and a first insulating film (23) having a thickness of 0.5 νm is formed over the false steps. The film thickness is so selected that a gap Y is formed between the false steps (211 and 222). Then, the heat treatment is effected in, for example, a water vapor atmosphere at 900 °C for 20 minutes so that the first insulating film (23) reflows to have a flat surface. Then, a second insulating film (24) is formed and heat-treated until it reflows to have a flat surface, thereby to form an interlayer insulating film (25) having a predetermined film thickness.

Description

明 半 導 体 装 置 の 製 造 方 法 技術分野  Method for manufacturing semiconductor devices
こ の発明 は、 半導体装置の製造方法 に 関す る も の であ り 特に絶縁層を介 し'て複数の層 に導体層が形成 さ れる 多層配 線構造の半導体装置 に お い て、 各導体層間の層間絶緣膜の 表面を平坦化す る 方法を改良 し た半導体装置の製造方法に 係 る も の で あ る 。  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a semiconductor device having a multilayer wiring structure in which a conductor layer is formed in a plurality of layers via an insulating layer. The present invention relates to a method for manufacturing a semiconductor device in which a method for flattening the surface of an interlayer insulating film between layers is improved.
背景技術  Background art
半導体装置の高集積化、 さ ら に高密度化等に伴 っ て、 こ の半導体装置の配線層は多層化構造が採用 さ れ る 。 すな わ ち 、 多数の各種回路素子が形成 さ れた半導体基板上 に、 各 回路素子部に接続 さ れた電極層を形成す る と 共に、 こ の電 極層上に絶縁膜を形成 し 、 こ の絶縁膜上に第 1 の配線層.を 形成す る 。 そ し て、 さ ら に こ の第 1 の配線層の上に層間絶 縁膜を形成 し 、 こ の絶縁膜上に第 2 の配線層を形成す る よ う な構造が採用 さ れてい る 。 こ の様な多層配線構造 と し た 場合、 各配線層の信頼性を高め る た め に は、 各配線層が形 成 さ れ る 層間絶縁膜の表面を平坦化す る こ と が非常に重要 め る o  2. Description of the Related Art With the increase in the degree of integration and the density of a semiconductor device, a multilayer structure is adopted for a wiring layer of the semiconductor device. That is, an electrode layer connected to each circuit element portion is formed on a semiconductor substrate on which a number of various circuit elements are formed, and an insulating film is formed on the electrode layer. Then, a first wiring layer is formed on the insulating film. In addition, a structure is adopted in which an interlayer insulating film is formed on the first wiring layer and a second wiring layer is formed on the insulating film. . In the case of such a multilayer wiring structure, it is very important to flatten the surface of the interlayer insulating film on which each wiring layer is formed in order to increase the reliability of each wiring layer. O
—般的 に層間絶縁膜の表面 に は、 そ の下層 に存在す る 配 線パ タ ー ン に よ る 凹凸がそ の ま ま 存在す る 。 例え ば第 3 図 に示すよ う に、 半導体基板 1 1の表面に ゲー ト 酸化膜 1 2を介 し てポ リ シ リ コ ン膜に よ っ て構成 さ れたゲ一 ト 電極膜 1 3が 形成 さ れた半導体装置 においては、 こ の ゲー ト 電極膜 1 3部 分を含む半導体基板 1 1の表面に絶縁膜 14が形成 さ れ る 。 そ し て、 こ の絶縁膜 14上に第 1 の配線を構成す る 高融点 シ リ サ イ ド膜 1 5が形成 さ れ、 第 1 層の積層膜 1 6が構成 さ れ る 。 —Generally, the surface of an interlayer insulating film still has irregularities due to the wiring pattern present thereunder. For example, as shown in FIG. 3, a gate oxide film 12 is interposed on the surface of the semiconductor substrate 11. Then, in a semiconductor device having a gate electrode film 13 formed of a polysilicon film formed thereon, the semiconductor substrate 11 including the gate electrode film 13 is formed. An insulating film 14 is formed on the surface of the substrate. Then, a high melting point silicide film 15 constituting the first wiring is formed on the insulating film 14 to form a first layered film 16.
こ の第 1 層の積層膜 1 6の表面上に は、 さ ら に第 2 の積層 膜 と し て層間絶緣膜 1 7が形成 さ れ、 こ の層間絶縁膜 1 7上に 第 2 の配線 と さ れ る ア ル ミ ニ ウ ム膜 1 8が形成 さ れ、 2 層配 線構造 と さ れ る よ う に な る 。  On the surface of the first-layer laminated film 16, an interlayer insulating film 17 is further formed as a second laminated film, and a second wiring is formed on the interlayer insulating film 17. Thus, an aluminum film 18 is formed, and a two-layer wiring structure is obtained.
こ の様に し て多層配線を行 う 場合、 半導体基板 1 1の表面 に ゲー ト 電極 1 3が突設さ れ、 さ ら に こ の ゲー ト 電極 1 3部を 覆 う よ う に形成 さ れた絶縁膜 1 4上に突設 し た状態で高融点 シ リ サイ ド膜 1 5が形成 さ れてい る し フ が つ て、 層間絶縁 膜 1 7の下地部分に は大 き な 凹凸が存在 し てお り 、 こ の た め ア ル ミ 二 ゥ ム膜 1 8に よ る 金属配線層を形成す る 層間絶縁膜 1 7の表面に、 大 き な 凹凸に よ る 段差部が存在す る よ う に な る 。 こ の様に段差が存在す る 状態で ア ル ミ ニ ゥ ム膜 1 8を形 成 し た ので は、 段差部に おい てァ ル ミ 二 ゥ ム膜の被覆性、 加工性が著 し く 損なわれ、 配線の信頼性が得 ら れな い。 し たが っ て、 層間絶縁膜 1 7の表面に現れる 凹凸 に よ る 段差部 を緩和す る た め の処置が必要 と な る ο  In the case of performing multi-layer wiring in this way, a gate electrode 13 is protruded from the surface of the semiconductor substrate 11 and is formed so as to cover the gate electrode 13. The high melting point silicide film 15 is formed so as to protrude on the insulating film 14, and large irregularities are formed in the base portion of the interlayer insulating film 17. Therefore, there is a step due to large unevenness on the surface of the interlayer insulating film 17 forming the metal wiring layer made of the aluminum film 18. Become so . Since the aluminum film 18 was formed in the state where the steps exist, the coatability and workability of the aluminum film at the steps were remarkable. It is damaged and the wiring reliability cannot be obtained. Therefore, it is necessary to take measures to alleviate the step due to the unevenness appearing on the surface of the interlayer insulating film 17 ο
こ の た め層間絶縁膜 1 7は、 C V D 法に よ る P S G ( リ ン ケ ィ 酸ガラ ス ） 膜、 あ る い は B P S G (ボ ロ ン リ ン ケ ィ 酸ガラ ス） 膜を使用 し て構成 し、 こ の層間絶縁膜 1 7が堆積 さ れた後に、 例えば 9 0 0 での熱処理を行 っ て フ ロ ー （ リ フ ロ ー と も 呼ばれ る ） し 、 層間絶縁膜 17の表面を平坦化す る For this reason, the interlayer insulating film 17 is formed by using a PSG (linkage glass) film or a BPSG (boro-linkage glass) film by a CVD method. After the interlayer insulating film 17 is deposited, a heat treatment at 900, for example, is performed to flow (reflow). It is also called a flow) and flattens the surface of the interlayer insulating film 17.
こ の様な熱処理は、 例え ば水蒸気雰囲気中 あ る い はォ キ シ塩化 リ ン （ P O C 1 3 ) 雰囲気中で行われ る も の で、 比 較的低温の状態で フ ロ ーで き る。  Such a heat treatment is performed, for example, in a steam atmosphere or a phosphorus oxychloride (POC 13) atmosphere, so that the flow can be performed at a relatively low temperature. .
半導体装置の高集積化に よ る 微細化構造に よ っ て、 ゲー ト 電極膜 13さ ら に シ リ サ イ ド膜 15に よ る 配線力 細 く な り 、 ま た配線相互の 間隔が狭 く な る 。 そ し て、 さ ら に こ の第 1 層の積層膜 16上に積層 し て形成 さ れ る 金属配線層の加工上 の要求か ら 、 こ の金属配線 （ ア ル ミ ニ ウ ム膜 18) の形成前 に お け る 層間絶縁膜 17の表面は、 よ り 平坦化す る こ と が要 求 さ れ る 。  Due to the miniaturized structure due to the high integration of the semiconductor device, the wiring strength is reduced by the gate electrode film 13 and the silicide film 15, and the distance between the wirings is reduced. It gets worse. Further, due to processing requirements of a metal wiring layer formed by being laminated on the first layered film 16, the metal wiring (the aluminum film 18) is formed. It is required that the surface of the interlayer insulating film 17 before the formation is further planarized.
従来 に あ ό て は、 こ の層間絶縁膜 17は、 所望の厚 さ と な る よ う に 1 回の工程で形成 さ れて い る。 し 力、 し 、 半導体装 置の 回路構造の微細化に 伴 う 下地の形状や層間絶縁膜 17の 形成時に お け る 被覆性の悪 さ が原因 と な っ て、 下地配線部 相互間 に対応 し た段差部に空隙がで き た り 、 さ ら に上層の 配線装置下層の配線層 と の 間 に短絡が生ず る こ と があ り 、 充分な 信頼性が得 ら れな い。  Conventionally, the interlayer insulating film 17 is formed in a single process so as to have a desired thickness. Due to the lowering of the circuit structure of the semiconductor device, the shape of the base and the poor coverage at the time of forming the interlayer insulating film 17 correspond to the wiring between the base wiring parts. A gap may be formed at the stepped portion, and a short circuit may occur between the wiring layer and the lower wiring layer in the upper wiring device, and sufficient reliability cannot be obtained.
こ の様な 問題点につ い て、 第 4 図乃至第 6 図を用 い て さ ら に説明す る 。 第 4 図は半導体基板 11の表面上に、 ポ リ シ リ コ ン に よ っ て構成 し た疑似段差 191 、 192 を形成 し 、 Β P S G 膜 に よ る 層間絶縁膜 20を C V D 法に よ っ て滞積 し た 状態の断面構造を示 し てい る も ので、 2 つ の疑似段差 191 お よ び 192 の間 に空隙 21が形成 さ れ る よ う に な る 。 の空隙 2 1は、 層間絶縁膜 2 0を平坦化す る 工程におい て 膨脹あ る い は破裂 し 、 第 5 図で示すよ う に層間絶縁膜 2 0に 直径数 m の穴 2 2を形成 さ せ る よ う に な る 。 実際の半導体 装置に あ つ て は、 層間絶縁膜 2 0上に金属配線膜を形成 し た ノロ 、 こ の金属配線が穴 2 2部で下層の配線 と な る 疑似段差Such a problem will be further described with reference to FIGS. 4 to 6. FIG. FIG. 4 shows that pseudo steps 191 and 192 made of polysilicon are formed on the surface of a semiconductor substrate 11, and the interlayer insulating film 20 made of a PSG film is formed by a CVD method. Since the cross-sectional structure is shown in a state of being accumulated in the gap, the gap 21 is formed between the two pseudo steps 191 and 192. The void 21 expands or ruptures in the step of flattening the interlayer insulating film 20 to form a hole 22 having a diameter of several meters in the interlayer insulating film 20 as shown in FIG. To be able to do so. In an actual semiconductor device, a metal wiring film is formed on an interlayer insulating film 20 and a pseudo step in which the metal wiring becomes a lower wiring in a hole 22 portion.
1 9 1 、 1 9 2 に接触 し、 電気的 に短絡す る 事故が発生す る よ う に な る 。 Contact with 191 and 192 may cause an electrical short-circuit.
ま た、 こ の様な穴 2 2が発生す る 状態に至 ら な い よ う な場 合で も 、 第 6 図で示すよ う に層間絶緣膜 2 0の 中 に空洞 2 3が 残 り 、 半導体装置の信頼性の上で好ま し く な い  Further, even in a case where such a state that the holes 22 are not generated is obtained, the cavities 23 remain in the interlayer insulating film 20 as shown in FIG. Is not desirable in terms of the reliability of the semiconductor device.
半導体装置の高集積化 さ ら に微細化に伴 っ て 、 多層配線 構造が多用 さ れ る も のであ り 、 こ の多層配線層の信頼性を 高め る た め に も 層間絶縁膜の表面の平坦性が望ま れてい る し か し、 こ れま で述べた よ う に下地の配線の幅 も狭 く 、 且 つ配線相互間の 間隔 も 狭 く な る 現状 に おいて、 従来の層間 絶縁膜の製造工程では、 下地配線 と 上層配線 と の短絡が起 こ る 虞があ り 、 ま た絶縁膜中に空洞が残 る 可能性があ る 等 の、 半導体装置の信頼性を損な う 問題力 あ る 。  As the integration of semiconductor devices and the miniaturization of semiconductor devices increase, multilayer wiring structures are often used.In order to increase the reliability of the multilayer wiring layers, the surface of the interlayer insulating film is also required. Although flatness is desired, but as described above, the width of the underlying wiring is narrow and the spacing between wirings is also narrow, and the conventional interlayer insulation In the film manufacturing process, a short circuit may occur between the underlying wiring and the upper wiring, and the reliability of the semiconductor device may be impaired, for example, a cavity may be left in the insulating film. There is a problem.
の発明 は上記の よ う な点 みな さ れた も ので、 微細 化 さ れた配線層の上に層間絶縁膜を形成す る に際 し て、 下 地配線部の 間隔部に対応す る絶縁膜中 に、 空隙等が発生す る こ と を確実に防止す る こ と がで き 、 熱処理ェ程に よ っ て 表面が平坦化さ れ、 そ の上に さ ら に上層の配線が容易且つ 確実に形成さ れ、 半導体装置 と し ての信頼性が確実に得 ら れ る よ う に し た半導体装置の製造方法を提供す る こ と を 目 的 と す る 。 The invention of the present invention has been considered as described above, and when forming an interlayer insulating film on a miniaturized wiring layer, the insulating material corresponding to the space between the underlying wiring portions is formed. The formation of voids in the film can be reliably prevented, the surface is flattened by the heat treatment process, and the wiring of the upper layer is further facilitated. It is another object of the present invention to provide a method for manufacturing a semiconductor device, which is formed surely and ensures reliability as a semiconductor device. Target.
発明 の開示  DISCLOSURE OF THE INVENTION
こ の発明 に係 る 半導体装置の製造方法 に あ っ て は、 半導 体基板の表面に層間絶縁膜を形成 し た後、 こ の絶縁膜を フ ロ ー し て平坦化す る 工程にお いて、 絶縁膜を形成す る工程 と 平坦化す る工程 と を複数回繰 り 返 し て行わせ、 最終的 に 目 的 と す る厚 さ の層間絶縁膜が形成 さ れ る よ う にす る 。  In the method of manufacturing a semiconductor device according to the present invention, a step of forming an interlayer insulating film on the surface of a semiconductor substrate and then flattening the insulating film by flowing the insulating film is performed. Then, the step of forming the insulating film and the step of planarizing are repeatedly performed a plurality of times so that an interlayer insulating film having a desired thickness is finally formed.
こ の様な半導体の製造方法に お い て は、 半導体基板の主 表面上、 例え ばゲー ト 酸化膜、 絶縁膜お よ び金属 シ リ サ イ ド膜か ら 構成 さ れ る 第 1 の積層膜に よ っ て構成 さ れた下地 配線が形成 さ れた基板の主表面上に 、 さ ら に平坦な層間絶 縁膜を形成す る 工程に お い て、 下地配線の相互間の段差部 に空隙がで き な い程度の厚 さ の薄い絶縁膜を形成 し た後、 例え ば 7 0 0 で以上の熱処理工程で フ ロ ー し、 こ の絶縁膜 の表面を平坦化 し て下地に存在 し た段差形状を緩和す る 。 そ の後、 再び空隙がで き な い程度の厚 さ の絶縁膜を積層形 成 し 、 熱処理工程 に よ っ て そ の表面を平坦化す る も のであ り 、 こ れを繰 り 返す こ と に よ つ て 目 的の厚 さ の層間絶縁膜 が形成 さ れ る よ う に な る。  In such a method of manufacturing a semiconductor, a first laminated structure composed of, for example, a gate oxide film, an insulating film, and a metal silicide film is formed on a main surface of a semiconductor substrate. In the step of forming a flatter interlayer insulating film on the main surface of the substrate on which the underlying wiring composed of the film is formed, a step between the underlying wirings is formed. After forming a thin insulating film with a thickness that does not allow voids to form in the substrate, it is allowed to flow through the above heat treatment process, for example, at 700, and the surface of this insulating film is flattened and used as a base. Relieve the existing step shape. After that, an insulating film having a thickness that does not allow a void to be formed again is laminated, and the surface is flattened by a heat treatment step. This is repeated. As a result, an interlayer insulating film having a desired thickness is formed.
図面の簡単な説明  BRIEF DESCRIPTION OF THE FIGURES
第 1 図 A 乃至第 1 図 D は こ の発明 の一実施例 に係 る 半導 体の製造方法の特に層間絶縁膜の製造工程を、 疑似的な段 差を用 い て順次説明す る 断面構成図、 第 2 図は平坦化用絶 縁膜の堆積後の下地配線間隔お よ び堆積膜厚 と 堆積膜の段 差部間隔 と の関係を示す図、 第 3 図 は従来の半導体装置の 多層配線部を示す断面図、 第 4 図乃至第 6 図 はそれぞれ従 来の製造方法に お け る 問題点を疑似段差を用 いて説明す る 断面図であ る 。 FIG. 1A to FIG. 1D are cross-sectional views for sequentially explaining the steps of manufacturing a semiconductor according to one embodiment of the present invention, in particular, the steps of manufacturing an interlayer insulating film using pseudo steps. FIG. 2 is a diagram showing the relationship between the distance between the underlying wiring and the deposited film thickness after the deposition of the insulating film for planarization and the distance between the steps of the deposited film, and FIG. 3 is a diagram showing the conventional semiconductor device. FIGS. 4 to 6 are cross-sectional views showing a multilayer wiring portion, and are cross-sectional views for explaining the problems in the conventional manufacturing method using pseudo steps.
発明 を実施す る た めの最良の形態  BEST MODE FOR CARRYING OUT THE INVENTION
こ の発明を実施す る に 当た り 、 試行結果の再現性等を考 慮 し て、 半導体基板の表面に疑似段差を形成 し た も のを下 地 と し て使用 し、 こ の下地上に例え ば B P S G に よ つ て構 成 さ れた平坦化用絶縁膜を C V D 法に よ っ て堆積 し 、 こ の 絶縁膜の膜厚さ ら に疑似段差の 間隔等の条件を変え て試行 を行 っ た。 以下に こ れを実施例 と し て説明す る O  In practicing this invention, in consideration of the reproducibility of trial results, etc., a semiconductor substrate having a pseudo step formed on the surface is used as an underlayer, and the underlayer is used as an underlayer. For example, a planarization insulating film composed of BPSG is deposited by CVD, and trials are performed by changing the conditions such as the thickness of this insulating film and the interval between pseudo steps. went. This is described below as an example O
第 1 図 A で示すよ う に、 半導体基板 2 1の表面上に例えば 高 さ 0 . 8 m の ポ リ シ リ コ ン に よ っ て構成 し た下地配線 に相 当す る 疑似段差 2 2 1 、 2 2 2 を形成す る。 こ の疑似段差 2 2 1 、 2 2 2 の形成 さ れた半導体基板 2 1の表面上に は 、 第 1 の平坦化用絶縁膜 2 3を形成す る も ので、 こ の第 1 の絶縁膜 2 3の膜厚 t は、 要求 さ れ る 層間絶縁膜の厚さ に比較 し て充 分に薄 く 構成 さ れてい る 。  As shown in FIG. 1A, on the surface of the semiconductor substrate 21, for example, a pseudo step 22 corresponding to an underlying wiring formed of a 0.8-m-high polysilicon is used. 1, 2 and 2 are formed. On the surface of the semiconductor substrate 21 on which the pseudo steps 221, 22 are formed, a first planarizing insulating film 23 is formed, and thus the first insulating film 23 is formed. The film thickness t of 23 is configured to be sufficiently thin as compared with the required thickness of the interlayer insulating film.
こ の様に絶縁膜 2 3を堆積 し た場合、 疑似段差 2 2 1 およ び 2 2 2 の それぞれ側方に絶縁層が成長 し 、 疑似段差 2 2 1 お よ び 2 2 2 の相互間で、 こ の成長 さ れた絶縁膜の相互間隔 Yが 膜厚 t の増加 と共に小 さ く な り 、 さ ら に膜厚 t が大き く な る と 相互に接触 し て " t = 0 " と な る も のであ る 力 、 こ の 例に お い て は膜厚 t を小 さ く 制限 し 、 間隔 Yが " 0 " と な ら な い よ う に、 少な く と も 0 . 0 1 m の 間隔 Yが設定 さ れ る 膜厚 t が選定 さ れ る 。 こ の場合、 疑似段差 221 お よ び 222 の側方 に成長す る 絶 縁膜の厚 さ は、 堆積膜厚 t の 1 2 程度であ り 、 し たが つ て疑似段差 221 と 222 と の 間隔 X と の関連で、 こ の第 1 の 絶縁膜 23の厚 さ t が選定 さ れ る 。 例え ば " t く と さ れ る 。 When the insulating film 23 is deposited in this way, an insulating layer grows on each side of the pseudo steps 2 21 and 2 22, and the gap between the pseudo steps 2 2 1 and 2 2 Therefore, the distance Y between the grown insulating films becomes smaller as the film thickness t increases, and when the film thickness t becomes larger, they come into contact with each other and become “t = 0”. In this example, the thickness t is limited to a small value, and at least 0.1 m so as to prevent the interval Y from becoming "0". The film thickness t at which the interval Y is set is selected. In this case, the thickness of the insulating film growing on the sides of the pseudo steps 221 and 222 is about 12 of the deposited film thickness t, and accordingly, the difference between the pseudo steps 221 and 222 is large. The thickness t of the first insulating film 23 is selected in relation to the interval X. For example, "t.
こ の絶縁膜 23の膜厚を大 き く す る と 、 疑似段差 221 お よ び 222 の側方に成長 し た絶縁膜が相互 に接触 し て Yが " 0 " と な り 、 例え ば第 4 図で示 し た よ う に空隙が形成 さ れ る 。 試行結果に よ れば、 間隔 Yが " 0 " と な っ た時点で空隙が 発生 さ れ る こ と が確認 さ れた。  If the thickness of the insulating film 23 is increased, the insulating films grown on the sides of the pseudo steps 221 and 222 come into contact with each other, and Y becomes “0”. 4 Voids are formed as shown in the figure. According to the trial result, it was confirmed that a gap was generated when the interval Y became “0”.
こ の 図 に お い て、 疑似段差 221 、 222 に よ る 配線部の幅 を W、 配線間隔を X と し 、 平坦化用絶縁膜 23の厚 さ t を変 え た と き に 間隔 Y を測定す る 試行を行 っ た と こ ろ 、 第 2 図 で示すよ う な結果が得 ら れた。 こ の図で横軸 は配線間隔 X (配線幅 Wに等 し い） であ っ て、 縦軸 は絶縁膜 （ B P S G ) 堆積後の 間隔 Y ( m の測定値を示 し てい る 。 そ し て、 パ ラ メ ー タ は絶緣膜の堆積膜厚 t であ っ て、 曲線 A、 B 、 お よ び C は それぞれ膜厚 t 力 0 . 2 〃 m、 0 . 4 m 、 お よ び 0 . 7 m の場合を示 し て い る 。 こ の 図で縦軸 Y の値 が " 0 " と な っ た時点で絶縁膜中 に空隙が発生す る 。  In this figure, the width of the wiring portion formed by the pseudo steps 221 and 222 is W, the wiring interval is X, and when the thickness t of the planarizing insulating film 23 is changed, the interval Y is changed. As a result of the trial for measurement, the results shown in Fig. 2 were obtained. In this figure, the horizontal axis indicates the wiring interval X (equivalent to the wiring width W), and the vertical axis indicates the measured value of the interval Y (m) after the insulating film (BPSG) is deposited. Where the parameter is the deposited film thickness t of the insulating film, and curves A, B, and C are the thickness t forces of 0.2 μm, 0.4 m, and 0, respectively. In this figure, a gap is generated in the insulating film when the value of the vertical axis Y becomes “0”.
し たが っ て、 こ の第 1 図 A の状態で は、 例え ば疑似段差 221 お よ び 222 は、 高 さ 0 . 8 m 、 幅 Wお よ び間隔 X 力 それぞれ l / m で構成 さ れ る も の で、 こ の様な下地 に対 し て空隙ので き な い、 例え ば " t = 0 . 5 β m " の B P S G に よ る 絶縁膜 23が堆積 さ れ る 。 こ の絶緣膜 2 3は公知の方法で堆積 さ れ る も ので、 例え ば 常圧の c V D で反応ガス [ S Η 4 + Β 2 Η 6 + Ρ Η 3 +Therefore, in the state shown in FIG. 1A, for example, the pseudo steps 221 and 222 are each constituted by a height of 0.8 m, a width W and an interval X force of l / m. Therefore, a void cannot be formed in such an underlayer, for example, an insulating film 23 of BPSG of “t = 0.5 βm” is deposited. Since the insulating film 23 is deposited by a known method, for example, the reaction gas [SΗ4 + Β2Β6 + Ρ3 +
0 2 + ( N 2 ) ] を使用す る。 の場合空隙ので き な い絶 緣膜 2 3の厚 さ は、 第 2 図の参照 し て決め ら れ る 。 0 2 + (N 2)]. In this case, the thickness of the insulating film 23 where no void is formed is determined with reference to FIG.
こ の様に し て第 1 の絶縁膜 2 3が形成 さ れた な ら ば 図 B で示す よ う に例え ば N 2 の雰囲気中で 9 0 0 2 0 分の熱処理を行い、 絶緣 2 Sを フ 口 一 し てそ の表面を平坦 化す る 。 こ の様にすれば の第 1 の絶縁膜 2 3に は空隙 は形 成 さ れな いが、 そ の表面 は下地部分の凹凸が残 り 、 平坦 性およ び絶縁性共に不充分であ る 。 し たが っ て、 層間絶縁 膜 と し て充分な膜厚 と な る ま で、 第 1 の絶縁膜 2 3の形成ェ 程 と 同様の工程を緣 り 返す  If the first insulating film 23 is formed in this way, as shown in FIG. B, for example, heat treatment is performed for 900 minutes in an atmosphere of N 2, and a constant 2 S And flatten its surface. In this case, no void is formed in the first insulating film 23, but the surface thereof has unevenness of the underlying portion, and both the flatness and the insulating property are insufficient. . Therefore, the same steps as those for forming the first insulating film 23 are repeated until the film thickness becomes sufficient as the interlayer insulating film.
すな わ ち 、 第 1 図 C で示すよ う に第 1 の絶緣膜 2 3の上に さ ら に例え ば厚 さ 0 . 6 m の空隙が形成 さ れな い膜厚の 第 2 の絶縁膜 2 4を堆積す る 。 そ し て、 さ ら に第 1 図 D に示 すよ う に水蒸気雰囲気中で 9 0 0 、 3 0 分の熱処理を行 い 、 絶縁膜 2 3お よ び 2 4を フ ロ ー し て平坦化 さ れた層間絶縁 膜 2 5が得 ら れ る よ う にする 0  That is, as shown in FIG. 1C, a second insulating film having a thickness such that a gap having a thickness of 0.6 m is not formed on the first insulating film 23. The film 24 is deposited. Then, as shown in Fig. 1 (D), heat treatment was performed for 90 minutes and 30 minutes in a steam atmosphere, and the insulating films 23 and 24 were flowed and flattened. So that a simplified interlayer insulating film 25 can be obtained 0
こ の様に平坦化絶縁膜を堆積す る 工程 と 、 熱処理に よ つ て こ の絶緣膜を平坦化す る 工程 と を、 例え ば連続 して 2 回 綠 り 返す こ と に よ つ て、 緣膜中 に空隙が発生さ れる こ と な く 、 所定の膜厚並びに 面平坦性を有す る 層間絶縁膜が 形成 さ れ る よ う に な る o  By repeating the process of depositing the planarizing insulating film and the process of planarizing the insulating film by heat treatment twice in succession, for example, Opacity is not generated in the film, and an interlayer insulating film having a predetermined film thickness and surface flatness is formed.
こ れま での実施例説明で は、 半導体基板の表面上に疑似 配線を形成 し た下地に対 し て、 平坦化用絶縁膜を堆積 し 、 熱処理に よ っ て平坦化 し た。 こ の様な実施例の デー タ に基 づい て例え ば第 3 図で示 し た よ う な実際の半導体装置を製 造 し た と こ ろ 、 疑似配線に よ っ て説明 し た実施例 と 同等の 結果が得 ら れた。 In the description of the embodiments so far, a planarization insulating film is deposited on a base on which a pseudo wiring is formed on the surface of a semiconductor substrate. It was flattened by heat treatment. Based on the data of such an embodiment, for example, when an actual semiconductor device as shown in FIG. 3 was manufactured, the embodiment described with pseudo wiring was used. Comparable results were obtained.
以上の説明で は、 1 例 と し て平坦化絶縁膜 に常圧 C V D 法 に よ っ て形成 さ れた B P S G 膜を用 い たが、 常圧 C V D 法に よ る P S G 膜、 あ る い は それ以外の例え ば減圧 C V D、 プラ ズマ C V D 等の成膜方法 に よ っ て、 B P S G 膜あ る い は P S G膜を形成す る よ う に し て も よ い。 ま た、 ス ピ ンォ ン グラ ス等の平坦化塗布膜を用 い る よ う に し て も 同様の結 果が得 ら れ る 。 さ ら に熱処理工程 と し て、 実施例で示 し た N 2 雰囲気あ る い は水蒸気雰囲気に代え て、 P O C 1 2 あ る い は酸素等の他の雰囲気を用 い る よ う に し て も よ く 、 さ ら に こ の熱処理工程 と し て ラ ビ ッ ト ァニ ー ル、 高圧熱処理 を用 い る こ と も で き る 。 さ ら に こ の絶縁膜の堆積お よ び熱 処理に よ る 平坦化の工程の繰 り 返 し 回数は、 実施例で は 2 回 と し て示 し たが、 こ れは配線部の微細化の程度、 下地段 差の形状等の条件 に よ っ て は、 さ ら に そ の線 り 返 し 回数力 適宜増加可能であ る 。  In the above description, as an example, a BPSG film formed by an atmospheric pressure CVD method was used for a planarizing insulating film, but a PSG film or a PSG film formed by an atmospheric pressure CVD method was used. For example, a BPSG film or a PSG film may be formed by a film forming method such as low-pressure CVD or plasma CVD. Further, similar results can be obtained by using a flattened coating film such as spin glass. Further, as the heat treatment step, instead of the N 2 atmosphere or the steam atmosphere shown in the embodiment, another atmosphere such as POC 12 or oxygen is used. Rabbit annealing and high-pressure heat treatment can also be used as the heat treatment step. Furthermore, the number of repetitions of the process of depositing the insulating film and flattening by heat treatment is shown as two in the embodiment, but this is the fineness of the wiring part. Depending on the degree of formation, the shape of the base step, and the like, the number of times of re-turning can be increased as appropriate.
産業上の利用可能性  Industrial applicability
以上の よ う な こ の発明 に係 る 半導体装置の製造方法に よ れば、 半導体基板状 に形成 さ れた微細化 さ れた配線層の上 に、 層間絶縁膜を形成す る に 際 し て、 こ の絶縁膜中 に空隙 等が発生す る こ と を防止す る よ う に し て絶縁膜が堆積形成 さ れ、 そ の表面が平坦化 さ れ る 。 し たが っ て、 こ の絶縁膜 の上に さ ら に配線層が積層 し て形成す る こ と が容易であ り 、 且つ信頼性の高い半導体装置を構成す る こ と がで き る よ う に な る 。 すな わ ち 、 よ り 高集積化 し た半導体装置を、 よ り 信頼性の高い状態で確実に製造で き る 。 According to the method of manufacturing a semiconductor device according to the present invention as described above, an interlayer insulating film is formed on a fine wiring layer formed in a semiconductor substrate shape. Thus, an insulating film is deposited and formed so as to prevent generation of voids or the like in the insulating film, and the surface thereof is planarized. Therefore, this insulating film It is easy to further form a wiring layer on top of this, and a highly reliable semiconductor device can be formed. In other words, a highly integrated semiconductor device can be reliably manufactured in a more reliable state.

Claims

請 求 の 範 囲 The scope of the claims
( 1 ) 半導体基板の表面 に絶縁膜を介 し て第 1 の配線が 形成 さ れた第 1 の積層膜上に 、 第 1 の絶縁膜を堆積形成す る 第 1 の工程 と 、  (1) a first step of depositing and forming a first insulating film on a first laminated film having a first wiring formed on a surface of a semiconductor substrate via an insulating film;
こ の第 1 の工程で形成 さ れた第 1 の絶縁膜を熱処理 し 、 フ ロ ー に よ っ て そ の表面を平坦化す る 第 2 の工程 と 、  A second step of heat-treating the first insulating film formed in the first step and flattening the surface thereof by flow;
こ の工程で表面が平坦化 さ れた第 1 の絶縁膜の上 に第 2 の絶縁膜を堆積形成す る 第 3 の工程 と 、  A third step of depositing and forming a second insulating film on the first insulating film whose surface has been planarized in this step;
こ の第 3 の工程で形成 さ れた第 1 の絶縁膜を熱処理 し 、 フ ロ ー に よ っ て そ の表面を平坦化す る 第 4 の工程 と を具備 し 、  A fourth step of heat-treating the first insulating film formed in the third step and flattening the surface thereof by flow, and
こ の絶縁膜の堆積形成す る 工程お よ び平坦化の工程を 繰 り 返す こ と に よ っ て、 所定の厚 さ の層間絶縁膜が形成 さ れ、 こ の層間絶縁膜の上に さ ら に第 2 の配線が形成で き る よ う に し た こ と を特徵 と す る 半導体装置の製造方法。  By repeating the step of depositing and forming the insulating film and the step of planarizing, an interlayer insulating film having a predetermined thickness is formed, and is formed on the interlayer insulating film. And a method of manufacturing a semiconductor device, characterized in that a second wiring can be formed.
( 2 ) 前記第 1 の工程で形成 さ れた第 1 の絶縁膜の厚 さ は、 半導体基板面の前記第 1 の配線層 に よ る 凹凸形状の下 地に対応 し た前記第 1 の積層膜表面で、 前記第 1 の配線の 側方に成長 し た絶縁膜が相互 に接触 さ れ る こ と の な い厚 さ に設定 さ れ る よ う に し た請求項 1 の半導体の製造装置。  (2) The thickness of the first insulating film formed in the first step is equal to the thickness of the first laminate corresponding to the uneven ground of the first wiring layer on the semiconductor substrate surface. 2. The semiconductor manufacturing apparatus according to claim 1, wherein the thickness of the insulating film grown on the film surface is set so that the insulating films grown on the sides of the first wiring are not in contact with each other. .
( 8 ) 前記第 1 の積層膜表面で、 前記第 1 の配線そ れぞ れの側方に成長 し た絶縁膜相互の 間隔が、 0 . 0 1 m 以 上に設定 さ れ る よ う に 、 前記第 1 の絶縁膜の厚 さ が選定 さ れ る よ う に し た請求項 2 の半導体の製造装置。  (8) On the surface of the first laminated film, the distance between the insulating films grown on the sides of each of the first wirings is set to 0.01 m or more. 3. The semiconductor manufacturing apparatus according to claim 2, wherein a thickness of said first insulating film is selected.
( 4 ) 前記第 1 の絶縁膜の厚 さ は、 前記半導体基板の表 面部の第 1 の配線の相互間隔の少な く と も 1 Z 2 以下に選 定 さ れ る よ う に し た請求項 1 の半導体の製造装置。 (4) The thickness of the first insulating film is equal to the thickness of the semiconductor substrate. 2. The semiconductor manufacturing apparatus according to claim 1, wherein the distance between the first wirings on the surface portion is selected to be at least 1 Z 2 or less.
PCT/JP1991/000040 1990-01-18 1991-01-17 Method of producing semiconductor devices WO1991011023A1 (en)

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Publication number Priority date Publication date Assignee Title
JPS6388829A (en) * 1986-10-01 1988-04-19 Matsushita Electric Ind Co Ltd Vapor growth method
JPS63192239A (en) * 1987-02-05 1988-08-09 Fujitsu Ltd Manufacture of semiconductor device
JPS6476727A (en) * 1987-09-17 1989-03-22 Nec Corp Manufacture of semiconductor device

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Publication number Priority date Publication date Assignee Title
JPS6388829A (en) * 1986-10-01 1988-04-19 Matsushita Electric Ind Co Ltd Vapor growth method
JPS63192239A (en) * 1987-02-05 1988-08-09 Fujitsu Ltd Manufacture of semiconductor device
JPS6476727A (en) * 1987-09-17 1989-03-22 Nec Corp Manufacture of semiconductor device

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