JP3371576B2 - Manufacturing method of semiconductor integrated circuit device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor integrated circuit.

[0002]

2. Description of the Related Art A semiconductor integrated circuit such as an ASIC (Appl
In recent years, high-density integration of circuits has been attempted in IC (Specification IC) and the like, and accordingly, a multi-layer wiring structure in which a plurality of wiring layers are laminated via an interlayer insulating layer is adopted. For example, in the case where the minimum pattern width is 0.35 μm (so-called 0.35 μm rule), it is required to have a multilayer wiring of 3 to 4 layers.

With the increase in the number of wiring layers, the following characteristics are strongly required for the interlayer insulating layer interposed between the wiring layers. 1) The upper surface of the interlayer insulating layer should be as flat as possible so that the wiring layer formed on the interlayer insulating layer can be easily formed with high reliability. 2) In order to ensure the reliability of the wiring, the stress is reduced so that stress migration or the like is not induced in each wiring layer. 3) It has a mechanical strength that shows crack resistance against external force from a package such as a resin mold for a semiconductor integrated circuit. 4) It has a moisture blocking effect to prevent moisture from diffusing into a circuit element such as a transistor. 5) Reduce parasitic capacitance between wirings.

The reason for reducing the parasitic capacitance between the wirings will be described below. As the high density integration of the integrated circuit is attempted, the distance between the wirings is reduced and the wiring layers are multilayered, resulting in an increase in the parasitic capacitance between the wirings. When the parasitic capacitance between the wirings increases, the delay of the circuit operation, that is, the speeding up of the integrated circuit is hindered. Further, crosstalk between wirings becomes a problem.

However, it is difficult to satisfy all of the many performance requirements described above in the interlayer insulating layer. Normally, SiO ₂ (dielectric constant 3.8) is used as the interlayer insulating layer, but instead of this, in particular, in order to reduce the parasitic capacitance between wirings, a material having a low dielectric constant is used. In the case of forming a film, a substance that sufficiently satisfies the above-mentioned other properties has not been proposed yet. For example, inorganic low dielectric constant materials such as boron nitride (BN) are mechanically brittle,
Amorphous Teflon (Teflon is a registered trademark) and organic SOG
Organic low dielectric constant materials such as (Spin on glass) are not only mechanically weak, but also have a high water content.

[0006]

As described above, in the conventional structure, even if an attempt is made to reduce the dielectric constant of the interlayer insulating layer,
There is a disadvantage that the mechanical strength of the material (for example, creep strength) is insufficient and it cannot be realized.

The present invention is intended to improve such inconvenience, and a semiconductor integrated circuit realizing a low effective relative dielectric constant of an interlayer insulating layer, that is, a substantial reduction of the dielectric constant of the interlayer insulating layer.
The manufacturing method is proposed.

[0008]

That is, in the present invention, fine voids are formed in the interlayer insulating layer.

[0009]

[0010]

[0011]

[0012]

[0013]

The first aspect of the present invention is a method for manufacturing a semiconductor integrated circuit device having a multilayer wiring structure in which a _second wiring layer L ₂ is laminated on at least a first wiring layer L ₁ with an interlayer insulating layer 20 interposed therebetween. in the step of forming the interlayer insulating layer having at least a first wiring layer L ₁ of the wire between the step of forming the microvoids insulating layer 2 having minute voids 2g covers the first wiring layer L ₁ above, interlayer A step of forming a contact hole in the insulating layer 20 at a position where the first wiring layer L ₁ and the second wiring layer L ₂ are electrically contacted;
Of the second wiring layer L ₁ by making electrical contact with the wiring layer L ₁ of
_A target semiconductor integrated circuit device is obtained by taking the step of forming ₂ . Furthermore, the step of forming the fine void insulating layer 2
The process of forming a granular amorphous silicon layer and this
By repeating the oxidation process of fusing silicon.

A second aspect of the present invention is a step of forming an interlayer insulating layer.
A step of forming a dense base insulating layer 1 deposited on the first wiring layer L ₁ along the entire surface, and on the base insulating layer 1, at least the first base insulating layer 1 Wiring layer L ₁
Between the wirings and the first wiring layer L ₁ and the step of forming the fine void insulating layer 2 having the fine voids 2g.

In the third aspect of the present invention, the step of forming the interlayer insulating layer 20 includes the step of forming the low dielectric constant insulating material layer 3 embedded in the fine voids 2g.

[0017]

[0018]

[0019]

[0020]

[0021]

[0022]

According to the present invention described above, since a large number of minute voids 2g are formed in the interlayer insulating layer 20, it is possible to reduce the substantial dielectric constant of the interlayer insulating layer 20, that is, the effective relative permittivity, and the wiring. The parasitic capacitance between them can be reduced.

By embedding a low dielectric constant material in the fine voids 2g, it is possible to reduce the effective relative permittivity while maintaining the mechanical strength.

A semiconductor integrated circuit will be described below with reference to the drawings.
An example of the manufacturing method will be described in detail.

Although not shown in the illustrated embodiment,
For example, a circuit element that constitutes an ASIC, for example, a MIS-FET (insulated gate type field effect transistor) or the like is formed on a semiconductor substrate, and the surface thereof is covered, for example, BPSG
(Boron-phosphorus-doped silicate glass) is coated, and the surface is planarized by reflow, and the planarization insulating layer 10 is applied. On this flattening insulating layer 10,
The first wiring layer L ₁ is formed, for example, by vapor-depositing an Al—Cu alloy on the entire surface and pattern etching by photolithography. A second wiring layer L ₂ is formed on the first wiring layer L ₁ via the interlayer insulating layer 20 by metal vapor deposition of Al—Cu and pattern etching by photolithography.

Example 1 As shown in FIG. 1, a base insulating layer 1 such as a SiO ₂ layer which will be a stop layer for etching later is formed on the first wiring layer L ₁ by using TEOS (tetraethyl orthosilicate) as a raw material. Is formed over the entire surface to a thickness of 100 nm by plasma CVD or the like.

The fine void insulating layer 2 having the fine voids 2g is formed on the base insulating layer 1. As a method of forming the fine void insulating layer 2, for example, siloxane-based SOG having excellent mechanical strength is formed on the entire surface, and the fine voids 2g are formed by etching by lithography. SOG is diluted with a solvent such as alcohol or acetone and the viscosity is adjusted to 2 to 4 cp at 25 ° C., and the viscosity is adjusted to 2000 to 3000 rpm.
Is spin-coated on the base insulating layer 1 to a thickness of 700 nm at a rotational speed of. Thereafter, this is fired in two stages at 200 ° C. for 30 minutes and then at 400 ° C. for 30 minutes. After that, plasma nitriding treatment is performed. This nitriding treatment is performed in a vertical plasma furnace at a gas temperature of 400 ° C. and NH ₃ flow rate of 500 s.
The plasma nitriding treatment is performed for 30 minutes by supplying in ccm.

The fine voids 2g are formed by using lithography, for example, photolithography or lithography by electron beam, and etching is performed by RIE (Reactive Ion Etching). A fine void 2g is formed. In this case, the etching is performed on the base insulating layer 1 to a depth of 10 to 20% of the thickness of the base insulating layer 1 (FIG. 1A).

Next, the fine voids 2 of the fine void insulating layer 2 are formed.
Fill low dielectric constant material in g. This filling is made of a low dielectric constant material such as organic S adjusted to have a low viscosity with a solvent such as alcohol
With OG, this fills the fine voids 2 g.
Then, the low dielectric constant material layer 3 is formed by performing two-step firing and plasma nitriding treatment in the same manner as in the formation of the fine void insulating layer 2 by SOG.

RIE, CMP (Chemical Mechanical Po
The upper part of the fine void insulating layer 2 in which the low dielectric constant material layer 3 is formed in the fine void 2g is planarized by an etch back method such as lishing (chemical mechanical polishing) (FIG. 1B). T on it
The interlayer insulating layer 20 is formed by fully forming the cap insulating layer 4 to a thickness of 100 nm by a plasma CVD method using EOS as a raw material.

The thus formed base insulating layer 1 and the fine voids 2g filled with the low dielectric constant material layer 3 are filled with the low void dielectric layer 2.
A contact hole 5 is formed in the inter-layer insulating layer 20 composed of the cap insulating layer 4 and the lower first wiring layer L ₁ and the upper second wiring layer L ₂ . The formation of the contact hole 5 is not shown, for example, but first, a photoresist is used, for example, to form a mask in which an opening is formed in a portion where the contact hole 5 is formed by photolithography, and a mask is formed by RIE through the opening of the mask. Performed by isotropic etching. In this case, after forming the contact hole 5 as needed, the side wall 6 made of an insulating film is formed on the inner side wall of the contact hole 5. The side wall 6 is formed by a well-known method, that is, by depositing an insulating film such as SiO _{2 on} the inner side surface of the contact hole 5 with good coverage by a CVD method and then performing etching back by anisotropic etching. it can.

After that, the first through the contact hole 5
A second wiring layer L ₂ is formed on the interlayer insulating layer 20 by electrically contacting a predetermined portion of the wiring layer L ₁ . The second formation of the wiring layer L ₂ may, for example, can be applied entirely deposited and pattern etching by photolithography Al-Cu (Fig. 1C).

According to this method, the fine void insulating layer 2 is made of SOG having a high mechanical strength, and the fine voids 2g are filled with SOG having a low mechanical strength but a low dielectric constant. It is possible to sufficiently lower the effective relative permittivity of the interlayer insulating layer 20 as a whole while maintaining the mechanical strength.

Further, as described above, when the sidewall 6 is formed on the inner side surface of the contact hole 5, it has the effect of smoothing the shoulder portion of the contact hole 5, and therefore the shoulder of the contact hole 5 is formed. This has an effect of avoiding occurrence of so-called disconnection in the upper layer wiring, that is, the second wiring layer L ₂ in the portion.

In the above example, the two-layer structure of the first and second wiring layers L ₁ and L ₂ is used.
In the case of a multi-layered structure having more layers, it can be formed by repeating a series of operations such as the formation of the interlayer insulating layer 20, the formation of the contact hole 5 and the formation of the wiring layer.

Example 2 As shown in FIG. 2, a base insulating layer 1 such as a SiO ₂ layer was formed on the first wiring layer L ₁ by 100 nm in the same manner as in Example 1.
Is formed over the entire thickness.

The fine void insulating layer 2 is formed on the base insulating layer 1. In this example, the fine void insulating layer 2 is formed by a collection of hemispherical SiO ₂ particles 11. The formation of the fine void insulating layer 2 is as follows. A large number of hemispherical amorphous Si particles are formed on the base insulating layer 1 by a CVD method using polysilane such as Si ₂ H ₆ as a raw material. In this case, the substrate temperature is 610 ° C., the flow rate of Si ₂ H ₆ is ₆ sccm,
When CVD is performed for 25 seconds, a large number of hemispherical amorphous Si particles having an average particle diameter of 40 nm are formed. At this time, the fine voids 2g between the particles are about 1 nm. These hemispherical particles,
N ₂ O and N ₂ are 6 sc each at a substrate temperature of 400 ° C.
cm and 100 sccm, the pressure is 1 Torr,
A hemispherical SiO ₂ particle 11 is formed by performing a plasma oxidation process for 50 seconds with an energy of 0.5 kW (FIG. 2).
A).

Next, the fine voids 2g of the fine void insulating layer 2 are filled with the low dielectric constant material layer 3 and the fine void insulating layer 2 is formed.
Cover the surface of. As the low dielectric constant material layer 3, for example, an organic SOG adjusted to have a low viscosity with a solvent such as alcohol is used,
This is a fine void 2 between each of the hemispherical SiO ₂ particles 11.
g, and overlying it over the entire surface, and then at 30 ° C. at 30 ° C. as in Example 1.
For 2 minutes and then plasma nitriding at 400 ° C. for 30 minutes to planarize the upper part (FIG. 2B).

A cap insulating layer 4 is formed on the low dielectric constant material layer 3 by a plasma CVD method using TEOS as a raw material.
The interlayer insulating layer 20 is formed by forming the entire surface to a thickness of nm.

In the interlayer insulating layer 20 thus formed, a contact hole 5 for electrically contacting the lower first wiring layer L ₁ and the upper second wiring layer L ₂ is formed as in the first embodiment. . If necessary, contact holes 5
A side wall 6 made of an insulating film is formed on the inner side wall of the same as in the first embodiment. Then, the second wiring layer L ₂ is formed on the interlayer insulating layer 20 by electrically contacting a predetermined portion of the first wiring layer L ₁ through the contact hole 5.

In the above example, the two-layer structure of the first and second wiring layers L ₁ and L ₂ is used.
In the case of a multi-layer laminated structure having more layers, it can be formed by repeating the above-described series of operations of forming the interlayer insulating layer 20, forming the contact hole 5, and forming the wiring layer and the like.

Example 3 As shown in FIG. 3, a base insulating layer 1 such as a SiO ₂ layer was formed on the first wiring layer L ₁ by 100 nm as in Example 1.
Is formed over the entire thickness.

A fine void insulating layer 2 is formed on the underlying insulating layer 1.
To achieve. In this example, the microvoid insulating layer 2 is formed into a hemispherical shape.
SiO₂Formed by stacking multiple layers of particles 11
It The formation of the fine void insulating layer 2 is as follows. under
Si on the ground insulation layer 1₂H₆Made from polysilane such as
Many hemispherical amorphous Si particles are formed by the CVD method etc.
To do. Si at substrate temperature of 590 ° C₂H₆Flow rate of 6 sccm
When CVD is performed for 25 seconds, a hemisphere with an average particle size of 40 nm
A large number of amorphous Si particles are formed. At this time SiO₂
Voids between particles, that is, 2 g of fine voids, are about 1 nm.
The hemispherical particles were subjected to plasma oxidation treatment in the same manner as in Example 2.
Hemispherical SiO ₂Form a layer of particles 11.

[0044] over the layer of SiO ₂ particles 11 hemispherical, amorphous Si particles were formed in a large number in the same way, by plasma oxidation process, the second layer of hemispherical SiO ₂ particles 11
To form a layer of. This is repeated until the thickness of the fine void insulating layer 2 becomes necessary to form the fine void insulating layer 2 in which a large number of hemispherical SiO ₂ particles 11 are formed (FIG. 3A).

The interlayer insulating layer 20 is formed by flattening the upper part of the fine void insulating layer 2 and forming the cap insulating layer 4 on the entire surface to a thickness of 100 nm by plasma CVD or the like using TEOS as a raw material. Form.

The interlayer insulating layer 20 composed of the base insulating layer 1, the fine void insulating layer 2 and the cap insulating layer 4 thus formed.
Then, a contact hole 5 for contacting the first wiring layer L ₁ and the second wiring layer L ₂ is formed in the same manner as in the first embodiment. Also in this case, after forming the contact hole 5, the side wall 6 made of an insulating film is formed on the inner side wall of the contact hole 5 if necessary. Through the contact hole 5, a contact portion of the wiring is formed on the first wiring layer L ₁ , and further on the interlayer insulating layer 2, the second wiring layer L _{2 is formed.}
Are formed (FIG. 3B).

In the above example, the two-layer structure of the first and second wiring layers L ₁ and L ₂ is used.
In the case of a multi-layered structure having more layers, it can be formed by repeating a series of operations such as the formation of the interlayer insulating layer 20, the formation of the contact hole 5 and the formation of the wiring layer.

Example 4 As shown in FIG. 4, a base insulating layer 1 such as a SiO ₂ layer was formed on the first wiring layer L ₁ by SiH ₄ / N ₂ O system bias-ECR (Electron Cyclotron Resonance) CVD. Then, the entire surface is formed to a thickness of 100 nm by the method or the like. At this time, the base insulating layer 1 with low stress and good coverage is formed.

The fine void insulating layer 2 is formed on the base insulating layer 1. In this example, a porous insulating layer is formed as the fine void insulating layer 2. The formation of the fine void insulating layer 2 is as follows. SiH ₄ / N as with the base insulating layer 1
_{Although a 2} O-based bias-ECR CVD method or the like is used, in this case, the DC bias voltage is increased to form a porous insulating layer.

Again, the DC bias voltage is set to the same low value as when forming the base insulating layer 1, and the bias-ECR CVD is performed.
Then, the cap insulating layer 4 is entirely formed on the fine void insulating layer 2 made of a porous SiO ₂ layer (FIG. 4A).

The upper surface is flattened, and if necessary, a cap insulating layer 4 having a thickness of 100 nm is formed on the entire surface by plasma CVD or the like using TEOS as a raw material. Thereby, the interlayer insulating layer 20 is formed.

The first wiring layer L ₁ and the second wiring layer L ₂ are contacted with the interlayer insulating layer 20 composed of the base insulating layer 1, the porous fine void insulating layer 2 and the cap insulating layer 4 thus formed. The contact hole 5 is formed in the same manner as in the first embodiment. Also in this case, after forming the contact hole 5 as needed, the sidewall 6 made of an insulating film is formed on the inner sidewall of the contact hole 5. Through the contact hole 5, a wiring contact portion is formed on the first wiring layer L ₁ , and a second wiring layer L ₂ is further formed on the interlayer insulating layer 2 (FIG. 4B).

In the above example, the two-layer structure of the first and second wiring layers L ₁ and L ₂ is used.
In the case of a multi-layered structure having more layers, it can be formed by repeating a series of operations such as the formation of the interlayer insulating layer 20, the formation of the contact hole 5 and the formation of the wiring layer.

Example 5 In this example, an insulating layer having poor coverage is laminated, and a fine cavity is formed especially between narrow wirings, and then flattening is etched back to open the upper portion of the cavity. To form a microscopic void 2g, and the microscopic void 2g is filled with a low dielectric constant material. Further, in this example, formation of the base insulating layer is not particularly necessary.

This coverage will be described. Now, as shown in FIG. 7, in the case of depositing a layer on an uneven surface, the thickness D at the maximum deposition thickness and the thickness a at the minimum deposition thickness are: The value is called coverage.
Under the same deposition conditions, as the width of the recess becomes narrower, the coverage value becomes smaller, that is, worse.

[0056] on the first wiring layer L _1, the insulating layer 12 made of the coverage bad example PSG film (phosphosilicate glass), in an atmosphere of _{SiH 4 · PH 4 · N 2} · O 2 40
Under the condition of 0 ° C., the first wiring layer is entirely formed to have a thickness of 700 nm. At this time, cavities due to poor coverage, that is, minute voids 2g are formed above the narrow wirings of the first wiring layer L ₁ (FIG. 5A).

In order to planarize the insulating layer 12 on the insulating layer 12, a planarizing insulating layer such as SiO ₂ is formed to a thickness of 100 nm by a plasma CVD method using, for example, TEOS as a raw material. In addition, 700 by RIE, CMP, etc.
Etch back to a thickness of nm to planarize the upper portion of the insulating layer 12 and open the cavities in the insulating layer 12, that is, the minute voids 2g (FIG. 5B). Thus, the fine void insulating layer 2 having the fine voids 2g is formed.

A low dielectric constant polymer such as amorphous Teflon (Teflon is a registered trademark) (dielectric constant 1.9) is spin-coated to fill 2 g of the above-mentioned fine voids. Thereafter, as in Example 1, the low dielectric constant material layer 3 is formed by performing two-step firing and plasma nitriding at 200 ° C. for 30 minutes and subsequently at 400 ° C. for 30 minutes (FIG. 5).
C).

Next, the low dielectric constant polymer covering the fine void insulating layer 2 is removed by etching, and RIE and CM are performed.
A method such as P is used to flatten the upper portion of the fine void insulating layer 2 in which the low dielectric constant material layer 3 is formed in the fine void 2g. T on it
The interlayer insulating layer 20 is formed by fully forming the cap insulating layer 4 to a thickness of 100 nm by plasma CVD method using EOS as a raw material (FIG. 5D).

The first wiring layer L ₁ and the second wiring layer L ₂ are contacted with the interlayer insulating layer 20 composed of the base insulating layer 1, the porous fine void insulating layer 2 and the cap insulating layer 4 thus formed. The contact hole 5 is formed in the same manner as in the first embodiment. Also in this case, after forming the contact hole 5 as necessary, the sidewall 6 made of an insulating film is formed on the inner wall of the contact hole 5. Through the contact hole 5, a wiring contact portion is formed on the first wiring layer L ₁ , and further a second wiring layer L ₂ is formed on the interlayer insulating layer 2.

In the above example, the two-layer structure of the first and second wiring layers L ₁ and L ₂ is used.
In the case of a multi-layered structure having more layers, it can be formed by repeating a series of operations such as the formation of the interlayer insulating layer 20, the formation of the contact hole 5 and the formation of the wiring layer.

Example 6 In this example, the fine void insulating layer 2 having the voids, that is, the fine voids 2g is formed in the same manner as in Example 5, but the voids are kept closed when the flattening and etching back is performed, and the fine void insulation is performed. Layer. An insulating layer 12 having poor coverage is formed on the first wiring layer L _{1 in} the same manner as in Example 5 to have a thickness of 700 nm.
Over the first wiring layer to cover the first wiring layer. At this time, a cavity is formed above the narrow wiring of the first wiring layer L ₁ (FIG. 6A).

In order to planarize the insulating layer 12 on the insulating layer 12, a planarizing insulating layer is formed to a thickness of 100 nm by a plasma CVD method using, for example, TEOS as a raw material. Furthermore, the insulating layer 12 is etched back by a method such as RIE or CMP to a thickness that does not open the cavity in the insulating layer 12.
Flatten the top of. In this way, the fine void insulating layer 2 having the fine voids 2g formed by the above-mentioned cavities is formed (FIG. 6B).

A cap insulating layer 4 of 100 n is formed on the fine void insulating layer 2 by a plasma CVD method using TEOS as a raw material.
By forming the entire surface to a thickness of m, the interlayer insulating layer 2
0 (FIG. 6C).

The first wiring layer L ₁ and the second wiring layer L ₂ are brought into contact with the interlayer insulating layer 20 composed of the base insulating layer 1, the porous fine void insulating layer 2 and the cap insulating layer 4 thus formed. The contact hole 5 is formed in the same manner as in the first embodiment. Also in this case, after forming the contact hole 5 as necessary, the sidewall 6 made of an insulating film is formed on the inner wall of the contact hole 5. Through the contact hole 5, a wiring contact portion is formed on the first wiring layer L ₁ , and further a second wiring layer L ₂ is formed on the interlayer insulating layer 2.

In the above example, the two-layer structure of the first and second wiring layers L ₁ and L ₂ is used.
In the case of a multi-layered structure having more layers, it can be formed by repeating a series of operations such as the formation of the interlayer insulating layer 20, the formation of the contact hole 5 and the formation of the wiring layer.

As described above, since the fine voids 2g are formed in the interlayer insulating layer 20 between the wirings and the fine voids 2g are filled with the low dielectric constant material or are left as the fine voids 2g, the space between the wirings is kept. The parasitic capacitance can be reduced. The parasitic capacitance between the wirings is inversely proportional to the spacing between the wirings and is proportional to the dielectric constant of the insulating layer. The dielectric constant of the insulating layer is determined by the material of the insulating layer. For example, in a semiconductor integrated circuit, SiO ₂ used as an interlayer insulating layer or the like is about 3.8, and gas is about 1.01. Since the part of the fine void 2g is filled with gas, the dielectric constant and the capacitance are about 1 /
4. In the manufacturing method of the above-mentioned example, the dielectric constant can be reduced by 10 to 40% from 3.8 of SiO ₂ .

The portion other than the fine voids 2g is made of a material having sufficient mechanical strength, and even if a low dielectric constant material having a relatively low mechanical strength is put in the fine voids 2g, the interlayer insulating layer 2
It has the necessary strength as 0. Regarding the content of water and the absorption of water as well, it is difficult for the portions other than the fine voids 2g to absorb water in the same manner, so that the interlayer insulating layer 20 has a property of blocking water.

In the above-mentioned fine void insulating layer 2, when the fine void 2g is filled with a low dielectric constant material or is closed, the cap insulating layer is not always necessary, while the fine void is opened. If left as it is, a cap insulating layer is required in order to prevent penetration and the like during formation of the upper wiring layer.

If the fifth and sixth embodiments are carried out,
A material with poor coverage can be used for the interlayer insulating layer, which increases the degree of freedom in material selection. Further, when forming a cavity, that is, a minute void by utilizing the effect of low coverage as described above, there is an advantage that the cavity is surely formed in a portion where the space between wirings is narrow and the occurrence of parasitic capacitance is a problem. is there.

The above-described embodiments are examples of the present invention, and various other configurations and manufacturing conditions can be adopted without departing from the scope of the present invention.

[0072]

According to the present invention described above, in a semiconductor integrated circuit device having a multi-layer wiring structure, a fine void is provided in the interlayer insulating layer and the dielectric constant in the fine void is lowered to reduce the entire interlayer insulating layer. The effective permittivity can be lowered, the permittivity between wirings can be lowered, and the parasitic capacitance can be lowered. Therefore, when the value of the capacitance is determined in the design of the circuit, the thickness of the interlayer insulating layer can be made thinner than before, and the aspect ratio (hole width / hole depth) of the contact portion can be reduced.

By reducing the parasitic capacitance between wirings by the manufacturing method of the present invention, a high-density integration of the semiconductor integrated circuit device described at the beginning allows a multi-layer wiring structure, and
By reducing the distance between the wirings, the parasitic capacitance between the wirings increases and the inconvenience that the line delay time increases can be improved. Since the delay time of the operation of the circuit can be reduced and the operation can be speeded up, higher density integration is possible.

Since the manufacturing method of the present invention is a combination of conventional processes, stable manufacturing can be carried out without the need for new manufacturing equipment. Further, the above effects can be easily realized without complicating the process as compared with the conventional manufacturing method.

Further, regardless of whether the material of the interlayer insulating layer has good coverage or poor coverage, the manufacturing method can be adopted according to each of them, so that the degree of freedom in selecting the material and the degree of freedom in the manufacturing process are expanded. .

[0076]

[Brief description of drawings]

FIG. 1 is a process diagram of a manufacturing method of a first embodiment of a semiconductor integrated circuit device . A is a sectional view of the one step. B is a sectional view of the next one step. C is a cross-sectional view at the time when the second wiring layer is formed.

FIG. 2 is a process drawing of the manufacturing method of Example 2 of the semiconductor integrated circuit device . A is a sectional view of the one step. B is a sectional view of the next one step. C is a cross-sectional view at the time when the second wiring layer is formed.

FIG. 3 is a process drawing of the manufacturing method of Example 3 of the semiconductor integrated circuit device . A is a sectional view of the one step. 3B is a cross-sectional view at the time when the second wiring layer is formed.

FIG. 4 is a process drawing of the manufacturing method of Example 4 of the semiconductor integrated circuit device . A is a sectional view of the one step. 3B is a cross-sectional view at the time when the second wiring layer is formed.

FIG. 5 is a process drawing of the manufacturing method of Example 5 of the semiconductor integrated circuit device . A is a sectional view of the one step. B is a sectional view of the next one step. C is a cross-sectional view of the next one step. D is a cross-sectional view at the time when the interlayer insulating layer is formed.

FIG. 6 is a process drawing of the manufacturing method of Example 6 of the semiconductor integrated circuit device . A is a sectional view of the one step. B is a sectional view of the next one step. C is a cross-sectional view at the time when the interlayer insulating layer is formed.

FIG. 7 is a cross-sectional view illustrating coverage.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Base insulating layer 2 Micro void insulating layer 2g Micro void 3 Low dielectric constant material layer 4 Cap insulating layer 5 Contact hole 6 Sidewall 10 Flattening insulating layer 11 Hemispherical insulating layer 12 Insulating layer 20 Interlayer insulating layer L ₁ First Wiring layer L ₂ Second wiring layer

Continuation of the front page (56) Reference JP-A-5-283542 (JP, A) JP-A-4-311059 (JP, A) JP-A-63-208248 (JP, A) JP-A-3-156929 (JP , A) JP 63-7650 (JP, A) JP 63-318752 (JP, A) JP 6-77209 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB) Name) H01L 21/3205-21/3213 H01L 21/768

Claims (3)

(57) [Claims] 1. A method of manufacturing a semiconductor integrated circuit device having a multi-layer wiring structure in which a second wiring layer is laminated on at least a first wiring layer with an interlayer insulating layer interposed between the wirings of the first wiring layer. A step of forming an interlayer insulating layer having at least a step of forming a fine void insulating layer having a fine void covering the space and the first wiring layer, and the first wiring layer and the second layer of the interlayer insulating layer. A step of forming a contact hole at a position electrically contacting the wiring layer, and a step of electrically contacting the first wiring layer through the contact hole to form the second wiring layer.
Taken, the process of forming the microvoids insulating layers, grain shape amorphous sheet
Recon layer formation process and oxidation of the amorphous silicon
A method of manufacturing a semiconductor integrated circuit device characterized by repeating the process. 2. The step of forming the fine void insulating layer, the step of forming a dense underlying insulating layer deposited along the entire surface on the first wiring layer, and the step of forming the dense underlying insulating layer on the underlying insulating layer. At least between the wirings of the first wiring layer on the base insulating layer and the first wiring layer
2. The method for manufacturing a semiconductor integrated circuit device according to claim 1 , further comprising the step of forming a fine void insulating layer having a fine void covering the wiring layer of FIG. 3. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the step of forming the interlayer insulating layer includes the step of forming a low dielectric constant insulating material filling the fine voids.