JPS6159748A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain sufficient step coverage by setting the relation between an interval (a) of lower layer wiring and thickness (b) of insulation film which directly covers such wiring to a-2b approx.<0.7mum or a-2b approx.>2.0mum in such a case where the stepped portion is alleviated by coating a part of interlayer insulation film of multilayer wirings with silicon oxide resin film and sintering this film. CONSTITUTION:A lower layer metal wiring 3 and a first insulation film 14 which directly covers this wiring are formed on a silicon substrate 1 and silicon oxide film 2. Next, the surface is coated with silicon oxide resin and is then sintered for flattening the insulation layer, and a silicon oxide film 5 is formed thereon and moreover a second interlayer insulation film 6 is formed and an upper layer metal wiring 7 is formed thereon. In this case, the relation between the interval (a) of lower layer wiring and thickness (b) of first insulation film is set as a-2b approx.<0.7mum, or a-2b approx.>2.0mum. Thereby, the step coverage can be im proved and disconnection of upper layer wiring can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Application on Industrial Structures The present invention relates to a semiconductor device having a multilayer wiring structure, and more particularly, to a semiconductor device having a silicon oxide resin film coated on a part of an interlayer insulating film of the multilayer wiring and sintered. The present invention relates to a semiconductor device using a silicon film.

Conventionally, in multilayer wiring of semiconductor devices, a structure has been adopted in which a silicon oxide resin film is used as part of an interlayer insulating film in order to prevent disconnection of upper layer wiring and to obtain sufficient step coverage. ing. This structure includes a two-layer structure consisting of a first insulating film and a silicon oxide resin film coated thereon, or a two-layer structure consisting of a first insulating film and a silicon oxide resin film coated on the first insulating film, or a silicon oxide resin film coated on the first insulating film and a second insulating film. One example is a three-layer structure with a sandwich structure sandwiching a silicon oxide film made of sintered silicon oxide. In particular, if it is desired to maintain a high degree of vacuum during subsequent vapor deposition or sputtering of upper layer wiring, the latter sandwich-inch structure is generally used.

As the degree of integration increases, the wiring spacing decreases,
Due to an increase in the thickness of the lower layer wiring, etc., the steep shape of the stepped portion of the R film may not be sufficiently alleviated by the applied silicon oxide resin film alone. That is, as shown in FIG. 3, the lower interconnections 3 formed on the silicon substrate 1 and the thick silicon oxide film 2 obtained by oxidizing the surface thereof are spaced at intervals al and a! are arranged in Due to the formation of multilayer wiring on such a board, the first glabella? 3. A rim film 4 is grown over the entire surface, and a silicon oxide resin film is applied to smooth the shape. The silicon oxide resin film is baked and hardened by heat treatment at 400° C. or higher, and becomes the silicon oxide film 5. Subsequently, as mentioned above, in order to maintain a high degree of vacuum during vapor deposition or sputtering of the upper wiring layer, the second glabella insulating film 6 is further grown on the entire surface, and then the metal for the upper wiring layer 7 (generally aluminum) is deposited or sputtered.

C0 Problems to be Solved by the Invention As mentioned above, even if a silicon oxide resin film is used as a part of the interlayer insulating film, if the spacing between the lower layer wiring becomes narrower, the step coverage of the upper layer wiring will deteriorate. However, this is cited as a problem that requires resolution.

Technical Means for Solving Problems 21 In order to solve the above-mentioned problems, the present invention has a narrow lower layer wiring interval 3 and an insulating layer that directly covers the lower layer wiring. & film thickness b,
The relationship is a-2b≦Q, 7pm, or a-2b≧λOμm.

E, Example Next, the present invention will be explained by examples.

FIG. 1 is a sectional view of an embodiment of the present invention. Referring to the figure, when comparing this with the conventional example shown in FIG. 3, a silicon substrate 1, silicon oxide [2, lower layer wiring 3, - silicon oxide film 5 formed by sintering a monosilicon oxide resin film, The second interlayer insulating film 6 and the upper wiring layer 7 are the same. However, the conventional first interlayer insulating film 4
In the present invention, the thickness bl of the first interlayer insulating film 14 is
The thickness of the lower layer wiring 3.3 is increased and the distance a from the lower layer wiring 3.3 satisfies the relationship (a-2b)≦0.7 μm.

The reason why the step coverage of the upper layer wiring 7 is improved by satisfying such a relationship will be explained below. That is, FIG. 4 shows 1. This is a graph of the investigation results with (a-2b) on the horizontal axis and step coverage on the vertical axis.From this figure, if (a-2b') is about 2 μm or more, the step coverage is 60% or more. Although it has coverage,
If it becomes smaller than that, the step coverage deteriorates rapidly, and in particular, around (a-2b) = takes shape. In such a state, a slight abnormality in the shape of the underlying layer may lead to disconnection of the upper layer wiring, and more importantly, there is a problem from the viewpoint of reliability. However, when (a-zb) becomes even smaller, less than 1 μm, especially less than about 0.7 μm, a rapid improvement in step coverage is observed.

FIG. 2 is a cross-sectional view of an embodiment of the present invention having a through hole. That is, as shown in FIG.
2b) The lower layer wiring interval a and the first
Even if the interlayer insulating film thickness is selected as follows, when forming the pier hole, the first. Due to the difference in etching rate between the second interlayer insulating film 14.6 and the silicon oxide film 5 obtained by sintering the silicon oxide resin film, step coverage of the upper wiring layer 7 at the peer hole portion 8 deteriorates. There are cases. Therefore, in order to prevent such defects, the first interlayer insulation a
It is necessary to limit the thickness b of K14. That means,
The distance a between the lower wirings 3 is also limited by the relationship (a-2b), and the range of practical use is greatly narrowed. Therefore, %(”-2b)≦0.7μm
The lower layer wiring layer spacing a and the first interlayer insulating film thickness are selected to satisfy The silicon oxide film 5 obtained by sintering the base resin film is removed, leaving the silicon oxide film 5a only in the recesses between the lower wiring layers. As shown in the figure, the silicon oxide film 5 is formed on the flat part.
Due to the absence of this, restrictions on the opening and timing of the peer hole 8 are removed, and good step coverage of the upper wiring layer 7 can be obtained.

In addition, in the embodiment of the present invention, after the lower layer wiring.

Although the example of the fourth wiring layer and the second wiring layer is used as the upper wiring layer, this relationship is similar to the second wiring layer, the third wiring layer, and two such consecutive wiring layers.

The same applies to the wiring layers, and is not particularly limited to the first wiring layer and the second M wiring layer.

Effects of the Invention As described above, according to the present invention, when the interlayer insulating film that directly covers the lower layer wiring is constant and the lower layer wiring has a certain interval, even if a silicon oxide resin film is used, the upper layer wiring This saves the step coverage from rapidly deteriorating.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of one embodiment of the present invention, FIG. 2 is a cross-sectional view of another embodiment of the present invention, FIG. 3 is a cross-sectional view of a conventional semiconductor device, and FIG. 4 is a detailed diagram of the present invention. This is a graph for explanation. DESCRIPTION OF SYMBOLS 1...Silicon substrate, 2...Silicon oxide film, 3...Lower wiring, 4, 14...First interlayer insulating film, 5 ... Sintered silicon oxide film of silicon oxide resin film, 5a ... Remaining sintered silicon oxide film, 6 ... - Second interlayer insulating film, 7...
Upper layer arrangement i/i)! 1.8...Pier Hall. Figure 1 Muscle 2 Figure 3 61,,! ; lO/, A; 2. θ (
7m) (0-2b) Figure 4

Claims (2)

[Claims] 1. A semiconductor with a multilayer wiring having an interlayer insulation film including an insulation film directly covering the lower wiring and a silicon oxide film coated with a silicon oxide resin film and sintered to soften the stepped portion of the insulation film. In the device, when the interval between the lower layer wirings is a and the thickness of the insulating film directly covering the lower layer wirings is b, then a-2b 0.7 μm, or a-2b 2.
A semiconductor device characterized by having a diameter of 0 μm. 2. 2. The semiconductor device according to claim 1, wherein the silicon oxide film obtained by sintering the silicon oxide resin film is left only in the recesses between the lower wirings.