JPH03212958A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH03212958A JPH03212958A JP916390A JP916390A JPH03212958A JP H03212958 A JPH03212958 A JP H03212958A JP 916390 A JP916390 A JP 916390A JP 916390 A JP916390 A JP 916390A JP H03212958 A JPH03212958 A JP H03212958A
- Authority
- JP
- Japan
- Prior art keywords
- film
- insulating film
- wiring
- bpsg
- deposited
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 238000000034 method Methods 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000010438 heat treatment Methods 0.000 abstract description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 8
- 229920005591 polysilicon Polymers 0.000 abstract description 8
- 239000005380 borophosphosilicate glass Substances 0.000 abstract description 5
- 238000005137 deposition process Methods 0.000 abstract 1
- 239000002184 metal Substances 0.000 description 12
- 239000010410 layer Substances 0.000 description 8
- 239000011229 interlayer Substances 0.000 description 7
- 238000009413 insulation Methods 0.000 description 6
- 239000005360 phosphosilicate glass Substances 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- XHXFXVLFKHQFAL-UHFFFAOYSA-N phosphoryl trichloride Chemical compound ClP(Cl)(Cl)=O XHXFXVLFKHQFAL-UHFFFAOYSA-N 0.000 description 4
- 229910021332 silicide Inorganic materials 0.000 description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 150000003839 salts Chemical class 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の目的１
（産業上の利用分野）
本発明は、半導体装置の製造方法に関するもので、特に
積層して形成される導体層（多層配線）間の眉間絶縁膜
の平坦化方法の改良に係るものである。Detailed Description of the Invention [Objective of the Invention 1 (Industrial Field of Application) The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device, and in particular, a method for manufacturing a glabellar insulating film between conductor layers (multilayer wiring) formed by stacking. The present invention relates to an improvement of a flattening method.
（従来の技術）
半導体装置の高集積化、高密度化等により、配線の多層
化は、必然の技術である。 多層配線構造番実現するた
め、層間絶縁膜の表面を平坦化することは、信頼性の高
い多層配線を得るための必要条件である。(Prior Art) Multilayer wiring is an inevitable technology as semiconductor devices become more highly integrated and densely packed. In order to realize a multilayer wiring structure, flattening the surface of an interlayer insulating film is a necessary condition for obtaining a highly reliable multilayer wiring.
一般に眉間絶縁膜には、下層配線パターンにより生ずる
凹凸が存在している。 例えば第４図に示すように、半
導体基板１上に、ゲート酸化膜２、ポリシリコン膜（ゲ
ート電極Ｍ＞３、絶縁ＷＡ４及び高融点シリサイド膜５
からなる積層膜旦が形成されている。 この積層膜呈上
に、更に眉間絶縁ＷＡ６を−介し、金属配線Ｍ（図示な
し）を形成する場合、前記積層膜により金属配線膜形成
前に大きな段差が生じる。 この段差を緩和し、金属配
線膜の被覆性、加工性を向上させるため、例えば眉間絶
縁膜６としては、ＣＶＤ法によるＰＳＧ（リンケイ酸ガ
ラス）膜又はＢ Ｐ Ｓ Ｇ 、（ポロンリンゲイ酸ガ
ラス）膜を使用し、堆積後、例えば９００℃の熱処理に
よって、フロー（リフローと呼ばれることもある）させ
て、眉間絶縁膜（例えばＢＰＳＧ膜等で、平坦化用絶縁
膜と呼ぶこともある）６の表面を平坦化する工程が用い
られている。 この熱処理としては、水蒸気雰囲気や、
オキシ塩化リン（ＰＯＣＩ、）雰囲気中で行なうことで
、比較的低温でフローできることが知られており、使用
されている。Generally, the glabella insulating film has unevenness caused by the underlying wiring pattern. For example, as shown in FIG.
A laminated film plate consisting of the following is formed. When metal wiring M (not shown) is further formed on this laminated film via the glabellar insulation WA6, a large step is created by the laminated film before the metal wiring film is formed. In order to alleviate this difference in level and improve the coverage and processability of the metal wiring film, for example, as the glabella insulating film 6, a PSG (phosphosilicate glass) film or a BPSG (poron phosphorus silicate glass) film by CVD method is used. After deposition, the surface of the glabella insulating film (for example, BPSG film, etc., sometimes called a flattening insulating film) 6 is made to flow (sometimes called reflow) by heat treatment at 900°C, for example. A process of flattening the surface is used. This heat treatment can be carried out in a steam atmosphere,
It is known that phosphorus oxychloride (POCI) can flow at a relatively low temperature by being carried out in an atmosphere, and is used.
半導体装置の微細化に伴い、ポリシリコンＭ３及び金属
シリサイド膜５の配線は細く、又配線間隔は狭くなって
ゆくが、これらの上層に積層される金属配線の加工上の
要求から、金属配線形成前の眉間絶縁ＷＡ６の表面は、
従来と同様な平坦性、もしくは、それ以上の平坦性が要
求される。With the miniaturization of semiconductor devices, the interconnections of the polysilicon M3 and metal silicide film 5 are becoming thinner, and the interconnect spacing is becoming narrower. The surface of the previous glabellar insulation WA6 is
Flatness similar to or better than the conventional one is required.
しかしながら、従来技術では、所望の厚さの眉間絶縁膜
を、１回の工程で、前記積層膜旦の段差上に形成してい
るが、装置の微細化に伴う下地のポリシリコン膜３又は
金属シリサイド膜５の形状や眉間絶縁膜形成時の被覆性
の悪さにより、眉間絶縁ＩＩ！６内の下地配線間の段差
部に空隙ができたり、更に上層の金属配線と下地配線と
の短絡現象が発生することがあり、問題となっている。However, in the conventional technology, a glabella insulating film with a desired thickness is formed on the steps of the laminated film layer in a single process, but with the miniaturization of devices, the underlying polysilicon film 3 or metal Due to the shape of the silicide film 5 and poor coverage during formation of the glabellar insulating film, glabellar insulation II! There are problems in that gaps may be formed at the stepped portions between the underlying wirings in the 6th layer, and short-circuit phenomena may occur between the upper layer metal wiring and the underlying wiring.
この問題点について、第５図ないし第７図を参照して、
更に詳しく説明する。 第５図は、半導体基板１上にポ
リシリコンから成る疑似段差７を設け、眉間絶縁膜（Ｂ
ＰＳＧ膜）をＣＶＤ法により堆積した断面図である。
２つの段差７．７間に空隙８ができる。 第６図に示す
ように、この空隙８は、平坦化するための熱処理工程に
おいて、彫版、破裂し、眉間絶縁膜６に数μｍ径の穴９
を発生させる。 実際の半導体装置では、金属配線形成
後、その穴を通じて、金属シリサイド膜の配線と金属配
線とが短絡し、半導体装置の動作不良が発生するという
問題があり、半導体装置の微細化に伴い、この不良は増
加している。 又穴の発生に至らない場合でも、第７図
に示すように、平坦化された膜中に空洞１０が残り、半
導体装置の信頼性上好ましくない、 （発明が解決し
ようとする課題）
半導体装置の高集積化、ＦＲｍ化に伴い、多層配線構造
が多用され、眉間絶縁膜の平坦性が強く望まれている。Regarding this problem, please refer to Figures 5 to 7.
It will be explained in more detail. FIG. 5 shows that a pseudo step 7 made of polysilicon is provided on a semiconductor substrate 1, and a glabellar insulating film (B
FIG. 2 is a cross-sectional view of a PSG film deposited by a CVD method.
A gap 8 is created between the two steps 7.7. As shown in FIG. 6, this void 8 is engraved and ruptured during the heat treatment process for flattening, resulting in a hole 9 with a diameter of several μm in the glabella insulating film 6.
to occur. In actual semiconductor devices, there is a problem in that after the metal wiring is formed, the metal silicide film wiring and the metal wiring are short-circuited through the holes, resulting in malfunction of the semiconductor device. Defects are increasing. Even if holes do not occur, cavities 10 remain in the flattened film as shown in FIG. 7, which is unfavorable in terms of reliability of the semiconductor device. (Problems to be Solved by the Invention) Semiconductor Device With the trend toward higher integration and FRm, multilayer wiring structures are frequently used, and flatness of the glabella insulating film is strongly desired.
しかしこれまで述べたように、下地配線の幅も細く
、配線相互の間隔も狭くなり、従来技術の眉間絶縁膜で
は、下地配線と上層金属配線とが短絡したり、絶縁膜中
に空洞が残る等、半導体装置の信頼性を損なう問題があ
った。However, as mentioned above, the width of the underlying wiring is narrower, and the distance between the wirings is also narrower, and with the conventional technology's glabella insulating film, the underlying wiring and the upper layer metal wiring may short-circuit, or cavities may remain in the insulating film. There were problems such as impairing the reliability of semiconductor devices.
これらの問題は、眉間絶縁膜の形成時に空隙が発生する
ことが、根本的な原因である。The fundamental cause of these problems is the generation of voids during the formation of the glabellar insulating film.
本発明の目的は、半導体装置の微細化された配線上に、
眉間絶縁膜を形成するに際し、下地配線の配線間隔部の
絶縁膜中に、空隙が発生するのを防止しつつ眉間絶縁膜
を形成し、熱処理工程によって、平坦化された良好な絶
縁膜が得られる半導体装置の製造方法を提供することで
ある。An object of the present invention is to
When forming the glabellar insulating film, the glabellar insulating film is formed while preventing the generation of voids in the insulating film at the wiring spacing of the underlying wiring, and a good flattened insulating film is obtained by a heat treatment process. An object of the present invention is to provide a method for manufacturing a semiconductor device.
［発明の構成］
（課題を解決するための手段）
本発明の半導体装置の製造方法は、半導体基板の主表面
上に平坦化用絶縁膜（層間絶縁ＩＩＩ）を形成した後、
該絶縁膜をフロー（リフローと呼ばれれることもある）
して平坦化する行程において、該絶縁膜を形成する工程
と平坦化する工程とを連続して複数回繰り返し行うこと
を特徴とするものである。[Structure of the Invention] (Means for Solving the Problems) The method for manufacturing a semiconductor device of the present invention includes forming a planarizing insulating film (interlayer insulation III) on the main surface of a semiconductor substrate, and then forming a planarizing insulating film (interlayer insulation III).
Flow (sometimes called reflow) the insulating film
In the flattening process, the process of forming the insulating film and the flattening process are repeated a plurality of times in succession.
なお前記平坦化用絶縁膜としては、ＣＶＤ法により堆積
されたＰＳＧ （リンケイ酸ガラス）膜、ＢＰＳＧ（ボ
ロンリンケイ酸ガラス）膜、又はこれらの積層膜とする
ことが望ましい実施態様である。In a preferred embodiment, the flattening insulating film is a PSG (phosphosilicate glass) film, a BPSG (borophosphosilicate glass) film deposited by a CVD method, or a laminated film thereof.
（作用）
本発明は、半導体基板の主表面上、例えばゲート酸化膜
、導電性ポリシリコン膜、絶縁膜及び金属シリサイド膜
から成る積層膜等の下地配線が形成されている基板の主
表面上に、平坦な眉間絶縁膜を形成する工程において、
下地配線間の段差部に空隙のできない膜厚（例えば０．
７μｍ以下）の平坦化用絶縁膜を形成した後、熱処理工
程（例えば７００℃以上）にて該絶縁膜をフローして平
坦化し、下地の段差、形状を緩和する。 引き続いて、
更に空隙のできない膜厚（例えば合計膜厚で０．８μｍ
以上）の平坦化用絶縁膜を形成した後、熱処理工程によ
って平坦化する。 本発明は、このように平坦化用絶縁
膜を形成する工程と平坦化する工程とを繰り返し行ない
、所望の膜厚を有し、空隙のない平坦な眉間絶縁膜を形
成する製造方法である。(Function) The present invention provides a method for forming a substrate on the main surface of a semiconductor substrate, for example, on the main surface of a substrate on which underlying wiring such as a laminated film consisting of a gate oxide film, a conductive polysilicon film, an insulating film, and a metal silicide film is formed. , in the process of forming a flat glabellar insulating film,
The film thickness should be set so that there are no voids in the stepped portion between the underlying wiring (for example, 0.
After forming a flattening insulating film with a thickness of 7 μm or less, the insulating film is flowed and flattened in a heat treatment process (for example, at 700° C. or higher) to alleviate the step and shape of the underlying layer. Subsequently,
Furthermore, the film thickness should be 0.8 μm in total film thickness without voids (for example, 0.8 μm in total film thickness)
After forming the planarization insulating film (above), planarization is performed by a heat treatment process. The present invention is a manufacturing method for forming a flat glabellar insulating film having a desired thickness and having no voids by repeatedly performing the step of forming a flattening insulating film and the step of flattening as described above.
〈実施例）
本発明を行なうにあたって、試行結果の再現性等を考慮
して、半導体基板主面にポリシリコンから成る疑似段差
を設けたものを下地とし、この下地に、ＢＰＳＧからな
る平坦化用絶縁膜をＣＶＤ法によりｔｆｉ槓し、該絶縁
膜の膜厚や疑似段差の間隔等の条件を変えて試行を行な
った。<Example> In carrying out the present invention, in consideration of the reproducibility of trial results, etc., a pseudo step made of polysilicon was provided on the main surface of a semiconductor substrate was used as a base, and a planarization layer made of BPSG was used as a base. An insulating film was formed by TFI using the CVD method, and trials were conducted by changing conditions such as the thickness of the insulating film and the distance between the pseudo steps.
第２図はその一例で、半導体基板１上に、高さ０．８μ
ｍのポリシリコンからなる疑似段差（配線）７を設けた
下地に、ＢＰＳＧの平坦化用絶縁膜６をＣＶＤ法により
堆積させた断面図である。 同図は、平坦化用絶縁膜の
堆積膜厚しく下地の平坦部における厚さ、以下同様〉が
比較的薄く、２つの配線７．７上の堆積膜の最小間隔ｙ
が０より大きく、段差間に空隙を生じない場合を示す、
塩１ｉａ膜厚しが厚くなると、第５図に示すように空
隙ができる。 試行結果によれば、最小間隔ｙが０にな
った時点で空隙が発生すると考えてよい。FIG. 2 shows an example of this, in which a 0.8μ high layer is placed on the semiconductor substrate 1.
3 is a cross-sectional view showing a planarization insulating film 6 of BPSG deposited by CVD on a base provided with a pseudo step (wiring) 7 made of polysilicon with a thickness of m. In the same figure, the deposited film of the planarizing insulating film is thick and the thickness at the flat part of the base (hereinafter the same) is relatively thin, and the minimum distance y between the deposited films on the two wirings 7.
is larger than 0 and there is no gap between the steps,
When the salt 1ia film becomes thicker, voids are formed as shown in FIG. According to the trial results, it can be considered that a gap occurs when the minimum distance y becomes 0.
次に第２図において、配線７の幅Ｗ、配線間隔Ｘ及び平
坦化用絶縁膜の膜厚ｔを変えたときの堆積膜の最小間隔
ｙを測定した試行結果の一例を第３図に示す、 同図の
横軸は、配線間隔Ｘ（配線幅Ｗに等しい）で、０．８μ
■から１，６μｍまで変化させ、又縦軸は堆積後のＢＰ
ＳＧ膜の最小間隔ｙ （μｍ）の測定値である。 パラ
メータはＢＰＳＧ膜の堆積膜厚ｔで、直線Ａ、Ｂ及びＣ
はそれぞれｔ４ ＝０．２ μｌｌ 、 ｔａ ＝ｏ
、４ μｌｌ及びｔｃ＝０．７μｍの場合を示す、 な
お配線７の高さは０．８μｍである。 第３図で、縦軸
ｙの値が０になった時点で空隙が発生する。Next, in FIG. 2, an example of the trial results of measuring the minimum spacing y of the deposited film when changing the width W of the wiring 7, the wiring spacing X, and the film thickness t of the flattening insulating film is shown in FIG. , The horizontal axis of the figure is the wiring spacing X (equal to the wiring width W), which is 0.8μ
The vertical axis is the BP after deposition.
This is the measured value of the minimum distance y (μm) of the SG film. The parameter is the deposited film thickness t of the BPSG film, and the straight lines A, B, and C
are t4 = 0.2 μll and ta = o, respectively.
, 4 μll and tc=0.7 μm. Note that the height of the wiring 7 is 0.8 μm. In FIG. 3, a void occurs when the value of the vertical axis y becomes 0.
次に上記試行結果に基づき行なった本発明の一実施例に
ついて第１図を参照して説明する。 同図＜ａ ）は、
半導体基板１上に形成されたポリシリコン配線７（高さ
０，８μｍ、幅Ｗ及び間隔Ｘは１μｌ）を下地とし、空
隙のできない膜厚（例えば０．５μｌ）のＢＰＳＧ膜６
ａ全６ａしたときの断面図である。 ＢＰＳＧ膜の堆
積は公知の方法で、常圧ＣｖＤで反応ガス（Ｓｉ Ｈ，
＋Ｂ２Ｈ６モＰＨ，＋０２＋ （Ｎ２ ））を使用する
。 空隙のできないＢＰＳＧＪＩ！６ａの膜厚は、第３
図の試行結果を参照して決める。 次に同図（ｂ）に示
すように、熱処理を、例えばＮ２雰囲気中で９００℃、
２０分５行ない、ＢＰＳＧＭ６ａをフローシて平坦化さ
れたＢＰＳＧ膜６ｂが得られる。 ＢＰＳＧｇ６ｂには
空隙は存在しないが、しかしこれでは平坦性、絶縁性と
もに不十分である。 したがって眉間絶縁膜として十分
な膜厚になるまで、前記工程を繰り返す、 即ち同図（
Ｃ）に示すように、更にＢＰＳＧＷＡ６Ｃを空隙のでき
ない膜厚く例えば０．６μＩｌ）、ｔで堆積する。 次
に同図（ｄ ）に示すように、水蒸気雰囲気中で９００
’Ｃ１３０分の熱処理を行ない、ＢＰＳＧ膜６ｃ及び
６ｂをフローして平坦化されたＢＰＳＧＨ６ｄを得る。Next, an embodiment of the present invention based on the above trial results will be described with reference to FIG. The figure <a) is
A BPSG film 6 with a film thickness (for example, 0.5 μl) without voids is formed on a polysilicon wiring 7 (height: 0.8 μm, width W, and interval X: 1 μl) formed on a semiconductor substrate 1 as a base.
It is a cross-sectional view when all a is 6a. The BPSG film is deposited by a known method using reactive gases (SiH,
+B2H6moPH, +02+ (N2)) is used. BPSGJI with no gaps! The film thickness of 6a is the third
Decide by referring to the trial results shown in the figure. Next, as shown in FIG.
After 5 steps of 20 minutes, the BPSGM 6a is flowed to obtain a planarized BPSG film 6b. Although there are no voids in BPSGg6b, both flatness and insulation are insufficient. Therefore, the above steps are repeated until a film thickness sufficient for the glabella insulating film is obtained.
As shown in C), BPSGWA6C is further deposited to a thickness of, for example, 0.6 .mu.Il) without voids, and at a time of t. Next, as shown in the same figure (d), 900
A heat treatment for 130 minutes is performed to flow the BPSG films 6c and 6b to obtain a flattened BPSGH 6d.
このように平坦化用絶縁膜を堆積する工程と、熱処理に
より該絶縁膜を平坦化する工程とを、連続して２回、繰
り返して行ない、空隙を発生させずに、所望の膜厚及び
平坦性を持つ層間絶縁膜を得ることができる。The process of depositing the planarizing insulating film and the process of planarizing the insulating film by heat treatment are repeated twice in succession to achieve the desired film thickness and flatness without creating any voids. It is possible to obtain an interlayer insulating film with properties.
前記実施例では、半導体基板１上に疑似配線７を設けた
下地に、平坦化用絶縁膜を堆積、平坦化する例について
述べた。 前記実施例のデータに基づいて、例えば第４
図に示す実際の半導体装置の製造を行なった結果では、
前記実施例と同等の効果が得られた。In the embodiment described above, an example has been described in which a planarizing insulating film is deposited and planarized on the base on which the pseudo wiring 7 is provided on the semiconductor substrate 1. Based on the data of the above example, for example, the fourth
As a result of manufacturing the actual semiconductor device shown in the figure,
Effects equivalent to those of the previous example were obtained.
以上の説明では、−例として平坦化用絶縁膜に常圧ＣＶ
Ｄ法によるＢＰＳＧ膜を用いたが、常圧ＣＶＤ法による
ＰＳＧ膜やそれ以外の成膜方法（減圧ＣＶＤ、７”ラズ
７ＣＶＤ等）によるＢＰＳＧ膜又はＰＳＧ膜を用いても
良い、 又スピンオングラス等の平坦化用塗布膜を用い
ても同様な結果が得られる。 又、熱処理工程として上
述したＮ２、水蒸気に代えて、ＰＯＣｌ３、酸素等的の
雰囲気中で行なってもよいし、又熱処理工程として、ラ
ビッドアニール、高圧熱処理を用いる場合にも、本発明
は適用できる。 又工程の繰り返し回数についても、−
例として２回の場合を説明したが、微細化の程度、下地
段差の形状等の条件によっては、更に回数を増加させる
ことも可能である。In the above explanation, as an example, normal pressure CV is applied to the planarization insulating film.
Although a BPSG film formed by the D method was used, a PSG film formed by the normal pressure CVD method or a BPSG film formed by other film forming methods (low pressure CVD, 7"7" CVD, etc.) may also be used, or a spin-on glass film, etc. A similar result can be obtained by using a flattening coating film of The present invention can also be applied when using , rough annealing, or high-pressure heat treatment. Also, regarding the number of repetitions of the process, -
As an example, the case where the process is performed twice has been described, but the number of times can be further increased depending on conditions such as the degree of miniaturization and the shape of the base level difference.
［発明の効果］
これまでに述べたように、半導体装置の微細化された配
線上に層間絶縁膜を形成するに際し、本発明の半導体装
置の製造方法では、空隙が発生するのを防止しつつ平坦
化用絶縁膜の堆積及び平坦化工程を繰り返すので、空隙
のない平坦化された良好な層間絶縁膜が得られ、半導体
装置の製造に対して歩留りの向上と信頼性の向上が期待
できる。[Effects of the Invention] As described above, when forming an interlayer insulating film on the miniaturized wiring of a semiconductor device, the method for manufacturing a semiconductor device of the present invention prevents the generation of voids and Since the deposition of the planarization insulating film and the planarization process are repeated, a good planarized interlayer insulating film with no voids can be obtained, and it is expected that the yield and reliability will be improved in the manufacture of semiconductor devices.
第１図は本発明の半導体装置の製造方法を疑似段差に適
用したときの工程を示す断面図、第２図は本発明過程の
試行について説明するための断面図、第３図は平坦化用
絶縁膜堆積後の下地配線間隔及び堆積膜厚と堆積膜の段
差部間隔の関係を示すグラフ、第４図は従来の半導体装
置の金属配線形成前の断面図、第５図ないし第７図は従
来技術の問題点を疑似段差を用いて示す断面図である。
１・・・半導体基板、 ６．６ａ 、６ｂ 、 ６ｃ
。
６ｄ・・・層間絶縁膜（平坦化用絶縁膜又はＢＰＳＧ膜
）、 ７・・・疑似段差（疑似配線）。
（（１）
第
図
（１）
第
図
（２）
第２図
第３図
第
図
第
図
第
図Fig. 1 is a cross-sectional view showing the process when the semiconductor device manufacturing method of the present invention is applied to a pseudo step, Fig. 2 is a cross-sectional view for explaining a trial of the process of the present invention, and Fig. 3 is a cross-sectional view for flattening. A graph showing the relationship between the base wiring interval and the deposited film thickness after the insulating film is deposited, and the stepped part interval of the deposited film, FIG. 4 is a cross-sectional view of a conventional semiconductor device before metal wiring is formed, and FIGS. 5 to 7 are FIG. 3 is a cross-sectional view showing a problem with the prior art using a pseudo step. 1... Semiconductor substrate, 6.6a, 6b, 6c
. 6d... Interlayer insulating film (flattening insulating film or BPSG film), 7... Pseudo step (pseudo wiring). ((1) Figure (1) Figure (2) Figure 2 Figure 3 Figure Figure Figure
Claims (1)
縁膜をフローして平坦化する工程において、該絶縁膜を
形成する工程と平坦化する工程とを連続して複数回繰り
返し行なうことを特徴とする半導体装置の製造方法。1. After forming an insulating film on the main surface of a semiconductor substrate, in the step of flowing and planarizing the insulating film, repeating the step of forming the insulating film and the step of planarizing continuously multiple times. A method for manufacturing a semiconductor device, characterized by:
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP916390A JPH03212958A (en) | 1990-01-18 | 1990-01-18 | Manufacture of semiconductor device |
| PCT/JP1991/000040 WO1991011023A1 (en) | 1990-01-18 | 1991-01-17 | Method of producing semiconductor devices |
| DE19914190089 DE4190089T1 (en) | 1990-01-18 | 1991-01-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP916390A JPH03212958A (en) | 1990-01-18 | 1990-01-18 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03212958A true JPH03212958A (en) | 1991-09-18 |
Family
ID=11712948
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP916390A Pending JPH03212958A (en) | 1990-01-18 | 1990-01-18 | Manufacture of semiconductor device |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JPH03212958A (en) |
| DE (1) | DE4190089T1 (en) |
| WO (1) | WO1991011023A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5488007A (en) * | 1992-04-16 | 1996-01-30 | Samsung Electronics Co., Ltd. | Method of manufacture of a semiconductor device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6388829A (en) * | 1986-10-01 | 1988-04-19 | Matsushita Electric Ind Co Ltd | Vapor growth method |
| JPS63192239A (en) * | 1987-02-05 | 1988-08-09 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS6476727A (en) * | 1987-09-17 | 1989-03-22 | Nec Corp | Manufacture of semiconductor device |
-
1990
- 1990-01-18 JP JP916390A patent/JPH03212958A/en active Pending
-
1991
- 1991-01-17 WO PCT/JP1991/000040 patent/WO1991011023A1/en active Application Filing
- 1991-01-17 DE DE19914190089 patent/DE4190089T1/de not_active Ceased
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5488007A (en) * | 1992-04-16 | 1996-01-30 | Samsung Electronics Co., Ltd. | Method of manufacture of a semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| DE4190089T1 (en) | 1992-01-30 |
| WO1991011023A1 (en) | 1991-07-25 |
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