KR930006128B1 - Metal wiring method of semiconductor device - Google Patents

Metal wiring method of semiconductor device Download PDF

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KR930006128B1
KR930006128B1 KR9101861A KR910001861A KR930006128B1 KR 930006128 B1 KR930006128 B1 KR 930006128B1 KR 9101861 A KR9101861 A KR 9101861A KR 910001861 A KR910001861 A KR 910001861A KR 930006128 B1 KR930006128 B1 KR 930006128B1
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forming
metal wiring
metal
method
step
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KR9101861A
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Korean (ko)
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KR920015491A (en
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박종호
이덕민
이상인
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김광호
삼성전자 주식회사
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The method for forming a metal wire is characterized by (a) forming a contact hole on a first insulating film formed on the semiconductor substrate, (b) forming a first metal layer on the whole surface, (c) forming a half of a first metal wire, (d) forming a side wall spacer of a second insulating layer on the side surface of the first metal layer, and then etching the first insulating film, (e) forming a second metal layer on the whole surface, and (f) etching a second metal layer, and then forming a half of a first metal wire.

Description

반도체장치의 금속 배선 형성방법 A metal wiring of a semiconductor device forming method

제1a~d도는 종래의 금속배선 공정순서를 나타낸 단면도. No. 1a ~ d to turn a cross-sectional view showing a conventional metal wiring process sequence.

제2a~i도는 본 발명에 의한 금속배선 공정순서를 나타낸 단면도. The turn 2a ~ i a sectional view of the metal wiring process procedures according to the invention.

* 도면의 주요부분에 대한 부호의 설명 * Description of the Related Art

10 : 반도체기판 11 : 제1절연막 10: Semiconductor substrate 11: a first insulating film

12 : 콘택홀 13 : 금속층 12: contact holes 13: metal layer

14 : 포토레지스트패턴 15 : 금속배선 14: photoresist pattern 15: Metal wire

16 : 콘택홀 매립 금속층 17 : 제1절연막 16: contact hole 17, the buried metal layer: a first insulating film

18 : 측벽스페이서 19 : 요홈 18: sidewall spacer 19: groove

20 : 금속층 21 : 금속배선 20: metal layer 21: Metal wire

22 : 제3절연막 22: third insulating film

본 발명은 반도체 장치의 금속배선 형성방법에 관한 것으로, 특히 서브미크론 간격을 가지는 초고집적 반도체 장치의 금속배선 형성방법에 관한 것이다. The present invention relates to that, in particular, the metal wire forming method of the second high-density semiconductor devices with submicron spacing relates to a method to form metal wiring of a semiconductor device.

최근, 반도체 메모리장치는 서브미크론 단위의 미세공정기술의 발전으로 초고집적화가 급속히 진행되고 있다. Recently, semiconductor memory devices is the development of fine processing technology of the sub-micron unit, the second integration is proceeding rapidly. 예컨대, DRAM은 0.8㎛ 디자인률을 가지는 4M DRAM이 양상되고 있고 16M DRAM이 시제품단계를 거쳐서 양산준비를 서두르고 있으며 0.5㎛이하의 디자인률을 가지는 64M DRAM 및 256M DRAM의 연구가 활발히 진행되고 있다. For example, DRAM is proceeding through the prototype stage and 4M DRAM are aspects 16M DRAM having a 0.8㎛ design rate and rushing mass prepared actively study of 64M DRAM and 256M DRAM having a design ratio of less than 0.5㎛. 이와 같은 초고집적화와 더불어 금속배선기술의 다층화는 필연적이고 배선사이의 간격도 좁아지게 되었다. Multilayer metallization technique, with this second integration is inevitable and became even smaller spacing between wirings.

통상적으로 종래의 금속배선 형성방법은 콘택홀형성, 금속배선형성, 표면보호막 피복순으로 진행되고 있다. Typically conventional metal wiring forming method is proceeds to the contact hole is formed, a metal wiring formed on the surface protective film covering net. 그러므로 금속배선의 단차구조에 의해 금속배선을 덮는 표면보호막의 표면평탄도가 좋지 않을 뿐만 아니라 금속배선 사이의 간격이 좁아 표면보호막에 보이드가 생성되는등의 문제점이 제기되었다. Therefore, the flat surface of the surface protective layer covering the metal wiring by the step structure of the metal wiring also is not only bad been raised a problem such as the spacing between metal wiring voids are created in the narrower surface coating. 게다가 표면보호막의 평탄도가 좋지 않을 경우 후속되는 2차 금속배선공정이 곤란할 뿐만 아니라 심하면 단선등의 불량이 발생되며 생성된 보이드에 의한 금속배선간의 쇼트등의 불량이 발생되게 되어 장치의 신뢰도를 저하시키고 수율을 떨어뜨리는 원인이 되었다. Furthermore, when the flatness of the surface protective film is not good is to be a defect of short like between the metal wiring due to, as well as difficult the second metal wiring process subsequent extreme cases, the failure of the disconnection, etc. is generated create voids decrease the reliability of the device and it became a cause dropping yields. 따라서, 64M DRAM 및 256M DRAM을 실현하기 위해서는 새로운 금속배선기술이 요망되고 있다. Thus, the new metal wiring technology has been desired to realize a 64M DRAM and 256M DRAM.

본 발명의 목적은 상기와 같은 종래기술의 문제점을 해결하기 위하여 새로운 금속배선 형성방법을 제공하는데 있다. An object of the present invention to provide a new method for forming a metal wiring in order to solve the problems of the prior art.

본 발명의 다른 목적은 하프미크론단위의 금속배선 피치를 가지는 반도체 장치의 금속 형성방법을 제공하는데 있다. Another object of the present invention to provide a metal forming a semiconductor device having a metal wiring pitch of a half micron.

본 발명의 또 다른 목적은 후속공정의 평탄도를 향상시킬 수 있는 반도체 장치의 금속배선 형성방법을 제공하는데 있다. It is another object of the present invention there is provided a metal wiring method for forming a semiconductor device capable of improving the flatness of the subsequent process.

상기 목적들을 달성하기 위하여 본 발명의 금속배선 형성방법은 다음과 같은 일련의 공정순선에 따라 이루어지는 것을 특징으로 한다. Metal wiring forming method of the present invention to achieve the above objects is characterized by comprising by the following series of steps sunseon like.

반도체 기판상에 형성된 제1절연막에 콘택홀을 형성하는 공정 ; A step of forming a contact hole in a first insulating film formed on a semiconductor substrate; 상기 콘택홀 형성후, 상기 콘택홀이 완전히 매립되도록 전표면에 평탄한 제1금속층을 형성하는 공정 ; After forming the contact hole, the step of forming the flat first metal layer on the entire surface of the contact hole to be completely filled; 상기 제1금속층의 사진식각공정으로 일정간격으로 배열된 절반의 제1금속배선을 형성하는 공정 ; Forming a first metal wiring of the half arranged at regular intervals in the photolithography process of the first metal layer; 상기 제1금속층의 측면에 제2절연층으로된 측벽 스페이서를 형성하며 동시에 상기 측벽 스페이서 사이의 제1절연막을 일정깊이로 식각하는 공정 ; Forming a sidewall spacer in the second insulating layer on the side of the first metal layer, and at the same time the step of etching the first insulating layer between the sidewall spacer by a predetermined depth; 상기 식각공정후, 측벽 스페이서 사이의 공간을 완전히 채우도록 결과물의 전표면에 제2금속층을 형성하는 공정 ; After the step of forming the etching process, the second metal layer on the entire surface of the resultant so as to completely fill a space between the sidewall spacers; 상기 제2금속층을 이방성 식각공정으로 식각하여 상기 형성된 공간에 배열되며, 상기 측벽 스페이서에 의해 제2금속층과 절연되는 나머지 절발의 제1금속배선을 형성하는 공정. A step of etching the second metal layer by an anisotropic etching process is arranged in the space formed, to form a foot rest section, the first metal wiring is insulated from the second metal layer by the sidewall spacer.

이상과 같이 본 발명은 금속배선을 형성하기 위해 1차로 형성되는 절반의 금속배선을 사이에 두고 서로 인접하는 나머지 절반의 금속배선들을 후속공정시 형성하며, 그 금속배선 형성방법을 포토리소그라피공정으로 제1금속층을 패터닝하여 절반의 금속배선들을 먼저 형성하고 이 금속배선들의 측벽에 에치백 공정으로 절연중 스페이서를 형성하고 이어서 침적되는 제2금속층을 에치백공정으로 식각함으로써 나머지 절반의 금속배선들을 형성한다. The present invention as described above is the one across the metal line of the half formed by car to form a subsequent step the metal wiring of the other half of which are adjacent to each other, the metal wiring forming method for forming a metal wiring by photolithographic process of claim by patterning the first metal layer to form first metal wiring of the half, and by etching the etch-back process to the second metal layer forming a spacer of insulating the etch-back process to the sidewalls of the metal wiring and then immersing forming the metal wiring of the other half . 따라서, 종래와 동일하게 1회의 마스크공정으로 금속배선들의 간격을 측벽 스페이서의 크기로 조절할 수 있어 대략 0.1㎛까지의 금속배선 간격을 얻을 수 있다. Therefore, as in the prior art by one mask process can adjust the spacing of the metal wiring by the size of the sidewall spacers can be obtained a metal line spacing to approximately 0.1㎛.

이하 첨부된 도면을 참조하여 본 발명을 보다 상세히 설명하면 다음과 같다. In more detail the present invention with reference to the accompanying drawings as follows.

본 발명의 이해를 돕기 위해 종래의 금속배선 형성방법을 제1a부터 d도를 참조하여 설명한다. To facilitate understanding of the present invention will be described with the conventional method for forming metal wiring, see Fig d from claim 1a.

종래의 금속배선 공정은 제1a도에 도시한 바와 같이 반도체 기판(1)상에 층간절연막(2)을 덮고 이 층간 절연막(2)에 콘택홀(3)을 형성한다. To form a contact hole (3) in an interlayer insulating film (2) covering the interlayer insulating film 2 on the semiconductor substrate 1 as a conventional metal wiring process is shown in the Figure 1a. 이어서 고융점금속으로 된 장벽층(4)을 전표면에 도포하고 장벽층(4)상에 콘택홀(3)이 매립되도록 알루미늄 또는 알루미늄합금을 소퍼터링 또는 CVD방법으로 증착하여 금속층(5)를 형성한다. Subsequently and by applying a barrier layer 4 in the refractory metal on the entire surface, and depositing aluminum or an aluminum alloy so that the contact holes 3 are embedded in the barrier layer 4 in the Soper gettering or CVD method a metal layer (5) forms. 금속층(5)상에 포토레지스트를 도포하고 사진공정으로 포토레지스트패턴(6)을 형성한다(제1b도 참조). And applying a photoresist on the metal layer (5) to form a photo-resist pattern 6 in the photolithography process (see FIG claim 1b). 상기 포토레지스트패턴(6)을 식각마스크로 사용하여 금속층(5) 및 장벽층(4)을 식각하여 금속배선(7)을 형성한다(제1c도 참조). The photo-resist pattern 6 by using as an etching mask to etch the metal layer 5 and the barrier layer 4 to form a metal wiring 7 (see Fig claim 1c). 이어서 제1D도에 도시된 바와 같이 PSG막 또는 BPSG막 등으로 된 표면보호막(8)을 전표면에 피복하여 금속배선공정을 완료한다. Followed by coating a surface protection film 8 in the PSG film or a BPSG film or the like, as illustrated in Fig. 1D on the entire surface to complete the metal wiring process.

상술한 바와 같이 종래의 금속배선 공정은 리소그리피공정을 사용하여 금속층을 식각함으로써 금속배선을 형성한 다음 표면보호막을 덮기 때문에 금속배선 간격이 좁아질수록 금속배선과 금속배선 사이의 요홈이 어스펙트 비가 커지게 되므로 표면보호막 도포시 요홈내에 보이드가 생성되게 된다. Conventional metal wiring process as described above, resources Griffey by using the process to form a metal interconnection by etching the metal layer, and then a surface protective film of the groove is an aspect between the metal line spacing more narrow quality because of covering the metal wire and the metal wire ratio because increases is presented when voids are created in the surface protective layer coating grooves. 또한, 금속배선의 단차때문에 표면보호막의 표면요철이 커지게 된다. Further, the surface roughness becomes large because of the surface coating step of the metal wiring. 이와 같은 보이드 생성, 평탄도 열하는 금속배선의 신뢰도를 떨어뜨리고 후속공정을 어렵게 한다. The voids generated, flatness of thermal loading is difficult for a subsequent process to drop the reliability of the metal wiring.

제2a로부터 i도를 참조하여 본 발명에 의한 금속배선 공정을 설명한다. 2a from a reference to Figure i will be described with a metal wiring process according to the invention.

제2a도를 참조하면, 실리콘 반도체 기판(10)위에 산화막으로 된 제1절연막(11)을 형성하고 제1절연막(11)에 콘택홀(12)을 형성한다. Referring to the Figure 2a, to form a contact hole 12 formed in the silicon semiconductor substrate 10. The first insulation film 11 and the oxide film on the first insulation film 11.

제2b도를 참조하면, 콘택홀 형성후 콘택홀(12)이 완전히 매립되도록 전표면에 알루미늄 합금, 예컨대 알루미늄에 Si, Cu, Ti, Pd, Hf, B등이 첨가된 알루미늄합금을 스퍼터링 또는 CVD 방법으로 침적하여 제1금속층(13)을 형성한다. No. 2b Referring to Figure, the sputtering of aluminum alloy, for example, the aluminum alloy added Si, Cu, Ti, Pd, Hf, and B to the aluminum on the entire surface so that the contact hole 12 is completely filled after forming the contact holes or CVD immersed in a manner to form a first metal layer (13). 여기서, 알루미늄합금을 침적하기 전에 Ti/TiN, MoSix, Tiw, TiSix, W등의 고융점금속 또는 고융점금속 실리사이드로 된 장벽층을 형성할 수도 있다. Wherein, prior to depositing the aluminum alloy may form a high-melting point metal or a high melting point metal silicide layer with a barrier, such as Ti / TiN, MoSix, Tiw, TiSix, W.

제2c도를 참조하면, 상기 금속층(13)상에 포토레지스트를 도포하고 사진공정에 의해 포토레지스트패턴(14)을 형성한다. Referring to the Fig. 2c, the photoresist is applied on the metal layer 13 to form a photoresist pattern 14 by a photolithography process. 여기서 포토레지스트패턴(14)은 완성된 금속배선의 하나씩 건너뛴 절반의 금속배선들과 대응된다. The photoresist pattern 14 is compatible with the metal wiring of a half every other one of the completed metal wiring. 이때 가급적 선폭이 넓은 금속배선이 먼저 형성되도록 하는 것이 뒤따르는 에치백 공정시 영향을 덜 받는다. The etch-back process when possible, are less affect to follow such that a line width of a wide metal line is formed first.

제2d도를 참조하면, 상기 포토레지스트패턴(14)을 식각마스크로 사용하여 제1금속층(13)을 식각하고 포토레지스트패턴(14)을 제거함으로써 절반의 금속배선들(15) 및 콘택홀 매립금속층(16)을 형성한다. Refer to claim 2d even when the photo resist pattern 14 by using as an etching mask, etching the first metal layer 13 and the photoresist pattern 14, the metal wires 15 and the contact holes filled in half by eliminating to form a metal layer 16.

제2e도를 참조하면, 상기 식각공정후, 전표면에 SixNy, SixOyNz, USG, PSG 또는 BPSG등의 화합물로 된 제2절연막(17)을 균일하게 피복한다. Referring to the Figure 2e, the etching process and then, uniformly coated with a second insulating film (17) to compounds such as SixNy, SixOyNz, USG, PSG or BPSG on the entire surface.

제2f도를 참조하면, 상기 제2절연막(17)을 에치백방법으로 전면식각하여 상기 절반의 금속배선들(15)의 측벽에만 상기 제2절연물질로 된 측벽스페이서(18)를 남긴다. Referring to the Fig. 2f to leave the second insulating film 17, the sidewall spacers 18 into the second insulating material only in the side wall of the metal wiring of the front half by the etching (15) to the etch-back method in a. 이때 적절한 과잉식각을 함으로써, 이미 형성된 금속배선의 바닥보다 더 깊에 형성하는 것이 바람직하다. In this case, by the appropriate over-etched, it is preferable to form the deeper than the bottom of the already formed metal wire. 이는 인접하는 금속배선들의 바닥높이를 서로 다르게 함으로써 금속배선간의 기생커패시턴스를 감소시킬 수 있다. Which by varying the height of the bottom of the adjacent metal leads from each other it is possible to reduce the parasitic capacitance between the metal leads.

제2g도를 참조하면, 상기 요홈(19)이 완전히 매립되도록 알루미늄 함급을 스퍼터링 또는 CVD방법으로 전표면에 침적하여 제2금속층(20)을 형성한다. Article Referring to Figure 2g, a second metal layer 20 and the recess 19 is deposited on the entire surface by a sputtering or CVD method hamgeup aluminum is fully embedded.

제2h도를 참조하면, 상기 침적된 제2금속층(20)을 에치백 공정으로 전면식각하여 상기 형성된 절반의 금속배선들(15) 사이의 요홈(19) 내에 나머지 절반의 금속배선들(21)을 형성한다. Referring to the 2h also, the metal wiring of the other half in a groove (19) between the to in the deposited second metal layer 20 over etched to etch back process of the metal wiring of the formed half 15, 21 the form.

제2i도를 참조하면, 상기 측벽스페이서와 동일물질로 된 제3절연막(22)을 그 표면이 대체적으로 평판하게 되도록 전표면에 침적하여 금속배선공정을 완료한다. Referring to the FIG. 2i, a third insulating film (22) in the side wall spacer and the same substance to the surface is deposited on the entire surface so as to be substantially flat in the metal wiring process is completed.

이상과 같이 본 발명에 의한 금속배선공정은 인접하는 금속배선들 사이에 측벽스페이서가 형성되어 있기때문에 제3절연막의 평탄도를 향상시킬 수 있고 보이드생성을 방지할 수 있다. Metal wiring process according to the invention as described above is because the sidewall spacers are formed between the metal wire adjacent to improve the flatness of the third insulating film, and it is possible to prevent voids generation.

또한 종래의 금속배선공정과 동일하게 1회의 포토리소그라피 공정을 사용하면서도 절반의 금속배선들에 셀프얼라인되게 나머지 절반의 금속배선들을 형성할 수 있고 측벽스페이서의 폭을 조절함으로써 금속배선 간격을 0.1㎛까지 좁힐 수 있다. In addition, the metal wiring 0.1㎛ interval by adjusting the conventional metal wiring process in the same manner to form a single photolithographic the other half of the metal to be self-aligned to the metal wiring of the half step, but uses a wire and the width of the sidewall spacers to be narrow. 그러므로 6M DRAM 및 256M DRAM의 금속배선 공정에 사용가능하다. Therefore, it is possible to use a metal wiring process of 6M DRAM and 256M DRAM.

Claims (10)

  1. 반도체 기판상에 형성된 제1절연막에 콘택홀을 형성하는 공정 ; A step of forming a contact hole in a first insulating film formed on a semiconductor substrate; 상기 콘택홀 형성후, 상기 콘택홀이 완전히 매립되도록 전표면에 평탄한 제1금속층을 형성하는 공정 ; After forming the contact hole, the step of forming the flat first metal layer on the entire surface of the contact hole to be completely filled; 상기 제1금속층의 사진식각공정으로 일정간격으로 배열된 절반의 제1금속배선을 형성하는 공정 ; Forming a first metal wiring of the half arranged at regular intervals in the photolithography process of the first metal layer; 상기 제1금속층의 측면에 제2절연층으로된 측벽 스페이서를 형성하며 동시에 상기 측벽 스페이서 사이의 제1절연막을 일정깊이로 식각하는 공정 ; Forming a sidewall spacer in the second insulating layer on the side of the first metal layer, and at the same time the step of etching the first insulating layer between the sidewall spacer by a predetermined depth; 상기 식각공정후, 측벽 스페이서 사이의 공간을 완전히 채우도록 결과물의 전표면에 제2금속층을 형성하는 공정 ; After the step of forming the etching process, the second metal layer on the entire surface of the resultant so as to completely fill a space between the sidewall spacers; 상기 제2금속층을 이방성 식각공정으로 식각하여 상기 형성된 공간에 배열되며, 상기 측벽 스페이서에 의해 제1금속층과 절연되는 나머지 절반의 제1금속배선을 형성하는 공정을 구비하는 것을 특징으로 하는 반도체 장치의 금속배선 형성방법. A semiconductor device characterized by comprising the step of etching the second metal layer by an anisotropic etching process is arranged in the space formed, forming a first metal wiring of the other half which is insulated from the first metal layer by the sidewall spacers metal wiring forming method.
  2. 제1항에 있어서, 상기 금속층들은 고온 스퍼터링 또는 CVD 방법중 어느 하나에 의해 침적되는 것을 특징으로 하는 반도체 장치의 금속배선 형성방법. The method of claim 1, wherein the metal layers of metal wiring method for forming a semiconductor device characterized in that the deposition by one of high-temperature sputtering or a CVD method.
  3. 제1항에 있어서, 상기 금속층을 알루미늄 또는 알루미늄 합금중 어느 하나로 형성된 것을 특징으로 하는 반도체 장치의 금속배선 형성방법. The method of claim 1, wherein the metal wiring formation method of a semiconductor device, characterized in that the metal layer is formed of one of aluminum or an aluminum alloy.
  4. 제3항에 있어서, 상기 금속층은 알루미늄에 Si, Cu, Ti, Pd, Hf 또는 B가 소량첨가된 알루미늄합금인 것을 특징으로 하는 반도체 장치의 금속배선 형성방법. 4. The method of claim 3, wherein the metal layer is a metal wiring formation method of a semiconductor device, characterized in that the aluminum is Si, Cu, Ti, Pd, Hf or B, a small amount of an aluminum alloy added.
  5. 제1항에 있어서, 상기 금속층은 장벽층과 알루미늄합금의 적층막으로 된 것을 특징으로 하는 반도체 장치의 금속배선 형성방법. The method of claim 1, wherein the metal layer is a metal wiring formation method of a semiconductor device, characterized in that the laminate film of the barrier layer and the aluminum alloy.
  6. 제5항에 있어서, 상기 장벽층은 Ti/TiN, MoSix, Tiw, TiSx 또는 W등인 것을 특징으로 하는 반도체 장치의 금속배선 형성방법. The method of claim 5, wherein the barrier layer is forming a metal wiring of a semiconductor device or the like, characterized in that Ti / TiN, MoSix, Tiw, TiSx or W.
  7. 제1항에 있어서, 상기 측벽 스페이서는 SixNy, SixOyNz, USG, PSG 또는 BPSG로 된 것을 특징으로 하는 반도체 장치의 금속배선 형성방법. The method of claim 1, wherein the sidewall spacers are metal wires forming a semiconductor device, characterized in that the by SixNy, SixOyNz, USG, PSG, or BPSG.
  8. 제1항에 있어서, 상기 측벽스페이서를 형성하는 공정은 상기 제1금속층 형성공정후 플라즈마 저온 증착법 또는 대기압 화학기상 증착법에 의해 결과물의 전표면에 제2절연층을 형성하는 공정 ; The method of claim 1, wherein the step of forming the sidewall spacers is a step of forming a second insulating layer on the entire surface of the resultant formed by the first metal layer after the first step a low temperature plasma deposition or atmospheric pressure chemical vapor deposition; 과 에치백 공정으로 상기 제2절연층을 식각하는 공정을 포함하는 것을 특징으로 하는 반도체 장치의 금속배선 형성방법. And etch back process of a metal wiring method for forming a semiconductor device characterized in that it comprises a step of etching the second insulating layer.
  9. 제1항에 있어서, 상기 측벽 스페이서들의 두께는 약 0.1㎛인 것을 특징으로 하는 반도체 장치의 금속배선 형성방법. The method of claim 1, wherein the metal wiring formation method of a semiconductor device, characterized in that the thickness is from about 0.1㎛ of the sidewall spacer.
  10. 형성하고자 하는 금속배선의 2피치 간격으로 배열된 절반의 금속배선을 형성하는 공정 ; A step of forming a metal wiring of a half arranged in a second pitch of the metal wiring to be formed; 에치백 공정으로 상기 절반의 금속배선의 측면상에 절연물질로 이루어진 측벽 스페이서를 형성하는 공정 ; In the etch back process step of forming a side wall spacer made of an insulating material on a side surface of the metal wiring of the half; 과 에치백 공정에 의하여 상기 절반의 금속배선 사이의 공간에 배열되어 상기 측벽 스페이서에 의하여 상기 절반의 금속배선과 셀프얼라인되고 격리되는 나머지 절반의 금속배선을 형성하는 공정을 구비하는 것을 특징으로 하는 반도체 장치의 금속배선 형성방법. And in by the etch-back process it is arranged in the space between the metal wiring of the half which is characterized in that it comprises a step of forming a metal wiring of the other half which is, by the side wall spacer and the metal wiring and the self-alignment of the half isolated a metal wiring method for forming a semiconductor device.
KR9101861A 1991-01-31 1991-01-31 Metal wiring method of semiconductor device KR930006128B1 (en)

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KR9101861A KR930006128B1 (en) 1991-01-31 1991-01-31 Metal wiring method of semiconductor device
FR9106646A FR2672429B1 (en) 1991-01-31 1991-06-03 Method for producing metal conductors in a semiconductor device.
ITMI911517 IT1247972B (en) 1991-01-31 1991-06-04 Method for the formation of metal tracks of a semiconductor device
GB9112054A GB2252448B (en) 1991-01-31 1991-06-05 Method for forming metal wirings of a semiconductor device
DE19914118380 DE4118380C2 (en) 1991-01-31 1991-06-05 A process for the formation of metal lines on semiconductor devices
JP17060891A JPH0789566B2 (en) 1991-01-31 1991-06-14 Method of forming a metal line in a semiconductor device

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US4400865A (en) * 1980-07-08 1983-08-30 International Business Machines Corporation Self-aligned metal process for integrated circuit metallization
US4424621A (en) * 1981-12-30 1984-01-10 International Business Machines Corporation Method to fabricate stud structure for self-aligned metallization
US4584761A (en) * 1984-05-15 1986-04-29 Digital Equipment Corporation Integrated circuit chip processing techniques and integrated chip produced thereby
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US4789648A (en) * 1985-10-28 1988-12-06 International Business Machines Corporation Method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive lines simultaneously with stud vias
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IT1247972B (en) 1995-01-05
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FR2672429A1 (en) 1992-08-07
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JPH04249346A (en) 1992-09-04
ITMI911517D0 (en) 1991-06-04

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