JPH0321043A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To flatten the interlayer insulating film during multilayer wiring formation uniformly however wide the space of wiring may be by precipitating a silicon oxide film from in silica supersaturated solution and accumulating it only on an insulating film so as to fill the space between desired patterns of metal wiring. CONSTITUTION:The wiring of desired metal patterns is formed on an insulating film 13, which has a desired wiring connection hole, and a silicon oxide film 16 is precipitated from in silica saturated solution and is accumulated only on the insulating film 13 so as to fill the space between the desired patterns of the metal wiring 14. Since the silicon oxide film 16 is precipitated and accumulated selectively only on the interlayer insulating film 13 free of wiring patterns so as to fill the space between patterns, the interlayer insulating film can be flattened uniformly whether the space between wirings is wide or narrow.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and in particular, to planarization of an interlayer insulating film by selective deposition of an insulating film during a wiring formation process. Regarding the method.

(Prior Art) Conventionally, in the form or method of forming an interlayer insulating film of multilayer wiring in a semiconductor device, as shown in FIG. After forming the l-th wiring 104 to be connected, as shown in FIG.
As shown in b), for example, a plasma oxide film 105 is deposited on the entire surface, and then a resist film 106 is spin-coated to flatten the entire surface. Although plasma oxide films have the advantage of being able to be formed at low temperatures, they have poor step coverage and tend to have an overhang shape at step differences.

Next, the entire surface is covered with the resist 1/film 106 and the plasma oxide film 10.
After removing the resist 1 and the film 106 by etching using a reactive ion etching (RIE) method under etching conditions such that the etching rates of the first and second films are equal, a plasma oxide film 107 is further deposited on the entire surface. wiring 104
A second wiring 108 was formed to connect to.

However, this method of planarizing an interlayer insulating film using the resist etch bank method has problems that cannot be solved. for example,
Due to the poor step coverage of the plasma oxide film, holes remain in narrowly spaced wiring, and the next wiring material enters into these holes, causing short circuits (Figure 3 (C)).
. Note that the internal structure and surface state of the semiconductor substrate are not directly related to the gist of the present invention, so detailed illustrations thereof are omitted.

The same applies to FIGS. 1 and 2.

(Problems to be Solved by the Invention) As described above, in the conventional interlayer insulating film planarization method using the etch bank method when forming multilayer wiring, good planarization can be achieved when the space between wirings is wide to some extent. However, as the wiring space becomes narrower than 1 μm, there is a problem in that \V flattening defects due to the ig holes, which cause short circuits between the wirings, increase.

An object of the present invention is to provide a method for manufacturing a semiconductor device that can solve these problems and uniformly flatten an interlayer insulating film when forming multilayer wiring, whether it is a wide wiring or a narrow wiring. "Target."

[Structure of the invention]

(Means for Solving the Problems) A method for flattening a wear-resistant green film according to the first invention of the present invention includes:
In the wiring formation process of a semiconductor device, a desired pattern of metal wiring is formed on an insulating film having desired wiring connection holes, and a silicon oxide film is precipitated and deposited from a silica saturated solution only on the insulating film. The present invention is characterized in that the surface formed by the silicon oxide film and the metal wiring is flattened by filling the spaces between the desired patterns of the metal wiring.

Further, in the method for planarizing an interlayer insulating film according to the second aspect of the present invention, a desired pattern of wiring of a first metal is formed on an insulating film having a desired wiring connection hole in a wiring forming process of a semiconductor device. After forming a second metal on the top and side surfaces of the second metal wiring, a silicon oxide film is precipitated and deposited from a silica supersaturated solution only on the second insulating film. flattening the surface formed by the silicon oxide film and a second metal film covering two and side surfaces of the first metal wiring; It is characterized by

(Function) According to the present invention, the silicon oxide film is selectively deposited only on the interlayer insulating film of the wiring pattern to fill the space between the patterns, regardless of whether the space between the wirings is wide or narrow. Since the interlayer insulating film can be planarized in a similar manner, it becomes easy to process the metal wiring thereon, and it is possible to significantly improve the yield loss caused by the step difference in the base in so-called multilayer wiring.

4. According to the present invention, since the interlayer insulating film between the metal wirings can be formed at a low temperature (about room temperature), it is possible to prevent cracking of the metal wirings and improve the reliability, yield, etc. of the wirings.

According to the present invention, there is no need to use an etch-back method or the like, and it is only necessary to immerse the material in a solution, which greatly simplifies the process and shortens the manufacturing process.

Further, according to the second aspect of the present invention, since the first metal wiring is covered with the second metal film, the first metal is mainly aluminum, which is easily corroded by a silica supersaturated solution. It becomes possible to use conventional wiring materials.

Therefore, even if the second metal covering the surface has a high resistance value, its influence can be reduced.

(Example) Next, an example of the present invention will be described with reference to the drawings.

FIGS. 1A to 1C are cross-sectional views of a semiconductor device manufacturing process for explaining a first embodiment of the present invention.

? First, as shown in FIG. 1(a), an interlayer insulating film 13 is formed from a CVD oxide film or a BPSG film having a wiring connection hole to the wiring 12 on the surface of the semiconductor substrate 11 on which an integrated circuit is formed or to the semiconductor surface. After that, a metal wiring 14 having a desired pattern and a thickness of about 4,000 wafers is formed using, for example, tungsten (W). At this time, the interlayer insulating film l3 is smoothed and flattened by a high temperature melt method using ordinary BPSG (borophosphosilicate glass) or the like.

Next, as shown in FIG. 1(b), the entire surface of the semiconductor substrate is immersed in a hydrosilicic acid aqueous solution supersaturated with silica, and a dense silicon oxide film 16 is formed only on the interlayer insulating film 3 to a thickness of, for example, Precipitate and deposit about 4000λ.

A supersaturated silica solution is made as follows.

First, 40% by weight of hydrofluoric acid (H 2 Si
F G ) The aqueous solution is diluted with water to prepare a 3 mol/Q hydrofluorosilicic acid solution, and this is saturated with silica (SiO■).

An aluminum plate (AQ) is immersed in this solution to create a silica supersaturated solution. The concentration of the hydrofluorosilicic acid solution is not particularly limited to the examples. Is silica oversaturated? A hydrofluorosilicic acid solution of any concentration can be used as long as a solution of .

The above reaction formula is as follows.

H2SiF6+ 2H20→SiO■+61{F
... ■2A flood +61 {F → 2A sad F3 + 3H■
...(2)0) By reacting with the legs and consuming the HF, the 1{F concentration decreases and the deposition rate of the Sin2 film increases.

As the reaction temperature increases, the reaction (1) proceeds to the right, and Sin2
The precipitation of will increase. In this example, a solution with a liquid temperature of 30°C was used, but the deposition rate of the silicon oxide film was 1000 people/30°C.
It was about an hour. At present, when the liquid temperature is set to 35° C., the precipitation rate can be increased to 800 to IOOOA/hour. It is possible to achieve such a precipitation rate even at a liquid temperature of 20 to 30°C. This silicon oxide film l6 is very dense and is formed in close contact with the interlayer insulating film 13.

Next, as shown in the construction drawing (c), the entire surface is coated with low temperature (3
A plasma CVD oxide film 17, which can be deposited at a temperature of about 0.0°C (approximately 100°C), is deposited to a thickness of about 4,000 yen, and a wiring connection hole is opened to the metal wiring layer 14 in the lower layer 7 using an ordinary lamination lithography technique using a resist and an RIE method. ,A
A pattern of metal wiring 18 made of Q-Si-Cu is formed.

FIGS. 2(a) and 2(b) are cross-sectional views of a semiconductor device manufacturing process for explaining a second embodiment of the present invention.

First, as shown in FIG. 2(a), a certain lower wiring 12 or
After forming the thermally reflowed interlayer insulating film 13 with a layered structure of, for example, a C V D Sin2 film or a BPSG film, which has wiring connection holes for the N'' and P impurity layers on the semiconductor surface, several weight Using aluminum (abbreviated as i-Si) mixed with 1% silicon as an impurity,
An AQ-Si wiring 14 having a desired pattern and a film thickness of about 4000 A is formed as a first metal wiring.

Furthermore, a tungsten film 1 is selectively applied to this AQ-Sj surface.
About 500 people will accumulate 5. At this time, a hot-wall type LPGVD furnace using WF6 and 112 gas was used, but other equipment may also be used.

Next, as shown in FIG. 2(b), the entire surface of the substrate was immersed in an aqueous solution of hydrofluoric acid supersaturated with silica in the same manner as in Example 8 of Step 8, and silicon was oxidized only on the interlayer insulating film l3. Film 16 is deposited, for example, at about 450 OA. The conditions for the aqueous solution may be the same as in the first embodiment.

As a result, the step 4500A formed by the first metal wiring and the tungsten film covering its surface is completely flattened. Note that a silicon oxide film is not deposited on the surface of a tungsten film or the like. Below, Figure 1 (
The interlayer insulating film 17 and the second layer metal wiring 18 can be obtained through the steps described in c).

The present invention is not limited to the above embodiments.

For example, in the embodiment, the case of two-layer metal wiring has been described, but stable multilayer wiring can be realized by repeating the same process in the case of three-layer, four-layer, . . . N-layer metal wiring.

In addition, in the second embodiment, a CVD method was used to select or lengthen the tungsten film to cover the surface of the i-Si wiring in the first layer, but a molybdenum (Mo) film may also be used.
After the Q-Si wiring is subjected to appropriate pretreatment, electroless plating may be performed to coat it with, for example, zinc (Zn).

Furthermore, nickel (Nj) is applied by electrolytic plating on top of zinc.
It may be coated with.

〔Effect of the invention〕

As explained above, in the present invention, the silicon oxide film is selectively deposited only on the insulating film in the wiring space to fill the spaces between the wiring patterns, so the interlayer insulating film can be easily flattened, and as a result, the interlayer insulating film can be easily flattened. It is possible to eliminate the level difference in the wiring, and it is possible to significantly improve the reduction in product yield caused by the level difference in the wiring.

Further, since the present invention can form an interlayer insulating film between metal wirings at a low temperature, it is possible to prevent the occurrence of hillocks in the metal wirings, thereby improving the reliability and yield of the wirings.

Further, according to the present invention, there is no need to use an etch-puncture method using a resist to planarize the interlayer film of multilayer wiring, and the process can be significantly simplified and the manufacturing process can be shortened.

In addition, AQ-S, which is a material that is relatively easy to etch, is used as the first metal of the second invention of the present invention to form fine wiring, and the second and side surfaces of the metal are By covering a metal-coated structure with an insulating film formed at a low temperature, it is possible to increase the resistance to voids generated by electromigration and thermal history.

In addition, it is possible to effectively reduce wiring resistance because the first metal wiring can be coated with the second metal film, regardless of the wiring width and space of the first metal wiring determined by phosphorography. It is.

[Brief explanation of the drawing]

FIGS. 1(.) to (c) are process sectional views for explaining the first embodiment of the present invention, and FIGS. 2(a) to (c) are process sectional views for explaining the second embodiment of the present invention. A process sectional view for explaining the process and FIGS. 3(a) to 3(c) are process sectional views for explaining the prior art. II, 101 Semiconductor substrate 12, 1.02・Lower wiring 13, 1.7, 103, 105, 107
...Interlayer insulating film +4. 1.04・First layer metal wiring 15...Second metal film l6・Precipitated silicon oxide film 1
1 1.8, 108...Second layer metal wiring -12

Claims (2)

[Claims] (1) In the wiring formation process of a semiconductor device, there is a step of forming a desired metal wiring pattern on an insulating film having a desired wiring connection hole, and a step of forming a silicon oxide film only on the insulating film in a silica supersaturated solution. a step of flattening the surface formed by the silicon oxide film and the metal wiring by depositing the silicon oxide film and filling the spaces between the desired patterns of the metal wiring. Production method. (2) In the wiring formation process of a semiconductor device, a process of forming a wiring of a desired pattern of a first metal on an insulating film having a desired wiring connection hole, and a process of forming a wiring of a desired pattern of a first metal on the top and side surfaces of the wiring.
forming a metal film, and depositing a silicon oxide film from a silica supersaturated solution only on the interlayer insulating film to fill the spaces between the desired patterns of the first metal wiring. A method for manufacturing a semiconductor device, comprising the step of flattening a surface formed by the film and a second metal film covering the top and side surfaces of the first metal wiring.