US9960147B2 - Power module - Google Patents

Power module Download PDF

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Publication number
US9960147B2
US9960147B2 US15/541,861 US201515541861A US9960147B2 US 9960147 B2 US9960147 B2 US 9960147B2 US 201515541861 A US201515541861 A US 201515541861A US 9960147 B2 US9960147 B2 US 9960147B2
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Prior art keywords
edge
semiconductor chip
solder
semiconductor chips
edges
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US20180005986A1 (en
Inventor
Shiro Yamashita
Yusuke Takagi
Takahiro Shimura
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Hitachi Astemo Ltd
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Hitachi Automotive Systems Ltd
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Assigned to HITACHI AUTOMOTIVE SYSTEMS, LTD. reassignment HITACHI AUTOMOTIVE SYSTEMS, LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SHIMURA, TAKAHIRO, TAKAGI, YUSUKE, YAMASHITA, SHIRO
Publication of US20180005986A1 publication Critical patent/US20180005986A1/en
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Assigned to HITACHI ASTEMO, LTD. reassignment HITACHI ASTEMO, LTD. CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: HITACHI AUTOMOTIVE SYSTEMS, LTD.
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Definitions

  • the present invention relates to a power module provided with a power semiconductor chip.
  • Vehicles such as hybrid vehicles, plug-in hybrid vehicles, and electric vehicles, are mounted with a power-drive high-voltage rechargeable battery, an inverter that converts the power of the direct-current high-voltage output of the high-voltage rechargeable battery into the power of alternating current high voltage output for driving a motor, and other devices.
  • the inverter includes a power module having a built-in power semiconductor chip.
  • a structure is known in which a semiconductor chip is mounted between a pair of conductor plates thermally coupled to a heat dissipation plate.
  • a power module which also uses a conductor plate as a heat dissipation plate.
  • the semiconductor chip has one face and another face opposite to the one face.
  • the one face and the another face of the semiconductor chip are respectively soldered to one or the other of a pair of conductor plates with the semiconductor chip sandwiched between the pair of conductor plates.
  • a plurality of semiconductor chips is sometimes mounted between a pair of conductor plates.
  • the area around the semiconductor chip is sometimes filled with a sealing resin (see e.g. Patent Literature 1).
  • Patent Literature 1 Japanese Unexamined Patent Application Publication No. 2005-244166
  • solder in the forming regions of the solder fillets overflows from the outer edges of the conductor plate, short circuits occur between other members, or the overflowed solder is peeled off to be a conductive foreign substance, resulting in a factor to cause a fault or a factor to degrade performances.
  • a power module includes: a base plate; a first semiconductor chip having four edges; a second semiconductor chip having four edges, one of the four edges disposed adjacent to a first edge of the first semiconductor chip, the second semiconductor chip soldered to the base plate; and a third semiconductor chip having four edges, one of the four edges disposed adjacent to a second edge of the first semiconductor chip, the third semiconductor chip soldered to the base plate.
  • at least one of a third edge or a fourth edge of the first semiconductor chip is disposed adjacent to a side end of the base plate.
  • a length of a solder fillet formed on the edge of the first semiconductor chip at the shortest distance is formed in the shortest length.
  • a short circuit between semiconductor chips or overflows of solder from the side end of a base plate due to overflows of solder from solder fillet forming regions can be suppressed.
  • FIG. 1 is a perspective view of the appearance of an embodiment of a power module according to the present invention.
  • FIG. 2 is a cross sectional view of the power module in FIG. 1 taken along line II-II in FIG. 1 .
  • FIG. 3 is a schematic plan view of the mounting structure of semiconductor chips.
  • FIG. 4 is an enlarged cross sectional view of region IV in FIG. 2 taken along line IV-IV in FIG. 3 .
  • FIG. 5 show diagrams for explaining the relationship between the increased amount of the surface area of a solder fillet and the length of a solder fillet forming region; (a) is a cross sectional view for illustrating the criteria of the solder structure of a semiconductor chip, and (b) is a characteristic view of the relationship between the increased amount of the surface area of the solder fillet and the length of the solder fillet forming region.
  • FIG. 6 is a schematic plan view of a second embodiment of the present invention showing the mounting structure of semiconductor chips provided on a power module.
  • FIG. 7 is a cross sectional view taken along line VII-VII in FIG. 6 .
  • FIG. 8 is a cross sectional view of a third embodiment of the present invention showing the mounting structure of semiconductor chips provided on a power module.
  • FIG. 9 is a cross sectional view of a fourth embodiment of the present invention showing the mounting structure of semiconductor chips provided on a power module.
  • FIG. 10 is a schematic plan view of a fifth embodiment of the present invention showing the mounting structure of semiconductor chips provided on a power module.
  • FIG. 11 is a diagram of an exemplary modification of the fifth embodiment.
  • FIG. 12 is a schematic plan view of a sixth embodiment of the present invention showing the mounting structure of semiconductor chips provided on a power module.
  • FIG. 13 is a diagram of a first exemplary modification of the sixth embodiment.
  • FIG. 14 is a diagram of a second exemplary modification of the sixth embodiment.
  • FIG. 15 is a schematic plan view of a seventh embodiment of the present invention showing the mounting structure of semiconductor chips provided on a power module.
  • FIG. 16 is a diagram of an exemplary modification of the seventh embodiment.
  • FIG. 17 is a diagram of a first effect of the present invention showing the frequency of occurrence of short circuits between semiconductor chips according to the first embodiment of the present invention.
  • FIG. 18 is a diagram of a second effect of the present invention showing the frequency of occurrence of overflows of solder to the side end of a frame according to the second embodiment of the present invention.
  • FIGS. 1 to 4 a first embodiment of a power module according to the present invention will be described.
  • FIG. 1 is a perspective view of the appearance of an embodiment of a power module according to the present invention.
  • FIG. 2 is a cross sectional view of the power module in FIG. 1 taken along line II-II in FIG. 1 .
  • a power module 100 can be used in a device, such as an on-vehicle power converter of a rotary electric machine drive system installed on an automobile.
  • the power module 100 includes a module case 201 , which accommodates a plurality of power semiconductor chips 11 to 14 to be described later, mounted between a first lead frame 101 and a second lead frame 102 (see FIG. 3 and other drawings).
  • the module case 201 is formed of an aluminum alloy material, such as Al, AlSi, AlSiC, and Al—C, for example, having a can-type shape formed in one piece with no seam (in the following, referred to as a can type).
  • the can type means a container in a nearly rectangular parallelepiped shape with a bottom, the container having an insertion port 306 on a predetermined one face.
  • the module case 201 has a structure having no openings other than the insertion port 306 .
  • the outer edge of the insertion port 306 is surrounded by a flange 304 B.
  • a metal case in such a shape is formed.
  • a cooling medium such as water and oil
  • sealing against the cooling medium can be secured by the flange 304 B.
  • the cooling medium can be prevented from entering the inside and the terminal portion of the module case 201 with a simple configuration.
  • the shape of the module case 201 below the flange 304 B has a thin rectangular parallelepiped shape having a pair of heat dissipation bases 307 on which fins 305 are uniformly disposed.
  • a curved portion 304 A is formed whose thickness is extremely thin.
  • An insulating sheet 333 of a high thermal conductivity is provided between the inner surfaces of the heat dissipation bases 307 and the first and the second lead frames 101 and 102 . In operation, the power semiconductor chips 11 to 14 generate heat, and their temperatures become high.
  • heat generated by the semiconductor chips 11 to 14 in operation is spread in the first and the second lead frames 101 and 102 , and conducted to the insulating sheet 333 .
  • the heat is dissipated from the heat dissipation bases 307 formed on the module case 201 and the fins 305 provided on the heat dissipation bases 307 to a cooling medium.
  • a high cooling performance can be implemented.
  • the semiconductor chips 11 to 14 are mounted between the first and the second lead frames 101 and 102 by soldering, and regions around the semiconductor chips 11 to 14 are sealed with a primary sealing material 350 .
  • the mounting structure of the semiconductor chips 11 to 14 on the first and the second lead frames 101 and 102 will be described later.
  • the first lead frame 101 has a plurality of leads 111 extending upwardly.
  • the tip ends of the leads 111 are exposed to the outside of the primary sealing material 350 .
  • the first lead frame 101 is integrally formed with the primary sealing material 350 with the tip ends of the leads 111 exposed.
  • To the tip ends of the leads 111 direct current positive and negative electrode terminals 121 and an alternating current terminal 121 and a plurality of external signal terminals 122 are joined by soldering, for example.
  • the direct current positive and negative electrode terminals 121 and the alternating current terminal 121 , the plurality of external signal terminals 122 , and the leads 111 of the first lead frame 101 are integrally formed with an auxiliary mold body 380 .
  • the primary sealing material 350 integrally formed with the first lead frame 101 is accommodated in the module case 201 with the direct current positive and negative electrode terminals 121 and the alternating current terminal 121 and the plurality of external signal terminals 122 , which are integrally formed with the auxiliary mold body 380 , connected to the corresponding leads 111 of the first lead frame 101 .
  • a secondary sealing material 351 is charged from the insertion port 306 of the flange 304 B.
  • the secondary sealing material 351 is charged in the inner side of the flange 304 B and the space between the edges of the first and the second lead frames 101 and 102 and the primary sealing material 350 .
  • the secondary sealing material 351 is also charged between the bottom face of the module case 201 and the lower face of the primary sealing material 350 .
  • the power module 100 has such a structure.
  • the power module 100 converts the power of the direct-current high-voltage output of a high-voltage rechargeable battery into the power of an alternating current high voltage output to function as an inverter for driving a motor, for example.
  • FIG. 3 is a schematic plan view of the mounting structure of the semiconductor chips.
  • FIG. 4 is an enlarged cross sectional view of region IV in FIG. 2 taken along line IV-IV in FIG. 3 . Note that, in FIG. 3 , the semiconductor chips are illustrated with the second lead frame 102 removed. In FIG. 4 , the components, such as the leads 111 , disposed on the outer side of region IV in FIG. 2 are omitted.
  • the first base plate, i.e., the first lead frame 101 , and the second base plate, i.e., the second lead frame 102 are formed by punching a metal plate.
  • materials such as copper, aluminum, and iron, can be used.
  • the first and the second lead frames 101 and 102 preferably have high coefficients of thermal conductivity. Thus, specifically, copper and aluminum materials are preferable, which have excellent coefficients of thermal conductivity.
  • the first and the second lead frames 101 and 102 are oppositely disposed with space from each other.
  • Four semiconductor chips 11 to 14 are disposed between the first and the second lead frames 101 and 102 .
  • four projections 103 are formed opposite to the respective semiconductor chips 11 to 14 .
  • the four projections 103 are disposed in a two-by-two matrix configuration.
  • the semiconductor chips 11 to 14 are in a thin rectangular parallelepiped shape, and configured of insulated-gate bipolar transistors (IGBT), for example.
  • the semiconductor chips 11 to 14 may include diodes and passive devices together with IGBTs.
  • the semiconductor chips 11 to 14 include one face f L , which is a lower face in FIG. 4 , and another face f U , which is a top face in FIG. 4 .
  • the collector electrode of the IGBT is formed, for example.
  • the emitter electrode of the IGBT and a plurality of control electrodes are formed on the one face f L of each of the semiconductor chips 11 to 14 .
  • the control electrodes are connected to the lead 111 by bonding wires.
  • the one face f L of each of the semiconductor chips 11 to 14 is soldered with a first solder 50 on the first lead frame 101 .
  • the another face f U of each of the semiconductor chips 11 to 14 is soldered to the projection 103 of the second lead frame 102 with a second solder 60 .
  • the projection 103 is formed in a rectangular shape slightly smaller than the sizes of the semiconductor chips 11 to 14 in a planar view.
  • the structure is provided in which the another face f U is soldered to the projection 103 of the second lead frame 102 .
  • the semiconductor chips 11 to 14 are disposed in a two-by-two matrix configuration.
  • solder materials of the first and the second solders 50 and 60 in addition to Sn-rich materials, Au, Zn—Al, and Al materials can be used.
  • materials containing a resin such as Ag paste, Cu paste, sintered Ag, and sintered Cu, can also be used. Materials containing a resin preferably have low viscosity.
  • the mounting structure of the semiconductor chips illustrated in FIGS. 3 and 4 is formed by procedures below, for example.
  • a solder material, which is to be hardened as the first solder 50 is supplied to the first lead frame 101 .
  • a sheet solder can be used.
  • methods can also be used, in which a solder paste is formed by printing, and in which a molten solder is supplied.
  • the semiconductor chips 11 to 14 are placed.
  • a solder material, which is to be hardened as the second solder 60 is supplied. The supply of this solder material can be similarly performed as the supply of the solder material, which is to be hardened as the first solder 50 .
  • the projections 103 are aligned with the solder material, which is to be hardened as the second solder 60 , and then the second lead frame 102 is placed on the solder material, which is to be hardened as the second solder 60 .
  • the first and the second lead frames 101 and 102 are heated with the second lead frame 2 pressed against the first lead frame 101 for soldering the semiconductor chips 11 to 14 to the first and the second lead frames 101 and 102 .
  • the mounting structure of the semiconductor chips 11 to 14 illustrated in FIGS. 3 and 4 is prepared.
  • the semiconductor chips 11 to 14 are not disposed in the center part of the first solder 50 .
  • the semiconductor chips 11 to 14 are disposed at positions close to the adjacent other semiconductor chips 11 to 14 , not in the center part.
  • Distances a to d in FIG. 3 are defined as below. Note that, four edges of the first lead frame, i.e., side ends E 1 to E 4 are as illustrated in FIG. 3 .
  • a distance between the semiconductor chip 11 and the semiconductor chip 12 i.e., a distance between the edges of the semiconductor chip 11 and the semiconductor chip 12 opposite to each other is defined as a;
  • a distance between the semiconductor chip 11 and the semiconductor chip 13 i.e., a distance between the edges of the semiconductor chip 11 and the semiconductor chip 13 opposite to each other is defined as b;
  • a distance between the left edge of the semiconductor chip 11 and the left side end E 1 of the first lead frame 101 is defined as c;
  • a distance between the upper edge of the semiconductor chip 11 and the upper side end E 2 of the first lead frame 10 is defined as d.
  • solder fillet 51 a of the semiconductor chip 11 and a solder fillet 52 a of the semiconductor chip 12 are formed between the semiconductor chip 11 and the semiconductor chip 12 .
  • solder fillet 51 b of the first semiconductor chip 11 and a solder fillet 53 b of the semiconductor chip 13 are formed between the semiconductor chip 11 and the semiconductor chip 13 .
  • the length of the solder fillet 51 a is equal to the length of the solder fillet 52 a
  • the length of the solder fillet 51 b is equal to the length of the solder fillet 53 b .
  • the lengths of the solder fillets 51 a and 52 a have to be a/2 or less
  • the lengths of the solder fillets 51 b and 53 b have to be b/2 or less.
  • the length of the solder fillet is defined as a length l from the edge of the semiconductor chip to the tip end of the solder fillet.
  • the semiconductor chips 11 to 14 are disposed at the positions close to the adjacent other semiconductor chips 11 to 14 , not in the center parts of four chip mounting regions almost equally divided on the first lead frame 101 .
  • the centers of four projections 103 of the second lead frame 102 are matched with the centers of the semiconductor chips 11 to 14 , which are not mounted in the centers of the chip mounting regions.
  • the distances a/2 and b/2 are shorter than the distances c and d. The shorter the distance between the semiconductor chips is, or the shorter the distance between the semiconductor chip and the side end of the base plate, the greater the possibility is that the semiconductor chips are short-circuited due to the overflow of the solder fillet or that the solder fillet overflows from the side end of the base plate.
  • the lengths of the solder fillets 51 a and 52 a formed on the edges adjacent to the other semiconductor chips 11 and 12 are formed shorter than the lengths of the solder fillets 51 c and 51 d formed on two edges of the semiconductor chip 11 adjacent to the side ends E 1 and E 2 of the first lead frame 101 .
  • the lengths of the solder fillets 51 c and 51 d are formed longer than the lengths of the solder fillets 51 a and 52 a .
  • the lengths of the solder fillets 51 b and 53 b formed on the edges adjacent to the other semiconductor chips 11 and 13 are formed shorter than the lengths of the solder fillets 51 c and 51 d formed on two edges of the semiconductor chip 11 adjacent to the side ends E 1 and E 2 of the first lead frame 101 .
  • the lengths of the solder fillets 51 c and 51 d are formed longer than the lengths of the solder fillets 51 b and 53 b .
  • the length of the solder fillet formed on the edge at a shorter distance is made shorter.
  • the length of the solder fillet 51 a is formed shorter than the length of the solder fillet 51 b.
  • the length of the solder fillet formed on the edge at a shorter distance may be formed shorter.
  • the length of the solder fillet 51 c may be formed shorter than the length of the solder fillet 51 d.
  • Overflows of solder in forming solder fillets are caused by increasing a pressure in solder to cause a swell of the solder in the solder fillet forming region due to a short length of the solder fillet forming region with respect to a predetermined solder volume.
  • the increased amount of the surface area of the solder is changed depending on the lengths of the solder fillets.
  • FIG. 5 show an example of the correlation between the length l of the solder fillet and the increased amount of the surface area of solder.
  • FIG. 5( a ) is a cross sectional view for illustrating the criteria of the solder structure of a semiconductor chip.
  • FIG. 5( b ) is a characteristic view of the relationship between the increased amount of the surface area of the solder fillet and the length of the solder fillet forming region.
  • the size of the chip is a 10-mm square.
  • a thickness t of the solder is 0.2 mm.
  • the increased amount of the surface area of the solder fillet in FIG. 5( b ) is the increased amount of the surface area of the solder fillet, which is derived in the case where the semiconductor chip is sunk from the surface of the solder by 0.05 mm.
  • the surface area of the solder is assumed that the solder fillet swells in an arc shape.
  • FIG. 5( b ) reveals that the longer the length l of the solder fillet forming region is, the smaller the increased amount of the surface area of the solder is. In other words, the shorter the length l of the solder fillet forming region is, the greater the increased amount of the surface area of the solder of the solder fillet is. As described above, the greater the increased amount of the surface area of the solder is, the greater energy necessary for the increase is. With the use of this phenomenon, energy applied to the solder material with the first solder 50 being molten in pressing the semiconductor chip 11 against the first lead frame 101 is consumed by increasing the surface areas of the solder fillets 51 c and 51 d having a long length l of the solder fillet forming region.
  • solder fillets 51 a and 51 b having a short length l of the solder fillet forming region i.e., overflows of solder from the solder fillet forming regions can be suppressed.
  • the semiconductor chips 11 to 14 and the projections 103 are disposed on the same center parts. In other words, the gaps between four edges of each of the semiconductor chips 11 to 14 and four edges of the projection 103 are almost equal.
  • the second solder 60 joining the semiconductor chips 11 to 14 to the projections 103 has a solder fillet 61 , which is formed on four edges of each of the semiconductor chips 11 to 14 in equal length.
  • the length of the solder fillet 61 can be formed shorter than the lengths of the solder fillets 51 a and 51 b . The reason is as below.
  • the semiconductor chips 11 to 14 are heated, pressed, and soldered, with the first lead frame 101 , the first solder, the semiconductor chips 11 to 14 , the second solder 60 , and the second lead frame 102 stacked.
  • both of the first and the second solders 50 and 60 are molten.
  • the first and the second solders 50 and 60 are formed separately from each other.
  • the relationship between the increased amount of the surface area of the solder fillet and the length of the solder fillet forming region has the relationship shown in FIG. 5( b ) .
  • the length of the solder fillet 61 is not necessarily shorter than the lengths of the solder fillets 51 a and 51 b.
  • the semiconductor chip 11 was described.
  • the semiconductor chips 12 to 14 are the same as the case of the semiconductor chip 11 .
  • the lengths of the solder fillets formed on the edges adjacent to the other semiconductor chips 11 to 14 are formed shorter than the lengths of the solder fillets formed on the edges adjacent to the side ends E 1 to E 4 of the first lead frame 101 .
  • the semiconductor chips 11 to 14 were soldered to the first lead frame 101 with the first solder 50 .
  • the lengths of the solder fillets formed on the edges adjacent to the side ends E 1 to E 4 of the first lead frame 101 were formed longer than the lengths of the solder fillets formed on the edges adjacent to the other semiconductor chips 11 to 14 .
  • FIG. 6 is a schematic plan view of a second embodiment of the present invention showing the mounting structure of semiconductor chips provided on a power module.
  • FIG. 7 is a cross sectional view taken along line VII-VII in FIG. 6 .
  • first and second lead frames 101 and 102 , semiconductor chips 11 to 14 , first and second solders 50 and 60 are members the same as the members of the first embodiment.
  • the second embodiment is different from the first embodiment is in that the semiconductor chips 11 to 14 are disposed at positions near the corners of the first lead frame 101 , not disposed in the center part of the first solder 50 .
  • the semiconductor chip 11 is taken up as an example for description.
  • the lengths of solder fillets 51 c and 51 d formed on two edges adjacent to side ends E 1 and E 2 of the first lead frame 101 are formed shorter than the length of a solder fillet 51 a formed on the edge of the semiconductor chip 11 adjacent to the semiconductor chip 12 and the length of a solder fillet 52 a formed on the edge of the semiconductor chip 12 adjacent to the semiconductor chip 11 .
  • the lengths of the solder fillets 51 a and 52 a formed on the semiconductor chips 11 and 12 are formed longer than the lengths of the solder fillets 51 c and 51 d formed on two edges of the semiconductor chip 11 .
  • the lengths of the solder fillets 51 c and 51 d formed on two edges of the semiconductor chip 11 adjacent to the side ends El and E 2 of the first lead frame 101 are formed shorter than a solder fillet 51 b formed on the edge of the semiconductor chip 11 adjacent to the semiconductor chip 13 and the length of a solder fillet 53 b formed on the edge of the semiconductor chip 13 adjacent to the semiconductor chip 11 .
  • the lengths of the solder fillets 51 b and 53 b formed on the semiconductor chips 11 and 13 are formed longer than the lengths of the solder fillets 51 c and 51 d formed on two edges of the semiconductor chip 11 .
  • the length of the solder fillet formed on the edge at a shorter distance is made shorter.
  • the length of the solder fillet 51 c is formed shorter than the length of the solder fillet 51 d.
  • the length of the solder fillet formed on the edge at a shorter distance may be made shorter.
  • the length of the solder fillet 51 a is formed shorter than the length of the solder fillet 51 b.
  • the relationship of a half of the distance a and a half of the distance b between the edges adjacent to the other semiconductor chips 12 to 14 to the distances c and d from the edges of the semiconductor chips 12 to 14 to the side ends E 1 to E 4 of the first lead frame 101 are similar to the case of the semiconductor chip 11 .
  • the lengths of the solder fillets formed on the edges of the semiconductor chips 12 to 14 are similar to the solder fillets formed on the edges of the semiconductor chip 11 .
  • the lengths of the solder fillets formed on the edges adjacent to the side ends E 1 to E 4 of the first lead frame 101 are formed shorter than the lengths of the solder fillets formed on the edges adjacent to the other semiconductor chips 11 to 14 .
  • the semiconductor chips 11 to 14 were soldered to the first lead frame 101 with the first solder 50 .
  • the lengths of the solder fillets formed on the edges adjacent to the other semiconductor chips 11 to 14 were formed longer than the lengths of the solder fillets formed on the edges adjacent to the side ends of the first lead frame 101 .
  • FIG. 8 is a cross sectional view of a third embodiment of the present invention showing the mounting structure of semiconductor chips provided on a power module.
  • FIG. 8 is a diagram of a region corresponding to FIG. 4 of the first embodiment of the power module.
  • a power module 100 according to the third embodiment is different from the first embodiment in that a recess 102 b is formed on an inner surface 102 a of a second lead frame 102 opposite to a first lead frame 101 .
  • the other configurations of the power module 100 according to the third embodiment are similar to those of the first embodiment.
  • solder fillets 51 c and 51 d are formed on the edges adjacent to side ends E 1 and E 2 of the first lead frame 101 .
  • the lengths of the solder fillets 51 c and 51 d are formed longer than the lengths of solder fillets 51 a and 52 a formed on the edges adjacent to the other semiconductor chips 11 and 12 .
  • solder easily overflows from the forming regions of the solder fillets 51 c and 51 d.
  • the recess 102 b is formed on the inner surface 102 a of the second lead frame 102 at a portion where the solder fillets 51 c and 52 c are opposite to each other.
  • the side ends E 1 and E 3 of the second lead frame 102 are described.
  • the recess 102 b is similarly formed on side ends E 2 and E 4 . As described above, when the length of the solder fillet forming region is long, solder easily overflows.
  • solder overflows from the forming regions of the solder fillets 51 c , 52 c , 51 d , and 52 d having a long length of the solder fillet forming region, and contacts the second lead frame 102 , sometimes causing a short circuit between the first and the second lead frames 101 and 102 .
  • the recess 102 b is formed on the second lead frame 102 corresponding to portions where solder easily overflows. Consequently, a short circuit between the first and the second lead frames 101 and 102 can be prevented.
  • the other structures of the third embodiment are the same as the structures of the first embodiment. Thus, effects the same as the effect (1) of the first embodiment are exerted.
  • the recess 102 b is formed on the second lead frame 102 at portions opposite to the solder fillets formed on the edges adjacent to the first lead frame 101 , i.e., long solder fillets. Consequently, even in the case where solder overflows from the forming regions of the long solder fillets, a short circuit between the first and the second lead frames 101 and 102 can be prevented.
  • FIG. 9 is a cross sectional view of a fourth embodiment of the present invention showing the mounting structure of semiconductor chips provided on a power module.
  • FIG. 9 is a diagram of a region corresponding to FIG. 7 of the second embodiment of the power module.
  • a power module 100 according to the fourth embodiment is different from the second embodiment in that a recess 102 c is formed on an inner surface 102 a of a second lead frame 102 opposite to a first lead frame 101 .
  • the other configurations of the power module 100 according to the fourth embodiment are similar to those of the second embodiment.
  • solder fillets 51 a and 52 a are formed on the edges of semiconductor chips 11 and 12 adjacent to the edges of the other semiconductor chips 11 and 12 .
  • the lengths of the solder fillets 51 a and 52 a are formed longer than the lengths of solder fillets 51 c and 51 d of the semiconductor chip 11 formed on the edges adjacent to side ends E 1 and E 2 of the first lead frame 101 .
  • solder easily overflows from the forming regions of the solder fillets 51 a and 52 a.
  • the recess 102 c is formed on the inner surface 102 a of the second lead frame 102 at portions opposite to the solder fillets 51 a and 52 a .
  • FIG. 9 the solder fillets 51 a and 52 a between the semiconductor chips 11 and 12 are described.
  • the recess 102 c is formed on the portions opposite to the solder fillets between the semiconductor chips 11 and 13 , the solder fillets between the semiconductor chips 12 and 14 , and the solder fillets between the semiconductor chips 13 and 14 .
  • the other structures of the fourth embodiment are the same as the structures of the second embodiment. Thus, an effect the same as the effect (1) of the second embodiment is exerted.
  • the recess 102 c is formed on the second lead frame 102 opposite to the solder fillets formed on the edge adjacent to the edge of the other semiconductor chips 11 to 14 , i.e., long solder fillets.
  • FIG. 10 is a schematic plan view of a fifth embodiment of the present invention showing the mounting structure of semiconductor chips provided on a power module.
  • a power module 100 according to the fifth embodiment includes three semiconductor chips 21 to 23 linearly arrayed.
  • First solders 50 fixing the semiconductor chips 21 to 23 are in a rectangular shape in a planar view, in which the length in the arraying direction, i.e., the length in the lateral direction is longer than the length in a direction orthogonal to the arraying direction, i.e., the length in the vertical direction.
  • the semiconductor chips 21 to 23 are in a square in a planar view.
  • the semiconductor chips 21 to 23 are disposed almost in the center part of the first solder 50 in the lateral direction and in the vertical direction.
  • Distances a to d in FIG. 10 are defined as below.
  • a distance from the edge of the semiconductor chip 21 adjacent to the semiconductor chip 22 to the edge of the semiconductor chip 22 adjacent to the semiconductor chip 21 is defined as a;
  • a distance from the edge of the semiconductor chip 21 adjacent to the conductor the chip 23 to the edge of the semiconductor chip 23 adjacent to the semiconductor chip 21 is defined as b;
  • a distance from the edge of the semiconductor chip 21 adjacent to a lower side end E 4 of a first lead frame 101 to the lower side end E 4 of the first lead frame 101 is defined as c;
  • a distance from the edge of the semiconductor chip 21 adjacent to an upper side end E 2 of the first lead frame 101 to the upper side end E 2 of the first lead frame 101 is defined as d.
  • distances a/2 and b/2 are shorter than the distances c and d.
  • the lengths of solder fillets 51 a and 52 a of the semiconductor chips 21 and 22 formed on the edges adjacent to the other semiconductor chips 21 and 22 are formed shorter than the lengths of solder fillets 51 c and 51 d formed on the edges of the semiconductor chip 21 adjacent to the side ends E 2 and E 4 of the first lead frame 101 .
  • the lengths of the solder fillets 51 c and 51 d formed on the semiconductor chip 21 are formed longer than the lengths of the solder fillets 51 a and 52 a formed on the semiconductor chips 21 and 22 .
  • the lengths of solder fillets 51 b and 53 b of the semiconductor chips 21 and 23 formed on the edges adjacent to the other semiconductor chips 21 and 23 are formed shorter than the lengths of the solder fillets 51 c and 51 d formed on the edges of the semiconductor chip 21 adjacent to the side ends E 2 and E 4 of the first lead frame 101 .
  • the lengths of the solder fillets 51 c and 51 d formed on the semiconductor chip 21 are formed longer than the lengths of the solder fillets 51 b and 53 b formed on the semiconductor chips 21 and 23 .
  • the length of the solder fillet formed on the edge at a shorter distance is made shorter.
  • the length of the solder fillet 51 a is made shorter than the length of the solder fillet 51 b.
  • the length of the solder fillet formed on the edge at a shorter distance may be made shorter.
  • the length of the solder fillet 51 c may be made shorter than the length of the solder fillet 51 d.
  • the lengths of the solder fillets 51 c and 51 d formed on the edges of the semiconductor chip 21 adjacent to the side ends E 2 and E 4 of the first lead frame 101 were formed longer than the lengths of the solder fillets 51 a and 51 b formed on the edges of the semiconductor chip 21 adjacent to the semiconductor chips 22 and 23 .
  • a recess 102 b maybe formed on an inner surface 102 a of a second lead frame 102 .
  • the recess 102 b may be formed on the inner surface 102 a of the second lead frame 102 at portions corresponding to the solder fillets 51 c and 51 d formed on the edge of the semiconductor chips 21 to 23 adjacent to the side ends E 2 and E 4 of the first lead frame 101 .
  • FIG. 11 is a diagram of an exemplary modification of the fifth embodiment illustrated in FIG. 10 .
  • the semiconductor chips 21 to 23 are arrayed in two rows.
  • the relationship between the lengths of the solder fillets 51 a to 51 d formed on the edges of the semiconductor chip 21 disposed in two rows is the same as the relationship described in FIG. 10 .
  • the exemplary modification of the fifth embodiment exerts the effect similar to the effect of the fifth embodiment.
  • the semiconductor chips 21 to 23 can also be formed in three rows or more.
  • the number of the semiconductor chips 21 to 23 disposed in each row can be four or more.
  • FIG. 12 is a schematic plan view of a sixth embodiment of the present invention showing the mounting structure of semiconductor chips provided on a power module.
  • a power module 100 includes three semiconductor chips 21 to 23 linearly arrayed. However, the semiconductor chips 21 to 23 are disposed at positions off the center part of a first solder 50 .
  • a distance b/2 and the distance c are shorter than the distances a and d.
  • the distance b/2 is almost equal to the distance c.
  • the distance a is almost equal to the distance d.
  • the lengths of solder fillets 51 b and 53 b of the semiconductor chips 21 and 23 formed on the edges adjacent to the other semiconductor chips 21 and 23 are almost equal to the length of a solder fillet 51 c formed on the edge of the semiconductor chip 21 adjacent to a side end E 4 of a first lead frame 101 .
  • the length of a solder fillet 51 a formed on the edge of the semiconductor chip 21 adjacent to the semiconductor chip 22 is almost equal to the length of a solder fillet 51 d formed on the edge of the semiconductor chip 21 adjacent to a side end E 2 of the first lead frame 101 .
  • the lengths of the solder fillets 51 b and 53 b formed on the semiconductor chips 21 and 23 and the length of the solder fillet 51 c formed on the semiconductor chip 21 are formed shorter than the lengths of the solder fillets 51 a and 51 d formed on the semiconductor chip 21 .
  • the lengths of the solder fillets 51 a and 51 d formed on the semiconductor chip 21 are formed longer than the lengths of the solder fillets 51 b and 53 b formed on the semiconductor chips 21 and 23 and the length of the solder fillet 51 c formed on the semiconductor chip 21 .
  • the length of the solder fillet 52 a formed on the edge of the semiconductor chip 22 adjacent to the semiconductor chip 21 is almost equal to the lengths of the solder fillets 51 b and 53 b.
  • the lengths of the solder fillets 51 a and 51 d formed on the semiconductor chip 21 are formed longer than the lengths of the solder fillets 51 b and 53 b formed between the semiconductor chip 21 and the semiconductor chip 23 .
  • the lengths of the solder fillets 51 a and 51 d formed on the semiconductor chip 21 are formed longer than the length of the solder fillet 51 c formed on the semiconductor chip 21 . Consequently, overflows of solder from the forming region of the solder fillet 51 c formed on the semiconductor chip 21 to the side end E 4 of the first lead frame 101 can be suppressed.
  • a recess 102 b or 102 c may be formed on an inner surface 102 a of a second lead frame 102 .
  • the recess 102 c or 102 b may be formed on the inner surface 102 a of the second lead frame 102 at portions corresponding to the solder fillet 51 a formed on the edge of the semiconductor chip 21 adjacent to the semiconductor chip 22 and the solder fillet 51 d formed on the edges of the semiconductor chip 21 adjacent to the side ends E 2 and E 4 of the first lead frame 101 .
  • the recess 102 b may be formed on the inner surface 102 a of the second lead frame 102 at portions corresponding to the edges of the semiconductor chips 22 and 23 adjacent to the side ends E 1 and E 2 , or E 2 and E 3 of the first lead frame 101 .
  • FIG. 13 is a diagram of a first exemplary modification of the sixth embodiment illustrated in FIG. 12 .
  • the semiconductor chips 21 to 23 illustrated in FIG. 12 are arrayed in two rows.
  • the relationship between the distances a to d between the semiconductor chips 21 to 23 adjacent to each other or the relationship between the distances a to d between the semiconductor chips 21 to 23 and the side ends E 1 to E 4 of the first lead frame 101 is the same as the sixth embodiment illustrated in FIG. 12 both in the first and second rows.
  • the relationship between the lengths of the solder fillets ( 51 a to 51 d , 52 a , 53 b , and the like) formed on four edges of each of the semiconductor chips 21 to 23 is also the same as the sixth embodiment illustrated in FIG. 12 both in the first and second rows.
  • the first exemplary modification also exerts the effect similar to the effect of the sixth embodiment illustrated in FIG. 12 .
  • the semiconductor chips 21 to 23 can also be formed in three rows or more.
  • the number of the semiconductor chips 21 to 23 disposed in each row can be four or more.
  • FIG. 14 is a diagram of a second exemplary modification of the sixth embodiment illustrated in FIG. 12 .
  • the semiconductor chips 21 to 23 illustrated in FIG. 12 are arrayed in two rows. However, unlike the first exemplary modification illustrated in FIG. 13 , the semiconductor chips 21 to 23 in the second row are disposed upside down with respect to the semiconductor chips 21 to 23 in the first row.
  • the relationship between the distances a to d between the semiconductor chips 21 to 23 adjacent to each other or the relationship between the distances a to d between the semiconductor chips 21 to 23 and the side ends E 1 to E 4 of the first lead frame 101 is the same as the sixth embodiment illustrated in FIG. 12 both in the first and second rows.
  • the relationship between the lengths of the solder fillets ( 51 a to 51 d , 52 a , 53 b , and the like) formed on four edges of each of the semiconductor chips 21 to 23 is also the same as the sixth embodiment illustrated in FIG. 12 both in the first and second rows. Consequently, the second exemplary modification also exerts the effect similar to the effect of the sixth embodiment illustrated in FIG. 12 .
  • a configuration may be possible in which the semiconductor chips 21 to 23 in three rows or more are provided by alternately adding the arrangement of the semiconductor chips 21 to 23 in the first and the second rows.
  • the number of the semiconductor chips 21 to 23 disposed in each row can be four or more.
  • FIG. 15 is a schematic plan view of a seventh embodiment of the present invention showing the mounting structure of semiconductor chips provided on a power module.
  • a power module 100 includes three semiconductor chips 21 to 23 linearly arrayed.
  • the semiconductor chips 21 to 23 are disposed almost in the center part of the first solder 50 in the lateral direction and in the vertical direction.
  • first solders 50 soldering the semiconductor chips 21 to 23 are in a rectangular shape in which the length in the lateral direction is longer than the length in the vertical direction.
  • the seventh embodiment has configurations below.
  • the distance a from the edge of the semiconductor chip 21 adjacent to the semiconductor chip 22 to the edge of the semiconductor chip 22 adjacent to the semiconductor chip 21 is almost equal to the distance b from the edge of the semiconductor chip 21 adjacent to the semiconductor chip 23 to the edge of the semiconductor chip 23 adjacent to the semiconductor chip 21 .
  • the distance d from the edge of the semiconductor chip 21 adjacent to a side end E 2 of a first lead frame 101 to the side end E 2 of the first lead frame 101 is almost equal to the distance c from the edge of the semiconductor chip 21 adjacent to a side end E 4 of the first lead frame 101 to the side end E 4 of the first lead frame 101 .
  • the distances c and d are formed shorter than distances a/2 and b/2.
  • the lengths of solder fillets 51 a and 52 a of the semiconductor chips 21 and 22 formed on the edges adjacent to the other semiconductor chips 21 and 22 are formed almost equal to the lengths of solder fillets 51 b and 53 b of the semiconductor chips 21 and 22 formed on the edges adjacent to the other semiconductor chips 21 and 23 .
  • the lengths of solder fillets 51 c and 51 d formed on the edges of the semiconductor chip 21 adjacent to the side ends E 4 and E 2 of the first lead frame 101 are formed almost equal to each other.
  • the solder fillets 51 a , 51 b , 52 a , and 53 b are formed longer than the solder fillets 51 c and 51 d.
  • the solder of the solder fillets 51 a , 51 b , 52 a , and 53 b more easily overflows from the solder fillet forming regions than the solder of the solder fillets 51 c and 51 d does. Consequently, overflows of solder from the forming regions of the solder fillets 51 c and 51 d to the side ends E 2 and E 4 of the first lead frame 101 are suppressed.
  • a recess 102 c may be formed on an inner surface 102 a of a second lead frame 102 .
  • the recess 102 c maybe formed on the inner surface 102 a of the second lead frame 102 at portions corresponding to the solder fillets 51 a , 51 b , 52 a , and 53 b of the semiconductor chips 21 to 23 formed on the edges adjacent to the other semiconductor chips 21 to 23 .
  • FIG. 16 is a diagram of an exemplary modification of the seventh embodiment illustrated in FIG. 15 .
  • the semiconductor chips 21 to 23 are arrayed in two rows.
  • the relationship between the lengths of the solder fillets 51 a to 51 d formed on the edges of the semiconductor chip 21 disposed in two rows is the same as the relationship described in FIG. 15 .
  • the exemplary modification of the seventh embodiment exerts the effect similar to the effect of the seventh embodiment.
  • the semiconductor chips 21 to 23 can also be formed in three rows or more.
  • the number of the semiconductor chips 21 to 23 disposed in each row can be four or more.
  • FIG. 17 is a diagram of a first effect of the present invention showing the frequency of occurrence of short circuits between semiconductor chips according to Example 1 of the present invention.
  • Example 1 has a solder structure of a first lead frame 101 , a second lead frame 102 , and semiconductor chips 11 to 14 shown in FIGS. 3 and 4 as the first embodiment.
  • the first and the second lead frames 101 and 102 were formed of copper plates.
  • Four projections 103 were formed on the second lead frame 102 , and the four semiconductor chips 11 to 14 were mounted corresponding to the projections 103 .
  • the semiconductor chips 11 to 14 have a rectangular parallelepiped shape of a 10 mm square in size.
  • Distances (a, b, and the like) between the semiconductor chips 11 to 14 adjacent to each other were set to 1.0 mm.
  • Distances (c, d, and the like) from the semiconductor chips 11 to 14 to side ends E 1 to E 4 of the first lead frame 101 were set to 2.0 mm.
  • the lengths of solder fillets ( 51 a , 51 b , 52 a , 53 b , and the like) of the semiconductor chips 11 to 14 formed on the edges adjacent to the other semiconductor chips 11 to 14 were set to 0.3 mm.
  • the lengths of solder fillets ( 51 c , 51 d , and the like) formed on the edges of the semiconductor chips 11 to 14 adjacent to the side ends E 1 to E 4 of the first lead frame 101 were set to 1.0 mm.
  • solder 50 a sheet of Sn3Ag0.5Cu solder was used.
  • a vacuum reflow device was used for reflow, and connected using a temperature profile with a peak at a temperature of 250° C.
  • the lengths of solder fillets ( 51 a , 51 b , 52 a , 53 b , and the like) of the semiconductor chips 11 to 14 formed on the edges adjacent to the other semiconductor chips 11 to 14 were set to 0.3 mm.
  • the lengths of solder fillets ( 51 c , 51 d , and the like) formed on the edges of the semiconductor chips 11 to 14 adjacent to side ends E 1 to E 4 of the first lead frame 101 were set to 0.3 mm. In other words, the lengths of the solder fillets formed on four edges of each of the semiconductor chips 11 to 14 were all set to 0.3 mm.
  • Example 1 and Comparative Example 1 were prepared for 20 devices each. On Example 1 and Comparative Example 1, the number of occurrences of short circuits between the semiconductor chips 11 to 14 and the number of occurrences of overflows of solder from the solder fillet forming regions to the side ends of the first lead frame 101 in the semiconductor chips 11 to 14 were checked. The result is shown in FIG. 17 .
  • Comparative Example 1 i.e., in the mounting structure in which the lengths of the solder fillets formed on four edges of each of the semiconductor chips 11 to 14 were all formed in 0.3 mm, a short circuit occurred between the semiconductor chips 11 to 14 in seven out of 20 devices.
  • Example 1 i.e., in the mounting structure in which the lengths of the solder fillets ( 51 a , 51 b , 52 a , 53 b , and the like) of the semiconductor chips 11 to 14 formed on the edges adjacent to the other semiconductor chips 11 to 14 were set to 0.3 mm and the lengths of the solder fillets ( 51 c , 51 d , and the like) formed on the edges of the semiconductor chips 11 to 14 adjacent to the side ends of the first lead frame 101 were set to 1.0 mm, no short circuit occurred between the semiconductor chips 11 to 14 in zero out of 20 devices.
  • Example 1 both in Example 1 and Comparative Example 1, the number of occurrences of overflows of solder from the solder fillets formed on the semiconductor chips 11 to 14 to the side ends E 1 to E 4 of the first lead frame 101 was zero out of 20 devices.
  • Example 1 of the present invention it was confirmed that overflows of solder from the forming regions of the solder fillets of the semiconductor chips 11 to 14 formed on the edges adjacent to the other semiconductor chips 11 to 14 were suppressed and a short circuit between the semiconductor chips 11 to 14 could be prevented.
  • FIG. 18 is a diagram of a second effect of the present invention showing the frequency of occurrence of short circuits between semiconductor chips according to Example 2 of the present invention.
  • Example 2 has a solder structure of first and second lead frames 101 and 102 , and semiconductor chips 11 to 14 of the second embodiment illustrated in FIGS. 6 and 7 .
  • the first and second lead frames 101 and 102 were formed of copper plates.
  • Four projections 103 were formed on the second lead frame 102 , and the four semiconductor chips 11 to 14 were mounted corresponding to the projections 103 .
  • the semiconductor chips 11 to 14 have a rectangular parallelepiped shape of a 10 mm square in size.
  • Distances (a, b, and the like) between the semiconductor chips 11 to 14 adjacent to each other were set to 3.0 mm.
  • Distances (c, d, and the like) from the semiconductor chips 11 to 14 to side ends E 1 to E 4 of the first lead frame 101 were set to 1.0 mm.
  • the lengths of solder fillets ( 51 a , 51 b , 52 a , 53 b , and the like) of the semiconductor chips 11 to 14 formed on the edges adjacent to the other semiconductor chips 11 to 14 were set to 1.0 mm.
  • the lengths of solder fillets ( 51 c , 51 d , and the like) formed on the edges of the semiconductor chips 11 to 14 adjacent to the side ends E 1 to E 4 of the first lead frame 101 were set to 0.3 mm.
  • solder 50 a sheet of Sn3Ag0.5Cu solder was used.
  • a vacuum reflow device was used for reflow, and connected using a temperature profile with a peak at a temperature of 250° C.
  • the lengths of solder fillets ( 51 a , 51 b , 52 a , 53 b , and the like) of the semiconductor chips 11 to 14 formed on the edges adjacent to the other semiconductor chips 11 to 14 were set to 0.3 mm.
  • the lengths of solder fillets ( 51 c , 51 d b, and the like) formed on the edges of the semiconductor chips 11 to 14 adjacent to side ends E 1 to E 4 of the first lead frame 101 were set to 0.3 mm. In other words, the lengths of the solder fillets formed on four edges of each of the semiconductor chips 11 to 14 were all set to 0.3 mm.
  • Example 2 and Comparative Example 2 were prepared for 20 devices each.
  • Example 2 and Comparative Example 2 the number of occurrences of short circuits between the semiconductor chips 11 to 14 and the number of occurrences of overflows of solder from the solder fillet forming regions to the side ends of the first lead frame 101 in the semiconductor chips 11 to 14 were checked. The result is shown in FIG. 18 .
  • Comparative Example 2 i.e., in the mounting structure in which the lengths of the solder fillets formed on four edges of each of the semiconductor chips 11 to 14 were set to 0.3 mm, solder overflowed from the forming regions of the solder fillets formed on the semiconductor chips 11 to 14 to the side ends E 1 to E 4 of the first lead frame 101 in 11 out of 20 devices.
  • Example 2 i.e., in the mounting structure in which the lengths of the solder fillets of the semiconductor chips 11 to 14 formed on the edges adjacent to the other semiconductor chips 11 to 14 were set to 1.0 mm and the lengths of the solder fillets formed on the edges of the semiconductor chips 11 to 14 adjacent to the side ends E 1 to E 4 of the first lead frame 101 were set to 0.3 mm, no solder overflowed from the forming regions of the solder fillets formed on the semiconductor chips 11 to 14 to the side ends E 1 to E 4 of the first lead frame 101 in zero out of 20 devices.
  • Example 2 both in Example 2 and Comparative Example 2, the number of occurrences of faults, which are short circuits between the semiconductor chips 11 to 14 , was zero.
  • Example 2 of the present invention overflows of solder from the forming regions of the solder fillets formed on the edges of the semiconductor chips 11 to 14 adjacent to the side ends E 1 to E 4 of the first lead frame 101 to the side ends E 1 to E 4 of the first lead frame 101 can be suppressed.
  • Example 1 an example was shown in which the lengths of the solder fillets ( 51 a , 51 b , 52 a , 53 b , and the like) of the semiconductor chips 11 to 14 formed on the edges adjacent to the other semiconductor chips 11 to 14 were set to 0.3 mm and the lengths of the solder fillets ( 51 c , 51 d , and the like) formed on the edges of the semiconductor chips 11 to 14 adjacent to the side ends E 1 to E 4 of the first lead frame 101 were set to 1.0 mm.
  • the lengths of the solder fillets are examples.
  • the lengths of the solder fillets ( 51 a , 51 b , 52 a , 53 b , and the like) of the semiconductor chips 11 to 14 formed on the edges adjacent to the other semiconductor chips 11 to 14 may be shorter than 0.3 mm or longer than 0.3 mm.
  • the lengths of the solder fillets ( 51 a , 51 b , and the like) formed on two opposite edges of the semiconductor chips 11 to 14 adjacent to each other may be different from each other.
  • the lengths of the solder fillets ( 51 c , 51 d , and the like) formed on the edges of the semiconductor chips 11 to 14 adjacent to the side ends E 1 to E 4 of the first lead frame 101 may be shorter than 1.0 mm or longer than 1.0 mm.
  • the lengths of the solder fillets ( 51 c , 51 , and the like) formed on two edges of the semiconductor chips 11 to 14 adjacent to the side ends E 1 to E 4 of the first lead frame 101 may be different from each other.
  • Example 2 an example was shown in which the lengths of the solder fillets ( 51 a , 51 b , 52 a , 53 b , and the like) of the semiconductor chips 11 to 14 formed on the edges adjacent to the other semiconductor chips 11 to 14 were set to 1.0 mm and the lengths of the solder fillets ( 51 c , 51 d , and the like) formed on the edges of the semiconductor chips 11 to 14 adjacent to the side ends E 1 to E 4 of the first lead frame 101 were set to 0.3 mm.
  • the lengths of the solder fillets are examples.
  • the lengths of the solder fillets ( 51 a , 51 b , 52 a , 53 b , and the like) of the semiconductor chips 11 to 14 formed on the edges adjacent to the other semiconductor chips 11 to 14 may be shorter than 1.0 mm or longer than 1.0 mm.
  • the lengths of the solder fillets ( 51 a , 51 b , and the like) formed on edges of the semiconductor chips 11 to 14 adjacent to edges of the other semiconductor chips 11 to 14 may be different from each other.
  • the lengths of the solder fillets ( 51 c , 51 d , and the like) formed on the edges of the semiconductor chips 11 to 14 adjacent to the side ends E 1 to E 4 of the first lead frame 101 may be shorter than 0.3 mm or longer than 0.3 mm.
  • the lengths of the solder fillets ( 51 c , 51 , and the like) formed on two edges of the semiconductor chips 11 to 14 adjacent to the side ends of the first lead frame 101 may be different from each other.
  • a solder wetting prevention structure for preventing solder wetting may be formed around regions in which solder fillets are formed.
  • the solder wetting prevention structure can be formed, for example, by coating a solder resist, by dimpling, by oxidation treatment using a laser and the like, or by chemical roughening and the like.
  • the first to the seventh embodiments may be selectively combined.
  • a power module only has to have a configuration in which among a half of a distance from a first edge of a first semiconductor chip to one edge of a second semiconductor chip adjacent to the first edge of the first semiconductor chip, a half of a distance from a second edge of the first semiconductor chip to one edge of a third semiconductor chip adjacent to the second edge of the first semiconductor chip, and a distance from at least one of a third edge or a fourth edge of the first semiconductor chip to a side end of a base plate, the length of a solder fillet formed on the edge of the first semiconductor chip at the shortest distance is the shortest length.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Die Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
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CN112151565B (zh) * 2019-06-27 2023-01-24 成都辰显光电有限公司 微发光二极管显示面板的制造方法
CN111524883B (zh) 2020-04-29 2022-09-20 业成科技（成都）有限公司 膜内电子组件及其制备方法
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JP2016146398A (ja) 2016-08-12
US20180005986A1 (en) 2018-01-04
DE112015005593B4 (de) 2025-03-06
JP6276721B2 (ja) 2018-02-07
DE112015005593T5 (de) 2017-09-28
WO2016125390A1 (ja) 2016-08-11

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