US9936575B2 - Resin multilayer substrate and component module - Google Patents

Resin multilayer substrate and component module Download PDF

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US9936575B2
US9936575B2 US15/160,190 US201615160190A US9936575B2 US 9936575 B2 US9936575 B2 US 9936575B2 US 201615160190 A US201615160190 A US 201615160190A US 9936575 B2 US9936575 B2 US 9936575B2
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resin layer
resin
multilayer substrate
conductive pattern
conductive
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US20160270221A1 (en
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Yoshihito OTSUBO
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Murata Manufacturing Co Ltd
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Murata Manufacturing Co Ltd
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0277—Bendability or stretchability details
    • H05K1/028—Bending or folding regions of flexible printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0313—Organic insulating material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4632—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating thermoplastic or uncured resin sheets comprising printed circuits without added adhesive materials between the sheets
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking
    • H01L2924/35121—Peeling or delaminating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0104—Properties and characteristics in general
    • H05K2201/0129—Thermoplastic polymer, e.g. auto-adhesive layer; Shaping of thermoplastic polymer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components

Definitions

  • the present invention relates to a resin multilayer substrate and a component module.
  • a resin multilayer substrate is fabricated by stacking a single-sided copper clad sheet, a double-sided copper clad sheet, and the like.
  • WO2011/108308 discloses an example of a multilayer substrate incorporating components.
  • WO2012/124421 discloses an example of a multilayer substrate having a surface on which components are mounted.
  • a copper foil and a resin sheet are not bonded by chemical bonding such as an adhesive. Accordingly, the joining strength between the copper foil and the resin sheet is relatively weak. Therefore, there have been cases where the copper foil peeled off from the resin sheet by a certain trigger after completion of an assembly as a thermoplastic resin multilayer substrate. Accordingly, a problem can occur in the junction performance between the resin multilayer substrate and a mother substrate, and between the resin multilayer substrate and incorporated components or mounted components, and a problem could occur also in the reliability. Particularly, a copper foil arranged on the main surface of the resin multilayer substrate is exposed to the outside, which poses a problem that such a copper foil is relatively more likely to peel off.
  • it is an anchor effect that mainly supports a junction between a copper foil and a resin sheet.
  • the anchor effect is achieved.
  • the surface roughness of the copper foil will tend to decrease, so that it becomes difficult to achieve the anchor effect. Accordingly, it becomes necessary to improve the adhesion strength by a method other than that for increasing the joining strength by the anchor effect.
  • the “copper foil” used herein is not limited to a copper foil, but can be a metal foil in general.
  • preferred embodiments of the present invention provide a resin multilayer substrate and a component module, by which adhesion strength between a conductive pattern and a resin layer is enhanced by an effect other than the anchor effect.
  • a resin multilayer substrate includes a first resin layer including a main surface on a first side; a conductive pattern that covers a portion of the main surface of the first resin layer; a conductive via that extends through the first resin layer so as to be connected to the conductive pattern; and a second resin layer that is overlaid on the first side of the first resin layer.
  • the second resin layer includes an opening through which the conductive pattern is partially exposed so as to include a projected area of the conductive via onto the conductive pattern.
  • the opening includes an inner peripheral edge including a first portion that is spaced from the conductive via by a first distance; and a second portion that is spaced from the conductive via by a second distance longer than the first distance.
  • the conductive pattern has a length that starts from the inner peripheral edge of the opening to outside and extends under the second resin layer. The length of the conductive pattern at the second portion is greater than the length of the conductive pattern at the first portion.
  • the adhesion strength between a conductive pattern and a resin layer is enhanced by an effect other than the anchor effect. Also, since the conductive pattern does not have to be excessively increased in size, the design flexibility such as a conductive pattern arrangement is able to be improved.
  • FIG. 1 is a plan view of a resin multilayer substrate according to a first preferred embodiment of the present invention.
  • FIG. 2 is a cross-sectional view of the resin multilayer substrate according to the first preferred embodiment of the present invention.
  • FIG. 3 is a plan view of a resin multilayer substrate according to a second preferred embodiment of the present invention.
  • FIG. 4 is a cross-sectional view of the resin multilayer substrate according to the second preferred embodiment of the present invention.
  • FIG. 5 is a plan view of a resin multilayer substrate according to a third preferred embodiment of the present invention.
  • FIG. 6 is a cross-sectional view of the resin multilayer substrate according to the third preferred embodiment of the present invention.
  • FIG. 7 is an explanatory diagram showing the state where the resin multilayer substrate according to the third preferred embodiment of the present invention is bent.
  • FIG. 8 is a plan view of a resin multilayer substrate according to a fourth preferred embodiment of the present invention.
  • FIG. 9 is a cross-sectional view of the resin multilayer substrate according to the fourth preferred embodiment of the present invention.
  • FIG. 10 is an explanatory diagram showing the state where the resin multilayer substrate according to the fourth preferred embodiment of the present invention.
  • FIG. 11 is a plan view of a resin multilayer substrate according to a fifth preferred embodiment of the present invention.
  • FIG. 12 is a cross-sectional view of the resin multilayer substrate according to the fifth preferred embodiment of the present invention.
  • FIG. 13 is an explanatory diagram showing the state where the resin multilayer substrate according to the fifth preferred embodiment of the present invention is bent.
  • FIG. 14 is a plan view of a resin multilayer substrate according to a sixth preferred embodiment of the present invention.
  • FIG. 15 is an explanatory diagram showing the manner in which a component is mounted on the resin multilayer substrate according to the sixth preferred embodiment of the present invention.
  • FIG. 16 is a cross-sectional view showing the state after the component has been mounted on the resin multilayer substrate according to the sixth preferred embodiment of the present invention, and also shows a cross-sectional view of a component module according to a seventh preferred embodiment of the present invention.
  • FIG. 1 shows a plan view of a resin multilayer substrate 101 in the present preferred embodiment
  • FIG. 2 shows a cross-sectional view thereof.
  • Resin multilayer substrate 101 includes a first resin layer 21 including a main surface 21 u on a first side 91 ; a conductive pattern 7 defined by a metal foil and that covers a portion of main surface 21 u of first resin layer 21 ; a conductive via 6 that passes through first resin layer 21 so as to be connected to conductive pattern 7 ; and a second resin layer 22 that is overlaid on first side 91 of first resin layer 21 .
  • Second resin layer 22 is provided with an opening 8 through which conductive pattern 7 is partially exposed so as to include a projected area of conductive via 6 onto conductive pattern 7 .
  • the internal peripheral edge of opening 8 includes: a first portion 31 that is spaced from conductive via 6 by a first distance D 1 ; and a second portion 32 that is spaced from conductive via 6 by a second distance D 2 longer than first distance D 1 .
  • conductive pattern 7 has a length L 1 that starts from the inner peripheral edge of opening 8 to the outside and extends under second resin layer 22 .
  • conductive pattern 7 has a length L 2 that starts from the inner peripheral edge of opening 8 to the outside and extends under second resin layer 22 . In this case, length L 2 is greater than length L 1 .
  • the resin multilayer substrate 101 can be obtained, for example, according to a method described below.
  • a plurality of resin layers (sheets) are prepared.
  • the contents equivalent to a plurality of resin layers may be processed into one large-sized sheet, which is then divided so that a plurality of resin layers may be obtained.
  • the opening 8 may be provided by stacking a second resin layer having an opening provided in advance by means of punching, laser beam machining or the like, or by partially removing the resin layer by means of laser beam machining or the like after formation of the stacked body.
  • second resin layer 22 an area in the vicinity of the outer edge of conductive pattern 7 is covered by second resin layer 22 . Accordingly, conductive pattern 7 is pressed by second resin layer 22 , so that this conductive pattern 7 is less likely to peel off. If peeling occurs, it goes without saying that conductive pattern 7 typically peels off from its outer edge as a starting point. Therefore, second resin layer 22 presses the area in the vicinity of the outer edge of conductive pattern 7 so as to cover the area, with the result that peeling of the conductive pattern is effectively suppressed. In other words, the adhesion strength between conductive pattern 7 and the resin layer is enhanced by an effect other than the anchor effect. Particularly at second portion 32 of the inner peripheral edge of opening 8 that is relatively farther away from conductive via 6 , second resin layer 22 covers a relatively large area in the vicinity of the outer edge of conductive pattern 7 .
  • conductive pattern 7 and conductive via 6 are electrically and mechanically joined to each other.
  • the adhesion strength at this junction is greater than the adhesion strength at the junction obtained by the anchor effect between conductive pattern 7 and first resin layer 21 that defines and functions as a resin layer. Therefore, conductive pattern 7 is less likely to peel off from the resin layer in the vicinity of the region provided with conductive via 6 as compared with other regions. Specifically, conductive pattern 7 is relatively less likely to peel off at first portion 31 of the inner peripheral edge of opening 8 that is located on the side closer to conductive via 6 than at second portion 32 of the inner peripheral edge of opening 8 that is located on the side farther away from conductive via 6 .
  • conductive pattern 7 is relatively more likely to peel off at second portion 32 that is located on the side farther away from conductive via 6 .
  • second resin layer 22 is to cover a relatively large area in the vicinity of the outer edge of conductive pattern 7 . Accordingly, the adhesion strength at a portion that has been conventionally more likely to peel off is effectively compensated for, so that peeling of the conductive pattern is effectively suppressed or prevented.
  • second resin layer 22 covers a relatively small area in the vicinity of the outer edge of conductive pattern 7 as compared with second portion 32 .
  • conductive pattern 7 is efficiently arranged while effectively suppressing or preventing peeling of conductive pattern 7 . Therefore, the design flexibility of the conductive pattern in resin multilayer substrate 101 is improved.
  • the joining strength is able to be ensured even if the size of conductive pattern 7 serving as a land electrode is relatively small.
  • the present preferred embodiment provides a structure in which conductive pattern 7 is exposed through opening 8 provided in second resin layer 22 as an uppermost layer. Accordingly, it becomes possible to suppress or prevent a short circuit caused when solder used for electrical connection to conductive pattern 7 overflows into an undesirable portion.
  • the conductive pattern 7 and the upper surface of second resin layer 22 define and function as an uppermost surface, so that the coplanarity of resin multilayer substrate 101 is improved as a whole.
  • opening 8 preferably has a rectangular or substantially rectangular shape and has four sides.
  • a portion of one side of this rectangle that is closest to conductive via 6 is selected as first portion 31 while a portion of another side of this rectangle that is closest to conductive via 6 is selected as second portion 32 .
  • the side including first portion 31 and the side including second portion 32 are two sides opposite to each other, but first portion 31 and second portion 32 are not necessarily selected from such two sides opposite to each other.
  • the shape of opening 8 is not limited to a rectangle but may be another shape.
  • first portion 31 and second portion 32 each are located in the middle of a linear-shaped side in the present preferred embodiment, the side does not have to be a linear-shaped line, but may be a curved line.
  • FIG. 3 shows a plan view of a resin multilayer substrate 102 in the present preferred embodiment
  • FIG. 4 shows a cross-sectional view thereof.
  • conductive via 6 is located not in the center of opening 8 but at a position spaced from the center, as seen in plan view.
  • conductive via 6 is located in the center of opening 8 as seen in plan view. Also in this case, the same applies as in the first preferred embodiment.
  • Resin multilayer substrate 102 in the present preferred embodiment includes a first resin layer 21 including a main surface 21 u on a first side 91 ; a conductive pattern 7 defined by a metal foil and that covers a portion of main surface 21 u of first resin layer 21 ; a conductive via 6 that extends through first resin layer 21 so as to be connected to conductive pattern 7 ; and a second resin layer 22 that is overlaid on first side 91 of first resin layer 21 .
  • Second resin layer 22 includes an opening 8 through which conductive pattern 7 is partially exposed so as to include a projected area of conductive via 6 onto conductive pattern 7 .
  • the inner peripheral edge of opening 8 includes a first portion 33 that is spaced from conductive via 6 by a first distance D 3 , and a second portion 34 that is spaced from conductive via 6 by a second distance D 4 longer than first distance D 3 .
  • conductive pattern 7 has a length L 3 that starts from the inner peripheral edge of opening 8 to the outside and extends under second resin layer 22 .
  • conductive pattern 7 has a length L 4 that starts from the inner peripheral edge of opening 8 to the outside and extends under second resin layer 22 . In this case, length L 4 is greater than length L 3 .
  • opening 8 preferably has a rectangular or substantially rectangular shape, in which a side including first portion 33 and a side including second portion 34 correspond to adjacent two sides arranged at a right angle.
  • the present preferred embodiment also achieves the same effects as those in the first preferred embodiment.
  • FIG. 5 shows a plan view of a resin multilayer substrate 103 in the present preferred embodiment
  • FIG. 6 shows a cross-sectional view thereof.
  • Resin multilayer substrate 103 includes a configuration similar to the first or second preferred embodiment. However, resin multilayer substrate 103 has a configuration different from the configuration as having been described in the first or second preferred embodiment in the following points.
  • Resin multilayer substrate 103 includes a bending portion 9 provided so as to be adjacent to opening 8 as seen in plan view. As seen in plan view, the inner peripheral edge of opening 8 includes a non-bending portion-side portion 35 located on the side where bending portion 9 is not located; and a bending portion-side portion 36 located on the side where bending portion 9 is located.
  • conductive pattern 7 has a length L 5 that starts from the inner peripheral edge of opening 8 to the outside and extends under second resin layer 22 .
  • conductive pattern 7 has a length L 6 that starts from the inner peripheral edge of opening 8 to the outside and extends under second resin layer 22 . In this case, length L 6 is greater than length L 5 .
  • resin multilayer substrate 103 is repeatedly or continuously bent as shown by an arrow 92 . Due to the action of this bending moment, resin multilayer substrate 103 is bent at bending portion 9 and turned into a state as shown in FIG. 7 . In the case where such bending portion 9 is provided, conductive pattern 7 is more likely to peel off, than before bending, from the resin layer by the bending moment occurring during bending.
  • second resin layer 22 covers a relatively large area in the vicinity of the outer edge of conductive pattern 7 . Accordingly, the adhesion strength between conductive pattern 7 and the resin layer is enhanced by an effect other than the mere anchor effect. Therefore, peeling of conductive pattern 7 is effectively suppressed or prevented even when bending is applied.
  • second resin layer 22 covers a relatively small area in the vicinity of the outer edge of conductive pattern 7 . Accordingly, conductive pattern 7 is efficiently arranged.
  • FIG. 8 shows a plan view of a resin multilayer substrate 104 in the present preferred embodiment
  • FIG. 9 shows a cross-sectional view thereof.
  • Resin multilayer substrate 104 basically includes a configuration as having been described in the third preferred embodiment. However, resin multilayer substrate 104 has a configuration different from the configuration as having been described in the third preferred embodiment in the following points. Resin multilayer substrate 104 includes a bending portion-side portion 36 , in which a third resin layer 23 is overlaid on first side 91 of second resin layer 22 so as to at least partially cover a region in which conductive pattern 7 extends under second resin layer 22 .
  • resin multilayer substrate 104 is repeatedly or continuously bent as shown by an arrow 92 . Due to the action of this bending moment, resin multilayer substrate 104 is bent at bending portion 9 and turned into a state shown in FIG. 10 .
  • third resin layer 23 is overlaid at bending portion-side portion 36 as described above. Accordingly, peeling between second resin layer and conductive pattern 7 occurring at bending portion-side portion 36 is suppressed or prevented, so that the adhesion strength between the conductive pattern and the resin layer is enhanced.
  • FIG. 11 shows a plan view of a resin multilayer substrate 105 in the present preferred embodiment
  • FIG. 12 shows a cross-sectional view thereof.
  • Resin multilayer substrate 105 basically includes a configuration as having been described in the third preferred embodiment.
  • conductive via 6 is located in the center of opening 8 as seen in plan view.
  • conductive via 6 is located not in the center of opening 8 but at a position in the inner region of opening 8 that is farther away from bending portion 9 . In other words, conductive via 6 is located at a position closer to non-bending portion-side portion 35 .
  • resin multilayer substrate 105 is repeatedly or continuously bent as shown by an arrow 92 . Due to the action of this bending moment, resin multilayer substrate 105 is bent at bending portion 9 and turned into a state shown in FIG. 13 .
  • the present preferred embodiment also achieves the same effects as those in the third preferred embodiment.
  • FIG. 14 shows a plan view of a resin multilayer substrate 106 in the present preferred embodiment.
  • FIG. 15 shows the state immediately before component 3 is mounted on resin multilayer substrate 106 .
  • Resin multilayer substrate 106 is shown in sectional view in FIG. 15 .
  • Resin multilayer substrate 106 includes a first resin layer 21 including a main surface 21 u on a first side 91 ; a plurality of conductive patterns 7 each defined by a metal foil and located on main surface 21 u of first resin layer 21 so as to be joined to a product located on first side 91 of first resin layer 21 ; a conductive via 6 that extends through first resin layer 21 so as to be connected to a corresponding one of the plurality of conductive patterns 7 ; and a second resin layer 22 that is overlaid on first side 91 of first resin layer 21 .
  • Second resin layer 22 includes a plurality of openings 18 through which the plurality of conductive patterns 7 are partially exposed.
  • conductive via 6 and conductive pattern 7 located in a region inside each of the plurality of openings 18 establish the relation as having been described in the first or second preferred embodiment, that is, the following relationship is established.
  • the inner peripheral edge of opening 18 includes a first portion that is spaced from conductive via 6 by a first distance; and a second portion that is spaced from conductive via 6 by a second distance longer than the first distance.
  • Conductive pattern 7 has a length that starts from the inner peripheral edge of opening 18 to the outside and extends under second resin layer 22 . The length of conductive pattern 7 at the second portion is greater than the length of conductive pattern 7 at the first portion.
  • the plurality of conductive patterns 7 include a first conductive pattern 7 a located in the center portion of component 3 and having a length that starts from the inner peripheral edge of opening 18 to the outside and extends under second resin layer 22 ; and a second conductive pattern 7 b located at the end of component 3 and having a length that starts from the inner peripheral edge of opening 18 to the outside and extends under second resin layer 22 , in which case the maximum value of the length of conductive pattern 7 b is greater than the maximum value of the length of conductive pattern 7 a .
  • the “first conductive pattern 7 a located in the center portion of component 3 ” used herein means a conductive pattern 7 that is located closest to the center of gravity of component 3 when component 3 is seen in plan view.
  • Component 3 is mounted as a product on the upper surface of resin multilayer substrate 106 as described above.
  • a bump 10 is provided on the lower surface of component 3 .
  • Bump 10 may be a solder bump, for example. Bump 10 may be fluid during the mounting operation.
  • the number and arrangement of bumps 10 shown in the figure are merely by way of example and not limited thereto. Also, other bonding materials such as an electrically conductive adhesive may be used in place of bumps.
  • FIG. 16 shows a cross-sectional view in the state where component 3 has been mounted on resin multilayer substrate 106 .
  • Bumps 10 extend into a plurality of openings 18 , respectively, and are electrically connected to a plurality of conductive patterns 7 , respectively.
  • the plurality of conductive patterns 7 each define and function as a land electrode.
  • the joining strength is able to be ensured even if the size of each land electrode is relatively small.
  • conductive patterns 7 are able to be efficiently arranged while suppressing or preventing peeling of conductive patterns 7 .
  • the joining strength is ensured. Accordingly, even when bending is applied as shown by an arrow in FIG. 16 in the state after component 3 has been mounted, peeling between the conductive pattern and the resin layer is less likely to occur.
  • the present preferred embodiment provides a structure in which land electrodes are exposed through a plurality of openings 18 provided in second resin layer 22 as an uppermost layer, which leads to a configuration in which second resin layer 22 as an uppermost layer that separates the land electrodes from each other. Therefore, even in the case where a gap between the land electrodes is relatively narrow, mounting failures such as a solder short are less likely to occur.
  • Second resin layer 22 is located on the uppermost layer, so that the coplanarity of resin multilayer substrate 106 is improved as a whole.
  • a product is provided as component 3 and resin multilayer substrate 106 and component 3 are joined to each other
  • the product may be a mother board.
  • Preferred embodiments of the present invention are also applicable to a configuration in which resin multilayer substrate 106 and a mother board (not shown) such as a printed wiring board are connected to each other by a bump, an electrically conductive adhesive, and the like.
  • FIG. 16 shows a component module 201 according to a preferred embodiment of the present invention.
  • This component module 201 includes a resin multilayer substrate 106 having been described in the sixth preferred embodiment; and a component 3 as a product joined to resin multilayer substrate 106 utilizing a plurality of conductive patterns 7 .
  • the shape of component 3 shown in FIG. 16 is merely by way of example and not limited thereto.
  • the product may be those other than component 3 .
  • the adhesion strength between the conductive pattern and the resin layer is improved.
  • sixth and seventh preferred embodiments each show an example in which only a single component 3 is mounted, a plurality of components may be mounted.
  • Various preferred embodiments of the present invention can be utilized for a resin multilayer substrate and a component module.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
US15/160,190 2014-02-07 2016-05-20 Resin multilayer substrate and component module Active US9936575B2 (en)

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PCT/JP2015/051609 WO2015118951A1 (ja) 2014-02-07 2015-01-22 樹脂多層基板および部品モジュール

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CN205726710U (zh) 2016-11-23
JPWO2015118951A1 (ja) 2017-03-23

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