US9691665B2 - Semiconductor structure with self-aligned spacers and method of fabricating the same - Google Patents

Semiconductor structure with self-aligned spacers and method of fabricating the same Download PDF

Info

Publication number
US9691665B2
US9691665B2 US14/825,183 US201514825183A US9691665B2 US 9691665 B2 US9691665 B2 US 9691665B2 US 201514825183 A US201514825183 A US 201514825183A US 9691665 B2 US9691665 B2 US 9691665B2
Authority
US
United States
Prior art keywords
self
substrate
layer
aligned
silicon oxide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
US14/825,183
Other languages
English (en)
Other versions
US20170018460A1 (en
Inventor
Chih-Kai Hsu
Yu-Hsiang Hung
Ssu-I Fu
Jyh-Shyang Jenq
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
United Microelectronics Corp
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Assigned to UNITED MICROELECTRONICS CORP. reassignment UNITED MICROELECTRONICS CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: FU, SSU-I, HSU, CHIH-KAI, HUNG, YU-HSIANG, JENQ, JYH-SHYANG
Publication of US20170018460A1 publication Critical patent/US20170018460A1/en
Priority to US15/599,430 priority Critical patent/US9870951B2/en
Application granted granted Critical
Publication of US9691665B2 publication Critical patent/US9691665B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02167—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7856—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with an non-uniform gate, e.g. varying doping structure, shape or composition on different sides of the fin, or different gate insulator thickness or composition on opposing fin sides

Definitions

  • the present invention relates to a method of fabricating a semiconductor structure with self-aligned spacers, and more particularly, to a method of fabricating a semiconductor structure with double layers of self-aligned spacers.
  • circuit density is continuing to increase at a fairly constant rate.
  • the present invention provides a method of fabricating a self-aligned contact by using composite self-aligned spacers.
  • a method of fabricating a semiconductor structure with self-aligned spacers includes providing a substrate with at least two gate structures disposed on the substrate, wherein the substrate between the gate structures is exposed. Then, a silicon oxide layer is formed to cover the exposed substrate. A nitride-containing material layer is formed to cover the gate structures and the silicon oxide layer. After that, the nitride-containing material layer is etched to form a first self-aligned spacer at a sidewall of each gate structure, exposing part of the silicon oxide layer, wherein the sidewalls of each gate structure are opposed to each other.
  • the exposed silicon oxide layer is removed to form a second self-aligned spacer, wherein the first self-aligned spacer and the second self-aligned spacer cooperatively define a recess on the substrate. Finally, a contact plug is formed in the recess.
  • a semiconductor structure with self-aligned spacers includes a substrate, two gate structures disposed on the substrate, and composite self-aligned spacers respectively disposed on a sidewall of each of the gate structures, wherein the sidewalls of each of the gate structures are opposed to each other, each of the composite self-aligned spacers comprises a nitride-containing material layer and a silicon oxide layer, and the silicon oxide layer is disposed between the substrate and the nitride-containing material layer.
  • the semiconductor structure with self-aligned spacers further includes a contact plug disposed between the composite self-aligned spacers.
  • FIG. 1 to FIG. 6 depict a method of fabricating a FinFET with self-aligned spacers according to a first preferred embodiment of the present invention.
  • FIG. 7 to FIG. 9 depict a method of fabricating a FinFET with self-aligned spacers according to a second preferred embodiment of the present invention.
  • FIG. 10 depicts a planar transistor with self-aligned spacers, wherein the example (a) in FIG. 10 depicts a planar transistor with self-aligned spacers according to a fifth embodiment of the present invention, and the example (b) in FIG. 10 depicts a planar transistor with self-aligned spacers according to a sixth embodiment of the present invention.
  • FIG. 1 to FIG. 6 depict a method of fabricating a FinFET with self-aligned spacers according to a first preferred embodiment of the present invention.
  • a substrate 10 is provided. At least two gate structures 12 are disposed on the substrate 10 .
  • An epitaxial layer 14 or a doping region (not shown) is disposed in the substrate 10 between the gate structures 12 .
  • FIG. 1 shows the epitaxial layer 14 as an example.
  • the substrate 10 in FIG. 1 includes a fin structure but is not limited thereto.
  • the substrate 10 can be a planar substrate as shown in FIG. 10 .
  • the substrate 10 is preferably a silicon substrate.
  • the substrate 10 may be any suitable substrate, a III-V compound substrate, a silicon germanium (SiGe) substrate, an epi-substrate, or the like.
  • the substrate 10 may optionally have other layers formed therein or thereon, such as dielectric or metals that may form other devices, conductive traces, or the like.
  • the gate structure 12 can include a gate electrode 16 and a gate dielectric layer 18 disposed under the gate electrode 16 .
  • a spacer 20 is disposed at two sides of the gate structure 12 .
  • a cap layer 22 may cover the gate electrode 16 .
  • a shallow trench isolation (STI) 24 is embedded in the substrate 10 and sandwiches the fin structure.
  • a dielectric layer 26 covers the substrate 10 , the epitaxial layer 14 and the STI 24 .
  • a dielectric layer 28 covers the dielectric layer 26 and the gate structures 12 .
  • the epitaxial layer 14 is a single semiconductive layer or multiple semiconductive layers formed by a selective epitaxial growth process.
  • the epitaxial layer 14 may be silicon, germanium, or silicon germanium. According to a preferred embodiment, the epitaxial layer 14 is double layered.
  • the lower layer of the epitaxial layer 14 is silicon germanium and the upper layer of the epitaxial layer 14 is silicon.
  • the gate electrode 16 may include one or multiple layers of insulating layers such as silicon oxide or high-k materials.
  • the spacer 20 , the cap layer 22 , the STI 24 , and the dielectric layers 26 / 28 may include one or multiple layers of insulating layers such as silicon oxide, silicon nitride, silicon carbonitride or silicon oxycarbonitride. In one embodiment, the spacer 20 and the cap layer 22 are silicon nitride.
  • the STI 24 , the dielectric layers 26 / 28 are silicon oxide.
  • the dielectric layer 26 and the dielectric layer 28 are patterned to expose the substrate 10 which includes the epitaxial layer 14 which is between the adjacent gate structures 12 .
  • the steps of patterning the dielectric layer 26 and the dielectric layer 28 include removing part of the dielectric layer 26 and part of the dielectric layer 28 by a lithographic process to form the contact hole 30 . Based on different conditions, some dielectric layers 26 / 28 can remain on the spacer 20 to prevent damage to the gate structure 12 and the spacer 20 due to the offset of the lithographic process.
  • the contact hole 30 is defined by the dielectric layers 26 / 28 remaining on the spacer 20 and a top surface of the epitaxial layer 14 .
  • a silicon oxide layer 32 is formed to conformally cover the dielectric layers 26 / 28 and the substrate 10 comprising the epitaxial layer 14 .
  • the thickness of the silicon oxide layer 32 is greater than 10 angstroms, and preferably greater than 20 angstroms.
  • the silicon oxide layer 32 is formed by a deposition process to conformally fill in the contact hole 30 and contact the substrate 14 .
  • a nitride-containing material layer conformally covers the silicon oxide layer 32 .
  • the nitride-containing material layer 34 covers the silicon oxide layer 32 and the gate structures 12 , the dielectric layers 26 / 28 and the epitaxial layer 14 under the silicon oxide layer 32 .
  • the nitride-containing material layer 34 includes silicon nitride, silicon oxynitride, silicon carbonitride or silicon oxycarbonitride, but is not limited thereto. Other nitride-containing materials may also be used as the nitride-containing material layer 34 . Furthermore, the nitride-containing material layer 34 can include stress and the stress in the nitride-containing material layer 34 can be transferred into the epitaxial layer 14 by a thermal process. It is noteworthy that the contact hole 30 is formed before the silicon oxide layer 32 and the nitride-containing material layer 34 are formed.
  • the nitride-containing material layer 34 is etched to form a first self-aligned spacer 36 at a sidewall 112 of each of the gate structures 12 and expose the silicon oxide layer 32 which contacts the epitaxial layer 14 .
  • the first self-aligned spacer 36 is made of the nitride-containing material layer 34 .
  • the sidewalls 114 of each of the gate structures 12 are opposed to each other.
  • the nitride-containing material layer 34 is preferably etched anisotropically by taking the silicon oxide layer 32 as an etching stop layer.
  • the nitride-containing material layer 34 can be dry etched.
  • the epitaxial layer 14 is protected by the silicon oxide layer 32 from being damaged by etchant during the formation of the first self-aligned spacer 36 .
  • some dielectric layers 26 / 28 optionally remain on the spacer 20 ; therefore, when etching the nitride-containing material layer 34 , the dielectric layers 26 / 28 , the spacer 20 and the cap layer 22 work together to protect the gate electrode 16 from being damaged by over etched or etching shift.
  • the exposed silicon oxide layer 32 is removed and the remaining silicon oxide layer 32 forms a second self-aligned spacer 38 .
  • the second self-aligned spacer 38 is made of the silicon oxide layer 32 .
  • the first self-aligned spacer 36 and the second self-aligned spacer 38 define a recess 40 within the contact hole 30 and on the substrate 10 .
  • the entire second self-aligned spacer 38 has an L-shaped cross section.
  • the second self-aligned spacer 38 is disposed between the substrate 10 having the epitaxial layer 14 and the first self-aligned spacer 36 , and is disposed between the gate structure 12 and the first self-aligned spacer 36 .
  • the method of removing the exposed silicon oxide layer 32 includes a pre-clean process.
  • the pre-clean process may be a SiCoNiTM process.
  • the pre-clean process can be performed in a chamber available from Applied Materials, Inc. of Santa Clara, Calif., or other suitable chambers.
  • the pre-clean process is performed between two different processes for cleaning native oxide, and is a standard process in the conventional fabricating method.
  • the present invention using the pre-clean process to remove the silicon oxide layer 32 , therefore no extra step is added to remove the silicon oxide layer 32 .
  • the pre-clean process uses remote plasma assisted dry etch process which involves the simultaneous exposure of the exposed silicon oxide layer 32 to nitrogen trifluoride and ammonia. In addition, based on different conditions, hydrogen or hydrogen fluoride can be added into the plasma.
  • a barrier layer 42 such as tantalum nitride or titanium nitride is formed conformally to cover the recess 40 .
  • a metal layer 44 is formed to fill in the recess 42 .
  • the barrier layer 42 and the metal layer 44 are planarized and the remaining barrier layer 42 and the metal layer 44 in the recess 42 form a contact plug 52 .
  • the contact plug 52 electrically connects to the epitaxial layer 14 .
  • a silicide can be optionally formed on the top surface epitaxial layer 14 .
  • a FinFET Fin Field-Effect Transistor
  • FIG. 1 and FIG. 7 to FIG. 9 depict a method of fabricating a FinFET with self-aligned spacers according to a second preferred embodiment of the present invention, wherein like reference numerals are used to refer to like elements throughout.
  • the silicon oxide layer 32 is formed by oxidizing the surface of a silicon substrate. In the first preferred embodiment, however, the silicon oxide layer 32 is formed by a deposition process. Other steps and elements are the same as in the first preferred embodiment. Please refer to the first preferred embodiment for the detailed process.
  • the method of fabricating a FinFET with self-aligned spacers according to a second preferred embodiment is illustrated as follows. As shown in FIG.
  • a substrate 10 is provided. At least two gate structures 12 are disposed on the substrate 10 .
  • An epitaxial layer 14 or a doping region (not shown) is disposed in the substrate 10 between the gate structures 12 .
  • the doping region may be a source/drain doping region.
  • the substrate 10 includes a fin structure but is not limited thereto.
  • the substrate 10 can be a planar substrate.
  • the gate structure 12 can include agate electrode 16 and a gate dielectric layer 18 disposed under the gate electrode 16 .
  • a spacer 20 is disposed at two sides of the gate structure 12 .
  • a cap layer 22 may cover the gate electrode 16 .
  • An STI 24 is embedded in the substrate 10 and sandwiches the fin structure.
  • a dielectric layer 26 covers the substrate 10 , the epitaxial layer 14 and the STI 24 .
  • a dielectric layer 28 covers the dielectric layer 26 and the gate structures 12 .
  • the dielectric layer 26 and the dielectric layer 28 are patterned to expose the substrate 10 which includes the epitaxial layer 14 which is between the adjacent gate structures 12 .
  • a top surface of the epitaxial layer 14 is oxidized to form a silicon oxide layer 32 .
  • a top surface of the substrate 14 is oxidized to form the silicon oxide layer 32 .
  • the oxidization is preferably performed at a temperature below 600° C.
  • the thickness of the silicon oxide layer 32 is greater than 10 angstroms, and preferably greater than 20 angstroms.
  • a nitride-containing material layer 34 conformally covers the silicon oxide layer 32 .
  • the nitride-containing material layer 34 covers the silicon oxide layer 32 and the gate structures 12 , the dielectric layers 26 / 28 and the epitaxial layer 14 under the silicon oxide layer 32 .
  • the nitride-containing material layer 34 includes silicon nitride, silicon oxynitride, silicon carbonitride or silicon oxycarbonitride, but is not limited thereto. Other nitride-containing materials may also be used as the nitride-containing material layer 34 .
  • the nitride-containing material layer 34 is etched to form a first self-aligned spacer 36 at a sidewall 112 of each of the gate structures 12 by taking the silicon oxide layer 34 as an etching stop layer. After the nitride-containing material layer 34 is etched, part of the silicon oxide layer 32 is exposed.
  • the exposed silicon oxide layer 32 is removed to expose the epitaxial layer 14 in the substrate 10 .
  • the remaining silicon oxide layer 32 forms a second self-aligned spacer 38 .
  • the first self-aligned spacer 36 and the second self-aligned spacer 38 define a recess 40 within the contact hole 30 and on the substrate 10 .
  • the entire second self-aligned spacer 38 has a trapezoid-shaped cross section.
  • the second self-aligned spacer 38 is disposed between the substrate 10 having the epitaxial layer 14 and the first self-aligned spacer 36 . There is no second self-aligned spacer 38 between the first self-aligned spacer 36 and the gate structure 12 .
  • the method of removing the exposed silicon oxide layer 32 includes a pre-clean process.
  • the pre-clean process uses remote plasma assisted dry etch process which involves the simultaneous exposure of the exposed silicon oxide layer 32 to nitrogen trifluoride and ammonia. Based on different conditions, hydrogen or hydrogen fluoride can be added into the plasma.
  • a barrier layer 42 such as tantalum nitride or titanium nitride is formed conformally to cover the recess 40 .
  • a metal layer 44 is formed to fill in the recess 42 .
  • the barrier layer 42 and the metal layer 44 are planarized and the remaining barrier layer 42 and the metal layer 44 in the recess 42 form a contact plug 52 .
  • a silicide can be optionally formed on the top surface epitaxial layer 14 .
  • a FinFET with self-aligned spacers 200 according to a second preferred embodiment of the present invention is completed.
  • the first preferred embodiment and the second preferred embodiment of the present invention not only can be applied to the FinFET previously described but also can be applied to a planar transistor.
  • the example (a) and the example (b) in FIG. 10 respectively depict a planar transistor with self-aligned spacers 300 and a planar transistor with self-aligned spacers 400 by using the method illustrated in the first preferred embodiment and the second preferred embodiment.
  • FIG. 6 depicts a FinFET with self-aligned spacers according to a third preferred embodiment of the present invention.
  • a FinFET with self-aligned spacers 100 includes a substrate 10 .
  • the substrate 10 includes a fin structure but is not limited thereto.
  • the substrate 10 can be a planar substrate.
  • At least two gate structures 12 are disposed on the substrate 10 .
  • the gate structure 12 can include a gate electrode 16 and a gate dielectric layer 18 disposed under the gate electrode 16 .
  • a spacer 20 is disposed at two sides of the gate structure 12 .
  • a cap layer 22 may cover the gate electrode 16 .
  • An STI 24 is embedded in the substrate 10 and sandwiches the fin structure.
  • An epitaxial layer 14 or a doping region (not shown) is disposed in the substrate 10 between the gate structures 12 .
  • FIG. 6 shows the epitaxial layer 14 as an example.
  • Composite self-aligned spacers 50 are respectively disposed on a sidewall 112 of each of the gate structures 12 .
  • the sidewalls 112 of each of the gate structures 12 are opposed to each other.
  • Each of the composite self-aligned spacers 50 includes a first self-aligned spacer 36 and the second self-aligned spacer 38 .
  • the first self-aligned spacer 36 is made of a nitride-containing material layer.
  • the second self-aligned spacer 38 is made of a silicon oxide layer.
  • the thickness of the silicon oxide layer 38 is greater than 10 angstroms, and preferably greater than 20 angstroms.
  • the nitride-containing material layer includes silicon nitride, silicon oxynitride, silicon carbonitride or silicon oxycarbonitride, but is not limited thereto. Other nitride-containing materials may also be used as the second self-aligned spacer 38 .
  • the second self-aligned spacer 38 is disposed between the substrate 10 having the epitaxial layer 14 and the first self-aligned spacer 36 , and is disposed between the gate structure 12 and the first self-aligned spacer 36 .
  • the entire second self-aligned spacer 38 has an L-shaped cross section.
  • Dielectric layers 26 / 28 can optionally be disposed between one of the composite self-aligned spacer 50 and the spacer 20 .
  • a contact plug 52 is disposed between the composite self-aligned spacers 50 and the contact plug 52 contacts the epitaxial layer 14 .
  • FIG. 9 depicts a FinFET with self-aligned spacers according to a fourth preferred embodiment of the present invention.
  • the fourth preferred embodiment the entire second self-aligned spacer 38 has a trapezoid-shaped cross section.
  • the second self-aligned spacer 38 is only disposed between the substrate 10 having the epitaxial layer 14 and the first self-aligned spacer 36 .
  • the substrate 10 in the fourth preferred embodiment must be a silicon substrate.
  • Other elements in FIG. 9 are basically the same as those in FIG. 6 ; an accompanying explanation is therefore omitted.
  • the example (a) in FIG. 10 depicts a planar transistor with self-aligned spacers according to a fifth embodiment of the present invention.
  • the transistor in the fifth embodiment is a planar transistor rather than a FinFET, i.e. the substrate 10 is a planar substrate.
  • the substrate 10 is a planar substrate.
  • Other elements in the fifth embodiment are basically the same as those in the third embodiment; an accompanying explanation is therefore omitted.
  • the example (b) in FIG. 10 depicts a planar transistor with self-aligned spacers according to a sixth embodiment of the present invention.
  • the differences between the sixth embodiment and the fifth embodiment are that the entire second self-aligned spacer 38 has a trapezoid-shaped cross section.
  • the second self-aligned spacer 38 is disposed between the substrate 10 having the epitaxial layer 14 and the first self-aligned spacer 36 .
  • Other elements in the sixth embodiment are basically the same as those in the fifth embodiment; an accompanying explanation is therefore omitted.
  • the silicon oxide layer 32 is utilized as an etching stop layer during etching of the nitride-containing material layer 34 . Then, the silicon oxide layer 32 is removed by a pre-clean process. It is noteworthy that the pre-clean process is a conventional process used between two different fabricating steps to clean native oxide. Therefore, the silicon oxide layer 32 can be removed without adding any new processes. Moreover, the pre-clean process has a high etching ratio between the silicon substrate and the silicon oxide. Generally, the etching ratio of the silicon oxide to silicon substrate is greater than 20:1 in the pre-clean process. Therefore, when removing the silicon oxide layer 32 , the substrate or the epitaxial layer 14 under the silicon oxide layer 32 will not be damaged.
  • the conventional process utilizes a silicon nitride as an etching stop layer.
  • the silicon nitride should be removed by hot phosphoric acid; however, the etching ratio of the silicon substrate to the silicon nitride is not high enough by taking the hot phosphoric acid as the etchant. Therefore, the surface of the silicon substrate or the epitaxial layer will be damaged when removing the silicon nitride.
  • the present invention using the silicon oxide as the etching stop layer can prevent damage to the silicon substrate or the epitaxial layer.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
US14/825,183 2015-07-13 2015-08-13 Semiconductor structure with self-aligned spacers and method of fabricating the same Active US9691665B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/599,430 US9870951B2 (en) 2015-07-13 2017-05-18 Method of fabricating semiconductor structure with self-aligned spacers

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
CN201510407826.4A CN106356299B (zh) 2015-07-13 2015-07-13 具有自我对准间隙壁的半导体结构及其制作方法
CN201510407826 2015-07-13
CN201510407826.4 2015-07-13

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US15/599,430 Division US9870951B2 (en) 2015-07-13 2017-05-18 Method of fabricating semiconductor structure with self-aligned spacers

Publications (2)

Publication Number Publication Date
US20170018460A1 US20170018460A1 (en) 2017-01-19
US9691665B2 true US9691665B2 (en) 2017-06-27

Family

ID=57776380

Family Applications (2)

Application Number Title Priority Date Filing Date
US14/825,183 Active US9691665B2 (en) 2015-07-13 2015-08-13 Semiconductor structure with self-aligned spacers and method of fabricating the same
US15/599,430 Active US9870951B2 (en) 2015-07-13 2017-05-18 Method of fabricating semiconductor structure with self-aligned spacers

Family Applications After (1)

Application Number Title Priority Date Filing Date
US15/599,430 Active US9870951B2 (en) 2015-07-13 2017-05-18 Method of fabricating semiconductor structure with self-aligned spacers

Country Status (2)

Country Link
US (2) US9691665B2 (zh)
CN (1) CN106356299B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10276693B1 (en) * 2017-10-31 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10510851B2 (en) * 2016-11-29 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Low resistance contact method and structure
CN109390338B (zh) * 2017-08-08 2021-06-22 联华电子股份有限公司 互补式金属氧化物半导体元件及其制作方法
KR102432866B1 (ko) * 2017-11-29 2022-08-17 삼성전자주식회사 반도체 소자 및 그 제조 방법
JP2019153694A (ja) * 2018-03-02 2019-09-12 東芝メモリ株式会社 半導体装置およびその製造方法
US10720337B2 (en) * 2018-07-20 2020-07-21 Asm Ip Holding B.V. Pre-cleaning for etching of dielectric materials

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7135744B2 (en) 2003-02-11 2006-11-14 Samsung Electronics Co., Ltd. Semiconductor device having self-aligned contact hole and method of fabricating the same
US7375392B1 (en) * 2001-08-10 2008-05-20 Integrated Device Technology, Inc. Gate structures having sidewall spacers formed using selective deposition
US8236702B2 (en) 2005-10-06 2012-08-07 United Microelectronics Corp. Method of fabricating openings and contact holes
US8981422B2 (en) * 2011-02-22 2015-03-17 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100284905B1 (ko) * 1998-10-16 2001-04-02 윤종용 반도체 장치의 콘택 형성 방법
JP3450770B2 (ja) * 1999-11-29 2003-09-29 松下電器産業株式会社 半導体装置の製造方法
CN1206706C (zh) * 2001-01-11 2005-06-15 世界先进积体电路股份有限公司 一种在半导体基底上形成自行对准的接触窗结构的方法
CN1153273C (zh) * 2001-03-29 2004-06-09 华邦电子股份有限公司 一种具有牺牲型填充柱的自行对准接触方法
CN1303651C (zh) * 2003-07-16 2007-03-07 旺宏电子股份有限公司 自对准接触窗形成方法
CN100411146C (zh) * 2005-12-06 2008-08-13 联华电子股份有限公司 制作应变硅互补式金属氧化物半导体晶体管的方法
KR100831158B1 (ko) * 2006-12-20 2008-05-20 동부일렉트로닉스 주식회사 플래시 메모리 소자의 제조방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7375392B1 (en) * 2001-08-10 2008-05-20 Integrated Device Technology, Inc. Gate structures having sidewall spacers formed using selective deposition
US7135744B2 (en) 2003-02-11 2006-11-14 Samsung Electronics Co., Ltd. Semiconductor device having self-aligned contact hole and method of fabricating the same
US8236702B2 (en) 2005-10-06 2012-08-07 United Microelectronics Corp. Method of fabricating openings and contact holes
US8981422B2 (en) * 2011-02-22 2015-03-17 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10276693B1 (en) * 2017-10-31 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof

Also Published As

Publication number Publication date
US20170018460A1 (en) 2017-01-19
US20170256459A1 (en) 2017-09-07
CN106356299B (zh) 2021-04-13
US9870951B2 (en) 2018-01-16
CN106356299A (zh) 2017-01-25

Similar Documents

Publication Publication Date Title
US10297511B2 (en) Fin-FET device and fabrication method thereof
US9870951B2 (en) Method of fabricating semiconductor structure with self-aligned spacers
KR101815527B1 (ko) 반도체 소자 및 그 제조 방법
US11101178B2 (en) Semiconductor integrated circuit
TWI807067B (zh) 半導體結構與其形成方法、鰭狀場效電晶體裝置、與閘極結構
US7981784B2 (en) Methods of manufacturing a semiconductor device
US10714397B2 (en) Semiconductor device including an active pattern having a lower pattern and a pair of channel patterns disposed thereon and method for manufacturing the same
JP2007027348A (ja) 半導体装置及びその製造方法
JP2007103456A (ja) 半導体装置及びその製造方法
CN109148296B (zh) 半导体结构及其形成方法
TW202109623A (zh) 形成半導體裝置的方法
TW202404076A (zh) 半導體裝置及其製造方法
CN109887845B (zh) 半导体器件及其形成方法
US7989300B2 (en) Method of manufacturing semiconductor device
US10424482B2 (en) Methods and structures for forming a tight pitch structure
KR102546906B1 (ko) Finfet 디바이스 및 방법
US9318338B2 (en) Method for fabricating semiconductor device
KR102623749B1 (ko) 갭충전 구조물 및 그 제조 방법
JP2012230993A (ja) 半導体基板、半導体装置及びその製造方法
US20240113164A1 (en) Film modification for gate cut process
TW202410163A (zh) 奈米結構場效電晶體及其製造方法
TWI521709B (zh) 半導體結構及積體電路之製造方法
JP2005223196A (ja) 半導体装置及びその製造方法
JP2012243990A (ja) 半導体装置及びその製造方法
KR100752200B1 (ko) 반도체 소자의 제조 방법

Legal Events

Date Code Title Description
AS Assignment

Owner name: UNITED MICROELECTRONICS CORP., TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HSU, CHIH-KAI;HUNG, YU-HSIANG;FU, SSU-I;AND OTHERS;REEL/FRAME:036313/0775

Effective date: 20150807

STCF Information on status: patent grant

Free format text: PATENTED CASE

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 4