CN106356299A - 具有自我对准间隙壁的半导体结构及其制作方法 - Google Patents

具有自我对准间隙壁的半导体结构及其制作方法 Download PDF

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CN106356299A
CN106356299A CN201510407826.4A CN201510407826A CN106356299A CN 106356299 A CN106356299 A CN 106356299A CN 201510407826 A CN201510407826 A CN 201510407826A CN 106356299 A CN106356299 A CN 106356299A
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self
clearance wall
aligned clearance
layer
aligned
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CN106356299B (zh
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许智凯
洪裕祥
傅思逸
郑志祥
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to US14/825,183 priority patent/US9691665B2/en
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Priority to US15/599,430 priority patent/US9870951B2/en
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  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

本发明公开一种具有自我对准间隙壁的半导体结构及其制作方法，该制作方法包含首先提供一基材，至少二栅极结构设置于基材上，位于各个栅极结构之间的基材曝露出来，然后形成一氧化硅层覆盖曝露的基材，形成一含氮材料层覆盖各个栅极结构和氧化硅层，然后蚀刻含氮材料层形成一第一自我对准间隙壁于各个栅极结构的一侧壁，并且曝露出部分的氧化硅层，其中各个侧壁相对，移除曝露的氧化硅层以形成一第二自我对准间隙壁，其中第一自我对准间隙壁和第二自我对准间隙壁于该基材上定义出一凹槽，最后形成一接触插塞于凹槽中。

Description

具有自我对准间隙壁的 半导体结构及其制作方法
技术领域
本发明涉及一种具有自我对准间隙壁的晶体管的制作方法，特别是涉及一种具有双层自我对准间隙壁的晶体管的制作方法。
背景技术
当集成电路的集成度增加，使得芯片的表面无法提供足够的面积来制作所需的内连线(interconnects)时，为了配合MOS晶体管缩小后所增加的内连线需求，两层以上金属层设计，便逐渐成为许多集成电路所必需采用的方式。特别是一些功能较复杂的产品，如微处理器，甚至需要更多层的金属层，才能完成微处理器内各个元件间的连接，而不同金属层之间可以用导电插塞来连接。
通常，导电插塞的制作，是蚀刻一绝缘层以形成一接触洞，之后将导电材料填入此接触口，然而随着半导体制作工艺中线宽的缩小，接触洞的孔径亦随之缩小，因此就发展出自我对准接触(Self-aligned contact,SAC)制作工艺来定义并缩短相邻栅极的间距，以达到缩小芯片尺寸的目的。但传统的自我对准接触制作工艺在形成间隙壁时会伤害到下方的基材表面，影响元件的整体电性表现。因此如何改良现有自我对准接触制作工艺实为一重要课题。
发明内容
有鉴于此，本发明的目的在于提供了一种具有自我对准间隙壁的鳍状晶体管的制作方法来解决上述问题。
根据本发明的第一优选实施例，一种具有自我对准间隙壁的半导体结构的制作方法，包含首先提供一基材，至少二栅极结构设置于基材上，位于各个栅极结构之间的基材曝露出来，然后形成一氧化硅层覆盖曝露的基材，形成一含氮材料层覆盖各个栅极结构和氧化硅层，然后蚀刻含氮材料层形成一第一自我对准间隙壁于各个栅极结构的一侧壁，并且曝露出部分的氧化硅层，其中各个侧壁相对，移除曝露的氧化硅层以形成一第二自我对准间隙壁，其中第一自我对准间隙壁和第二自我对准间隙壁于该基材上定义出一凹槽，最后形成一接触插塞于凹槽中。
根据本发明的第二优选实施例，一种具有自我对准间隙壁的半导体结构，包含：一基材，二栅极结构设置于基材上，一复合自我对准间隙壁设置于各个栅极结构的一侧壁，其中各个侧壁相对，各个复合自我对准间隙壁包含一含氮材料层和一氧化硅层，氧化硅层夹在基材和含氮材料层之间以及一接触插塞设置于等复合自我对准间隙壁之间。
附图说明
图1至图6为本发明的第一优选实施例所绘示的具有自我对准间隙壁的鳍状晶体管的制作方法的示意图；
图1、图7至图9为本发明的第二优选实施例所绘示的具有自我对准间隙壁的鳍状晶体管的制作方法的示意图；
图10a为本发明的第五优选实施例所绘示的具有自我对准间隙壁的平面晶体管的示意图；
图10b为本发明的第六优选实施例所绘示的具有自我对准间隙壁的平面晶体管的示意图。
主要元件符号说明
10 基材 12 栅极结构
14 外延层 16 栅极电极
18 栅极介电层 20 间隙壁
22 栅极上盖层 24 浅沟槽隔离
26 介电层 28 介电层
30 接触洞 32 氧化硅层
34 含氮材料层 36 第一自我对准间隙壁
38 第二自我对准间隙 40 凹槽壁
42 缓冲层 44 金属层
50 复合自我对准间隙 52 接触插塞壁
100 具有自我对准间隙 200 具有自我对准间隙壁的鳍状晶体管 壁的鳍状晶体管
112 侧壁 114 掺质掺杂区
300 具有自我对准间隙 400 具有自我对准间隙壁的平面晶体管 壁的平面晶体管
具体实施方式
图1至图6为根据本发明的第一优选实施例所绘示的具有自我对准间隙壁的鳍状晶体管的制作方法。如图1所示，首先提供一基材10，基材10上设有至少两个栅极结构12，在二个栅极结构12之间的基材10中，包含有一外延层14或者是一掺质掺杂区(图未示)，在图1中以外延层14为例。在图1中的基材10上包含有一鳍状结构，但不限于此，基材10也可以为一平面的基底(如图10a及图10b所示)，在本实施例中，基材10优选为硅基底。此外基材10也可以为III-V族化合物基底或一硅锗基底等，基材10可有选择性地有其它的材料层，例如介电层或金属层，设置于基材10其中或是其上，前述介电层或金属层可用来形成其它元件。
栅极结构12可以包含一栅极电极16和一栅极介电层18位于栅极电极16之下，另外一间隙壁20位于栅极结构两侧，此外栅极电极16上可覆盖一栅极上盖层22。在最旁边的栅极结构12的一侧的基材10中，设有一浅沟槽隔离24。一介电层26覆盖基材10、外延层14和浅沟槽隔离24，一介电层28覆盖介电层26和栅极结构12。
外延层14为使用选择性外延成长制作工艺(Selective Epitaxial Growth,SEG)形成的一或多层的半导体材料层，例如硅、锗、锗化硅等。在一优选实施例中，外延层14为双层结构，下层为锗化硅和上层为硅。栅极电极16可包含一或多层的导电材料层，例如铝、钨、钛等。栅极介电层18可包含一或多层的绝缘材料层，例如氧化硅或高介电常数材料层。间隙壁20、栅极上盖层22、浅沟槽隔离24、介电层26和介电层28可包含一或多层的绝缘材料层，例如氧化硅、氮化硅、氮碳化硅、氮氧化硅或氮碳氧化硅等。于一优选实施例中，间隙壁20、栅极上盖层22为氮化硅，浅沟槽隔离24、介电层26和介电层28为氧化硅。
如图2所示，图案化介电层26和介电层28，使得位于相邻的栅极结构12之间包含有外延层14的基材10曝露出来，也就是说在相邻的栅极结构12之间的形成一接触洞30，前述图案化介电层26和介电层28的步骤包含将部分的介电层26和部分的介电层28利用光刻暨蚀刻制作工艺移除，以在介电层26/28中形成一接触洞30，可视情况需要，在间隙壁20上可以选择性残留一些介电层26/28，避免在形成接触洞30时因为光刻暨蚀刻制作工艺的误差，伤害到间隙壁20甚至栅极结构12。本实施例中，接触洞30以残留在间隙壁20上的介电层26/28和外延层14的上表面定义而成。
如图3所示，形成一氧化硅层32顺应地覆盖介电层26/28和包含有外延层14的基材10，氧化硅层32的厚度需大于10埃，优选大于20埃。详细来说利用沉积制作工艺形成氧化硅层32顺应地填入接触洞30并且接触外延层14，然后形成一含氮材料层34顺应地覆盖氧化硅层32，也就是说含氮材料层34覆盖了氧化硅层32和在氧化硅层32之下的栅极结构12、介电层26/28和外延层14。含氮材料层34包含有氮化硅、氮碳化硅、氮氧化硅或氮碳氧化硅等，但不限于此，其它的含氮材料也可以视情况使用。此外，含氮材料层34中可以包含有应力，并且利用加热的程序把应力转到外延层14中。值得注意的是本发明在形成接触洞30之前，氧化硅层32和含氮材料层34都未形成。
如图4所示，蚀刻含氮材料层34形成一第一自我对准间隙壁36于各个栅极结构12的一侧壁112，并且曝露出接触外延层14的氧化硅层32。第一自我对准间隙壁36是由含氮材料层34构成，其中各个侧壁112相对，在蚀刻含氮材料时34优选使用非等向性蚀刻，例如干蚀刻，并且以氧化硅层32作为蚀刻停止层，如此在形成第一自我对准间隙壁36时，外延层14被氧化硅层32保护，就不会被蚀刻剂伤害。此外，在间隙壁20上有选择性残留一些介电层26/28，因此在蚀刻含氮材料层34时，介电层26/28可以和间隙壁20和栅极上盖层22一同保护栅极电极16，避免干蚀刻时发生位移或过度蚀刻损害栅极电极16。
如图5所示，移除曝露的氧化硅层32以形成一第二自我对准间隙壁38，也就是说第二自我对准间隙壁38是由氧化硅层32构成，第一自我对准间隙壁36和第二自我对准间隙壁38于位于接触洞30内的基材10上定义出一凹槽40，整个第二自我对准间隙壁38的截面为L形，此外，第二自我对准间隙壁38夹在包含有外延层14的基材10和第一自我对准间隙壁36之间并且夹在栅极结构12和第一自我对准间隙壁36之间。此外，介电层28覆盖并重迭栅极上盖层22，第一自我对准间隙壁36和第二我对准间隙壁38都接触介电层28。移除曝露的氧化硅层的方式可以包含使用一预清洗制作工艺，例如为一SiCoNiTM预清洗制作工艺，SiCoNiTM预清洗制作工艺可以在由加利福尼亚州圣克拉拉市应用材料公司所提供的腔室进行。详细来说预清洗制作工艺一般而言是在不同制作工艺之间，用来去除原生氧化层的清洗制作工艺，为传统半导体制作工艺中的一标准制作工艺，本发明将预清洗制作工艺用来移除曝露的氧化硅层32，如此就不需要为了移除曝露的氧化硅层32额外增加其它步骤。预清洗制作工艺使用等离子体进行，并且将待移除的氧化硅层32曝露在含有三氟化氮以及氨气中，此外，视情况需要可以在等离子体增加氢气或者氟化氢。
如图6所示，形成一缓冲层42例如氮化钽或氮化钛等顺应地覆盖凹槽40，之后再形成一金属层44填满凹槽42，之后平坦化缓冲层42和金属层44以在凹槽40中用剩余的缓冲层42和金属层44形成一接触插塞52，接触插塞52电连接外延层14，在外延层14的上表面可以选择性形成一金属硅化物。至此根据本发明的第一优选实施例所制作的具有自我对准间隙壁的鳍状晶体管100业已完成。
图1、图7至图9为根据本发明的第二优选实施例所绘示的具有自我对准间隙壁的鳍状晶体管的制作方法，其中具有相同功能的元件以相同的符号标示。第二优选实施例和第一优选实施例之间的差别在于第二优选实施例的氧化硅层32是利用硅基底的表面氧化而形成，然而第一优选实施例中的氧化硅层32是利用沉积氧化硅层在基材表面而形成。其它制作工艺和材料，大致和第一优选实施例相同，因此对于相同的制作工艺请参考前文对于第一优选实施例的描述。本发明的第二优选实施例所绘示的具有自我对准间隙壁的半导体结构的制作方法如下，如图1所示，首先提供一基材10，基材10上设有至少两个栅极结构12，在二个栅极结构12之间的基材10中，包含有一外延层14或者是一掺质掺杂区(图未示)，掺质掺杂区可以例如为一源极/漏极掺杂区，基材10包含有鳍状结构，但不限于此，基材10也可以为一平面的基底，栅极结构12可以包含一栅极电极16和一栅极介电层18位于栅极电极16之下，另外一间隙壁20位于栅极结构12两侧，此外栅极电极20上可覆盖一栅极上盖层22。在最旁边的栅极结构12的一侧的基材10中，设有一浅沟槽隔离24。一介电层26覆盖基材10、外延层14和浅沟槽隔离24，一介电层28覆盖介电层26和栅极结构12。
如图7所示，图案化介电层26和介电层28，使得位于相邻的栅极结构12之间包含有外延层14的基材10曝露出来，也就是说在相邻的栅极结构12之间的形成一接触洞30，之后利用氧化制作工艺，氧化曝露的外延层14表面，若是基材10中没有外延层14，则会直接氧化基材10的表面，以在外延层14或基材10的上表面形成一氧化硅层32，氧化制作工艺的操作温度优选小于600℃，而氧化硅层32的厚度需大于10埃，优选大于20埃。接着形成一含氮材料层34顺应地覆盖氧化硅层32，也就是说含氮材料层34覆盖了氧化硅层32和在氧化硅层32之下的栅极结构12、介电层26/28和外延层14。含氮材料层34包含有氮化硅、氮碳化硅、氮氧化硅或氮碳氧化硅等，但不限于此，其它的含氮材料也可以视情况使用。
如图8所示，以氧化硅层32为蚀刻停止层，蚀刻含氮材料层34形成一第一自我对准间隙壁36于各个栅极结构12的一侧壁112，直至曝露出接触外延层14的氧化硅层32。
接着如图9所示，移除曝露的氧化硅层32，使得下层包含有外延层14的基材10曝露出来，剩余的氧化硅层32形成一第二自我对准间隙壁38，第一自我对准间隙壁36和第二自我对准间隙壁38于位于接触洞30内的基材10上定义出一凹槽40，整个第二自我对准间隙壁38的截面为梯形，此外，第二自我对准间隙壁38夹在包含有外延层14的基材10和第一自我对准间隙壁36之间，但在栅极结构12和第一自我对准间隙壁36之间并没有第二自我对准间隙壁38。此外，移除曝露的氧化硅层32的方式可以使用一预清洗制作工艺，预清洗制作工艺使使用等离子体进行，并且将待移除的氧化硅层32曝露在含有三氟化氮以及氨气中，此外，视情况需要可以在等离子体内增加氢气或者氟化氢。然后形成一缓冲层42例如氮化钽或氮化钛等顺应地覆盖凹槽40，之后再形成一金属层44填满凹槽40，之后平坦化缓冲层42和金属层40以在凹槽40中用剩余的缓冲层42和金属层44形成一接触插塞52，在形成接触插塞之前，外延层14的上表面可选择性地形成一金属硅化物。至此根据本发明的第二优选实施例所制作的具有自我对准间隙壁的鳍状晶体管200业已完成。
本发明的第一优选实施例和第二优选实施例的方法不只可适用于第一优选实施例和第二优选实施例中所举例的鳍状晶体管，同时也可使用在制作平面晶体管，图10a的态样和图10b的态样，分别为利用本发明的第一优选实施例和第二优选实施例的方法所制作出的具有自我对准间隙壁的平面晶体管300/400。
图6为根据本发明的第三优选实施例所绘示的具有自我对准间隙壁的鳍状晶体管的示意图。如图6所示一种具有自我对准间隙壁的鳍状晶体管100包含一基材10，基材10包含一鳍状结构，但不限于此，基材10也可以为一平面的基底，至少二栅极结构12设置于基材10上，栅极结构12可以包含一栅极电极16和一栅极介电层18位于栅极电极16之下，另外一间隙壁20位于栅极结构12两侧，此外栅极电极16上可覆盖一栅极上盖层22。在最旁边的栅极结构12的一侧的基材10中，设有一浅沟槽隔离24。在二个栅极结构12之间的基材10中，包含有一外延层14或者是一掺质掺杂区(图未示)，在图6中以外延层14为例。
一复合自我对准间隙壁50设置于各个栅极结构12的一侧壁112，其中各个侧壁112相对，各个复合自我对准间隙壁50包含一第一自我对准间隙壁36和一第二自我对准间隙壁38，第一自我对准间隙壁36为一含氮材料层，第二自我对准间隙壁38为一氧化硅层，第二自我对准间隙壁38的厚度需大于10埃，优选需大于20埃，含氮材料层包含有氮化硅、氮碳化硅、氮氧化硅或氮碳氧化硅等，但不限于此，其它的含氮材料也可以视情况使用。第二自我对准间隙壁38夹在包含有外延层14的基材10和第一自我对准间隙壁36之间并且夹在栅极结构12和第一自我对准间隙壁36之间，此外，整个第二自我对准间隙壁38的截面为L形。在复合自我对准间隙壁50和间隙壁20之间可选择性地保留介电层26/28。再者一接触插塞52设置于复合自我对准间隙壁50之间并且接触外延层14。
图9为根据本发明的第四优选实施例所绘示的具有自我对准间隙壁的鳍状晶体管的示意图。第四优选实施例和第三优选实施例的不同之处在于第四优选实施例的整个第二自我对准间隙壁38为梯形，并且第二自我对准间隙壁38仅夹在包含有外延层14的基材10和第一自我对准间隙壁36之间，但在栅极结构12和第一自我对准间隙壁36之间并没有第二自我对准间隙壁38，再者，基材10一定要是硅基材。其余的元件位置和材料，大致和第三优选实施例相同，在此不再赘述。
图10a为根据本发明的第五优选实施例所绘示的具有自我对准间隙壁的平面晶体管的示意图。和第三优选实施例的不同之处在于第五优选实施例是平面晶体管，也就是说，基材10为平面的基底，并且在栅极结构12之间的基材10中没有外延层，而是掺质掺杂区114。其余的元件位置和材料，大致和第三优选实施例相同，在此不再赘述。
图10b为根据本发明的第六优选实施例所绘示的具有自我对准间隙壁的平面晶体管的示意图。和第五优选实施例的不同之处在于第六优选实施例中整个第二自我对准间隙壁38为梯形，并且第二自我对准侧壁38子仅夹在包含有掺质掺杂区114的基材10和第一自我对准间隙壁36之间，但在栅极结构12和第一自我对准间隙壁36之间并没有第二自我对准侧壁38。其余的元件位置和材料，大致和第五优选实施例相同，在此不再赘述。
在第一优选实施例和第二优选实施例中，利用氧化硅层32作为蚀刻含氮材料层34的蚀刻停止层，之后再用预清洗制作工艺移除氧化硅层32，其优点在于预清洗制作工艺本来就是在不同的制作工艺之间会使用的预清洗步骤，因此，不需为了移除氧化硅层32额外增加其它步骤，再者，预清洗制作工艺针对硅基底和氧化硅的选择比极高，通常氧化硅比硅基底的选择比大于20:1，因此在移除氧化硅层32时，完全不会伤害到氧化硅层32下方的硅基底或外延层14。传统其它以氮化硅作为蚀刻停止层的情况，由于移除氮化硅需使用热磷酸，但是热磷酸对硅基底和氮化硅的选择比不高，因此在移除氮化硅的同时，会伤害到硅基底或外延层的表面。因此本发明使用氧化硅作为蚀刻停止层可避免伤害到硅基底或外延层的表面的情况。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (19)

1.一种具有自我对准间隙壁的半导体结构的制作方法，包含：
提供一基材，至少二栅极结构设置于该基材上，位于该多个栅极结构之间的该基材曝露出来；
形成一氧化硅层覆盖曝露的该基材；
形成一含氮材料层覆盖该多个栅极结构和该氧化硅层；
蚀刻该含氮材料层形成一第一自我对准间隙壁于各该栅极结构的一侧壁，并且曝露出部分的该氧化硅层，其中各该侧壁相对；
移除曝露的该氧化硅层以形成一第二自我对准间隙壁，其中该第一自我对准间隙壁和该第二自我对准间隙壁于该基材上定义出一凹槽；以及
形成一接触插塞于该凹槽中。
2.如权利要求1所述的具有自我对准间隙壁的半导体结构的制作方法，其中该氧化硅层的形成方式包含氧化该曝露的该基材以形成该氧化硅层。
3.如权利要求2所述的具有自我对准间隙壁的半导体结构的制作方法，其中整个该第二自我对准间隙壁的截面为梯形。
4.如权利要求2所述的具有自我对准间隙壁的半导体结构的制作方法，其中该第二自我对准间隙壁仅夹在该基材和该第一自我对准间隙壁之间。
5.如权利要求1所述的具有自我对准间隙壁的半导体结构的制作方法，其中该氧化硅层的形成方式包含利用沉积制作工艺形成该氧化硅层，并且该氧化硅层覆盖曝露的该基材和该多个栅极结构。
6.如权利要求5所述的具有自我对准间隙壁的半导体结构的制作方法，其中整个该第二自我对准间隙壁的一截面为L形。
7.如权利要求5所述的具有自我对准间隙壁的半导体结构的制作方法，其中该第二自我对准间隙壁夹在该基材和该第一自我对准间隙壁之间并且夹在各该栅极结构和该第一自我对准间隙壁之间。
8.如权利要求1所述的具有自我对准间隙壁的半导体结构的制作方法，其中位于该多个栅极结构之间的该基材包含外延层或掺质掺杂区。
9.如权利要求1所述的具有自我对准间隙壁的半导体结构的制作方法，其中该基材包含鳍状结构或平面硅基底。
10.如权利要求1所述的具有自我对准间隙壁的半导体结构的制作方法，其中该含氮材料层包含氮化硅、氮碳化硅或氮碳氧化硅。
11.如权利要求1所述的具有自我对准间隙壁的半导体结构的制作方法，其中移除曝露的该氧化硅层的方式包含使用一预清洗制作工艺，该预清洗制作工艺包含利用三氟化氮以及氨气。
12.如权利要求1所述的具有自我对准间隙壁的半导体结构的制作方法，其中蚀刻该含氮材料层形成该第一自我对准间隙壁时，以该氧化硅层作为一蚀刻停止层。
13.一种具有自我对准间隙壁的半导体结构，包含：
基材；
二栅极结构，设置于该基材上；
复合自我对准间隙壁，设置于各该栅极结构的一侧壁，其中各该侧壁相对，各该复合自我对准间隙壁包含一含氮材料层和一氧化硅层，该氧化硅层夹在该基材和该含氮材料层之间；以及
接触插塞，设置于该多个复合自我对准间隙壁之间。
14.如权利要求13所述的具有自我对准间隙壁的半导体结构，其中整个该氧化硅层的截面为一梯形。
15.如权利要求13所述的具有自我对准间隙壁的半导体结构，其中整个该氧化硅层的截面为一L形。
16.如权利要求15所述的具有自我对准间隙壁的半导体结构，其中该氧化硅层夹在该基材和该含氮材料层之间并且该氧化硅层夹在各该栅极结构和该含氮材料层之间。
17.如权利要求13所述的具有自我对准间隙壁的半导体结构，其中该含氮材料层包含氮化硅、氮碳化硅或氮碳氧化硅。
18.如权利要求13所述的具有自我对准间隙壁的半导体结构，其中该基材包含鳍状结构或平面硅基底。
19.如权利要求13所述的具有自我对准间隙壁的半导体结构，其中位于该多个栅极结构之间的该基材包含外延层或掺质掺杂区。
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