US9298052B2 - Display apparatus - Google Patents

Display apparatus Download PDF

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Publication number
US9298052B2
US9298052B2 US14/420,043 US201314420043A US9298052B2 US 9298052 B2 US9298052 B2 US 9298052B2 US 201314420043 A US201314420043 A US 201314420043A US 9298052 B2 US9298052 B2 US 9298052B2
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Prior art keywords
lead
portions
line
out lines
lines
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Expired - Fee Related
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US14/420,043
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US20150219944A1 (en
Inventor
Kazuyori Mitsumoto
Masahiro Yoshida
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Sharp Corp
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Sharp Corp
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Assigned to SHARP KABUSHIKI KAISHA reassignment SHARP KABUSHIKI KAISHA ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: YOSHIDA, MASAHIRO, MITSUMOTO, KAZUYORI
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • H01L27/3276—
    • H01L51/5246—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/842—Containers
    • H10K50/8426—Peripheral sealing arrangements, e.g. adhesives, sealants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/871—Self-supporting sealing arrangements
    • H10K59/8722—Peripheral sealing arrangements, e.g. adhesives, sealants
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line

Definitions

  • the present invention relates to a display device. More specifically, the present invention relates to a display device having a seal between two substrates facing each other.
  • Patent Document 1 discloses a display device that has a display region on which a gate line and a data line are formed so as to intersect each other with a gate insulating film therebetween, a display substrate including first, second, third, and fourth peripheral regions surrounding the four sides of the display region, an opposite substrate facing the display substrate and sandwiching liquid crystal therebetween, a seal line that is formed in an edge between the display substrate and the opposite substrate and that binds the display substrate to the opposite substrate, and a driver chip mounted on the first peripheral region of the display substrate adjacent to the first edge portion of the gate line.
  • the display substrate has first and second data signal applying lines disposed alternately sandwiching the gate insulating film and connecting the data line and the driver chip, and the first data signal applying line is formed such that a portion thereof overlaps the second data signal applying line such that the seal line is exposed.
  • Patent Document 3 discloses a liquid crystal display device that is formed by bonding a first substrate having a first electrode and an external connection terminal to a first substrate having a second electrode by a looped sealing member.
  • Patent Document 1 Japanese Patent Application Laid-Open Publication No. 2008-152261
  • Patent Document 3 WO 99/52011
  • an array substrate included in the display device related to Comparison Example 1 has lead-out lines 1018 a and 1018 b .
  • the lead-out lines 1018 a and 1018 b are disposed alternately within the frame region and are covered by a seal (not shown).
  • the material of the seal (hereinafter, also referred to as sealing member) is photocurable (ultraviolet curable, for example), and the seal includes the cured material of the sealing member.
  • the lead-out line 1018 a is provided in the same conductive layer as the gate bus line
  • the lead-out line 1018 b is provided in the same conductive layer as the source bus line.
  • the conductive layer having the gate bus line is also referred to as the gate layer and the conductive layer having the source bus line is also referred to as the source layer.
  • Comparison Example 1 makes it possible for the frame portion to be made narrower than if all of the lead-out lines are provided in the same conductive layer, because a plurality of lead-out lines can be disposed within a narrower region.
  • the sealing member cannot be sufficiently cured, thereby resulting in a decrease in panel strength and causing defects such as display anomalies. This is because a sufficient light transmissive region cannot be secured due to lead-out lines blocking a large portion of light (ultraviolet light, for example) radiated from the array substrate side to the sealing member.
  • the reason for radiating light from the array substrate side is because, usually, a light-shielding member such as a BM is formed on the opposite substrate that faces the array substrate.
  • the array substrate included in the display device related to Comparison Example 2 has lead-out lines 1118 a and 1118 b
  • the array substrate included in the display device related to the Comparison Example 3 has lead-out lines 1218 a and 1218 b , as shown in FIG. 22 .
  • Comparison Examples 2 and 3 are substantially the same as Comparison Example 1.
  • the lead-out line 1118 b partially overlaps the lead-out line 1118 a .
  • the lead-out line 1218 a is bent in a zigzag pattern, and the lead-out line 1218 b partially overlaps the lead-out line 1218 a .
  • the present invention takes into consideration the above-mentioned situation, and an object thereof is to provide a display device that can suppress defects from taking place due to sealing members not curing, and that can suppress defective products from being manufactured due to shifts in alignment, and in addition, can reduce variation among individual products in the time for curing sealing members and power consumption.
  • the inventors of the present invention took into consideration the above-mentioned situation and performed various research on a display device that can suppress defects caused by sealing members not curing and defective products from occurring due to shifts in alignment, and in addition, that can reduce the variation in the curing time of sealing members and the power consumption among individual products.
  • the inventors focused on the plan view patterns of the lead-out lines under the seal.
  • the inventors found that a sufficient light transmissive region can be secured under the seal by two lead-out lines (first and second lead-out lines) both having a first portion and a second portion, the first and second portions being respectively provided in different conductive layers such that the first and second portions extend in the first direction in a plan view and that one of the first and second portions partially overlaps the other.
  • a feature of the present invention includes a display device (hereinafter, also referred to as display device related to the present invention) having a plurality of pixels, including:
  • the plurality of lead-out lines include a first lead-out line and a second lead-out line
  • first lead-out line and the second lead-out line include, under the seal, a first portion and a second portion, respectively,
  • first portion and the second portion partially overlaps with each other
  • first portion has one or more third portions located on one side of the second portion, and has one or more fourth portions located on another side of the second portion in the plan view,
  • the second portion includes one or more fifth portions located on one side of the first portion, and one or more sixth portions located on another side of the first portion in the plan view, and
  • the first substrate may have at least one insulating film provided on the insulating substrate, and the plurality of conductive layers may be stacked alternately with at least one insulating film mentioned above.
  • the respective functions of the aforementioned at least one insulating film are not limited in particular, but each of the aforementioned at least one insulating film usually functions as a gate insulating film or an interlayer insulating film.
  • the boundaries of the bus lines and the lead-out lines are set to be on the outline of the display region, in which the bus lines are disposed within the display region and the lead-out lines are disposed within the frame region.
  • the first substrate have at least two insulating films interposed between the first portion and the second portion.
  • the first substrate has at least two insulating films interposed between the conductive layer having the first portion and the conductive layer having the second portion.
  • At least one of the first portion and the second portion may have a wave shape in the plan view.
  • the first and/or second portion can be formed in a suitable pattern for the die-to-die comparison test.
  • one or more of the first and the second portions be formed in a sine wave shape, a trapezoid wave shape, or a triangle wave shape in a plan view.
  • the plurality of lead-out lines include a plurality of the first lead-out lines
  • each of the plurality of the first portions is formed in a trapezoid wave shape in the plan view and include flat portions parallel to the first direction and slanted portions that extend diagonally with respect to the first direction,
  • angles respectively formed between the first direction and the plurality of slanted portions of the plurality of first portions are 15° or less.
  • the aforementioned angle needs to be set as 11.x° ( ⁇ 12° or less in order to prevent the width of the slanted portion becoming smaller than the width of the flat portion by 0.1 ⁇ m or more, and in order to prevent the gap between the slanted portions of the first portions adjacent to each other from becoming smaller than the gap between the respective flat portions by 0.1 ⁇ m or more.
  • This 0.1 ⁇ m value is the smallest unit on figures generally used for designing masks during the manufacturing process, and thus, this means that the design dimensions do not differ substantially as long as there is no difference that is 0.1 ⁇ m or more.
  • the width of the slanted portion can be made substantially the same as the width of the flat portion, and in order to make the gap between the slanted portions and the gap between the flat portions substantially the same, it is preferable that the angle be 12° or less.
  • the upper limit was set as 15° based on this 12° angle after taking into account practical applicability.
  • the angle is set at 15°, and if the difference in width between the slanted portion and the flat portion is 0.1 ⁇ m or less, then a difference of approximately 0.1 ⁇ m to 0.2 ⁇ m occurs between a gap between the slanted portions and a gap between the flat portions.
  • the difference in the gap between the slanted portions and the flat portions are 0.1 ⁇ m or less, then a difference of approximately 0.1 ⁇ m to 0.2 ⁇ m occurs between the width of the slanted portion and the flat portion.
  • this level of difference is within a practically acceptable range considering the manufacturing error of a mask (in general, 0.2 ⁇ m to 0.3 ⁇ m).
  • the present invention can realize a display device that can suppress occurrence of defects due to a sealing member being uncured and occurrence of defective products due to shifts in alignment, and furthermore, variations in curing time of the sealing member and power consumption among display devices can be reduced in case a shift in alignment occurs.
  • FIG. 2 is a schematic plan view of lead-out lines included in the display device of Embodiment 1.
  • FIG. 3 is a schematic plan view of lead-out lines included in the display device of Embodiment 1.
  • FIG. 4 is a schematic plan view of lead-out lines included in the display device of Embodiment 1.
  • FIG. 5 is a schematic cross-sectional view of FIG. 2 along a line A-B of a liquid crystal panel included in the display device of Embodiment 1.
  • FIG. 7 shows the results of the measurements performed regarding the overlapping area and the light transmissive portion area for each of the plan view patterns of the lead-out lines related to Embodiments 1 and 2.
  • FIG. 9 is a schematic plan view of a liquid crystal panel included in a display device of Embodiment 3.
  • FIG. 11 is a schematic plan view of lead-out lines included in a display device of Embodiment 4.
  • FIG. 12 is a schematic cross-sectional view of FIG. 11 along a line C-D of a liquid crystal panel included in the display device of Embodiment 4.
  • FIG. 13 is a schematic plan view of lead-out lines included in a display device of a modification example of Embodiments 1 to 4.
  • FIG. 15 is a schematic plan view of lead-out lines included in a display device of a modification example of Embodiments 1 to 4.
  • FIG. 17 is a schematic plan view of lead-out lines included in a display device of a modification example of Embodiments 1 to 4.
  • FIG. 18 is a schematic plan view of lead-out lines included in a modification example of Embodiments 1 to 4.
  • FIG. 20 is a schematic plan view of lead-out lines included in a display device of Comparison Example 1.
  • FIG. 21 is a schematic plan view of lead-out lines included in a display device of Comparison Example 2.
  • the conductive layer having the source bus lines is also referred to as the source layer
  • the conductive layer having the gate bus lines is also referred to as the gate layer.
  • the lead-out line or a portion thereof in this state may be bent such as in a line graph shape, a triangle wave shape, or a trapezoid wave shape, or may be curved such as in a smoothed line shape or in a sine wave shape.
  • the degree of bending (angle of bending or curvature, for example) of the lead-out line or a portion thereof is not limited in particular.
  • a display device of Embodiment 1 will be described with reference to FIGS. 1 to 5 .
  • the display device of Embodiment 1 is a liquid crystal display that is active matrix driven and transmissive. As shown in FIG. 1 , the display device has a liquid crystal panel 1 , a backlight (not shown) disposed behind the liquid crystal panel 1 , a control unit (not shown) that drives and controls the liquid crystal panel 1 and the backlight unit, and a flexible substrate (not shown) that connects the control unit to the liquid crystal panel 1 .
  • the liquid crystal panel 1 includes an active matrix substrate (array substrate) 10 , an opposite substrate 50 that faces the array substrate 10 , a liquid crystal layer (not shown) and a seal 62 disposed between the substrates 10 and 50 , an alignment film (not shown) disposed on a surface of the array substrate 10 on the liquid crystal layer side, an alignment film (not shown) disposed on a surface of the opposite substrate 50 on the liquid crystal layer side, and a driver chip 5 that is mounted on the array substrate 10 and that functions as a source driver and a gate driver.
  • the liquid crystal panel 1 , the array substrate 10 , and the opposite substrate 50 include an area (display region) 7 corresponding to the display unit 2 , and an area (frame region) 8 corresponding to the surrounding area of the display region 7 .
  • the driver chip 5 is a driving circuit for the source bus line and the gate bus line mentioned later.
  • the thermosetting type sealing member is suitable for use.
  • the sealing members include acrylic resin and/or epoxy resin.
  • the Photolec S series (Sekisui Chemical Co., Ltd.) that has the epoxy acrylic resin as a main component can be raised as a specific example of a photo-heat combination type sealing member.
  • the array substrate 10 is provided towards the rear of the liquid crystal display, and the opposite substrate 50 is provided towards the viewer side.
  • Polarizing plates (not shown) are bonded on the surfaces of the substrates 10 and 50 opposite to the liquid crystal layer. These polarizing plates are generally disposed in a crossed Nicols state.
  • the driver chip 5 is mounted on an area of the array substrate 10 that does not face the opposite substrate 50 , or in other words, the area protruding from the opposite substrate 50 (hereinafter, protruding region) using COG (chip on glass) technology.
  • the array substrate 10 has terminals 26 , 27 a , 27 b , 28 , 29 , and 30 within the protruding region, at least 4 m number of source bus lines 12 a and 12 b vertically crossing the display region 7 , at least 2 n number of gate bus lines 13 horizontally crossing the display region 7 , at least 2 n number of common bus lines 17 horizontally crossing the display region 7 , at least 2 m number of lead-out lines 18 a formed within the frame region 8 , at least 2 n number of lead-out lines 18 c formed within the frame region 8 , a common trunk wiring line 16 formed within the frame region 8 so as to surround the display region 7 , and an input wiring line 25 formed within the frame region 8 .
  • Each of the gate bus lines 13 are connected to the first output section of the driver chip 5 through the corresponding lead-out lines 18 c and the terminals 26 .
  • a flexible substrate is mounted in the region where the terminals 28 and 30 are provided (area surrounded by a bolded two-dot chain line in FIG. 1 ).
  • the driver chip 5 has a plurality of input portions, and each input portion is supplied with signals or electricity from the control unit through the flexible substrate, the terminals 28 , the input wiring lines 25 , and the terminals 29 .
  • a common signal is supplied to the common trunk wiring line 16 from the control unit through the flexible substrate and the terminal 30 .
  • the common signal is a signal applied to all of the pixels.
  • the common bus lines 17 are connected to the common trunk wiring lines 16 within the frame region 8 , and a common signal is applied to the common bus line 17 from the common trunk wiring line 16 .
  • the source bus lines 12 a and 12 b are disposed alternately and the lead-out lines 18 a and 18 b are respectively disposed on the upper side and the lower side of the display region 7 .
  • the respective source bus lines 12 a are connected to the second output section of the driver chip 5 through the corresponding lead-out lines 18 a and the terminals 27 a .
  • Each of the respective lead-out lines 18 a extends from a corresponding source bus line towards an edge 10 a of the array substrate 10 , and then extends along the edge 10 a towards the protruding region.
  • Each of the source bus lines 12 b is connected to the third output section of the driver chip 5 through the corresponding lead-out line 18 b and the terminal 27 b .
  • Each of the respective lead-out lines 18 b extends from a corresponding source bus line towards an edge 10 b of the array substrate 10 , and then extends along the edge 10 b towards the protruding region.
  • the edge 10 b faces the edge 10 a .
  • At least a portion of the respective lead-out lines 18 a and 18 b are covered by the seal 62 .
  • the lead-out lines 18 a include a lead-out line 18 aa that is connected to the source bus line number 4 m ⁇ 3, and a lead-out line 18 ab connected to the source bus line number 4 m ⁇ 1.
  • the lead-out lines 18 b include a lead-out line 18 ba that is connected to the source bus line number 4 m ⁇ 2, and a lead-out line 18 bb connected to the source bus line number 4 m.
  • Each of the sub pixels 4 corresponds to an area delineated by the source bus lines 12 a and 12 b and the common bus lines 17 (hereinafter, also referred to as the sub pixel area).
  • the array substrate 10 has a plurality of TFTs (not shown) and a transparent pixel electrode (not shown) connected to each of the TFTs.
  • a TFT and a pixel electrode are provided in each of the sub pixel areas.
  • Each TFT is connected to the source bus line 12 a or 12 b and the gate bus line 13 .
  • the plan view pattern of the lead-out line 18 a in the area where the seal 62 exists (area surrounded by bold dotted lines in FIG. 1 ) will be described with reference to FIGS. 2 to 4 .
  • the lead-out line 18 b is formed in a similar manner to the lead-out line 18 a , and thus an explanation of the lead-out line 18 b will be omitted.
  • each of the lead-out lines 18 aa and 18 ab extend in a horizontal direction (direction corresponding to the first direction, hereinafter, also referred to as extending direction), and is disposed in a bent state in a plan view.
  • the extending direction is substantially parallel to the edge 10 a of the array substrate 10 .
  • the width of the overlapping area between the flat portions of the lead-out lines 18 ab and 18 aa are not limited in particular, and can be set as appropriate, but the width may be set as 1.5 ⁇ m as shown in FIG. 2 , for example.
  • the length of the flat portions is not limited, and can be set as appropriate, but the length may be set as 30 ⁇ m as shown in FIGS. 3 and 4 , for example.
  • the respective lead-out lines 18 aa and 18 ab may be formed without a flat portion so as to be in a triangle wave shape in a plan view.
  • the angle between the extending direction and the slanted portion is not limited in particular, and can be set as appropriate, but the angle may be set as approximately 3° as shown in FIGS. 3 and 4 , for example.
  • the array substrate 10 has a transparent insulating substrate 11 such as a glass substrate or a plastic substrate.
  • a gate layer is formed on the insulating substrate 11 , and a portion of the lead-out line 18 ab , a portion of the lead-out line 18 bb , the gate bus line 13 , the common bus line 17 , and the input wiring line are provided in the gate layer.
  • the portion 16 a of the common trunk wiring line 16 (hereinafter, also referred to as lower layer portion) that intersects the lead-out lines 18 a and 18 b is also provided in the gate layer.
  • the gate layer is formed of a conductive film including materials such as molybdenum (Mo), titanium (Ti), aluminum (Al), copper (Cu), or an alloy of these.
  • the gate layer may be formed of a multilayer film of these conductive films.
  • a semiconductor layer (not shown) is formed on the gate insulating film 31 .
  • Elements Group 14 semiconductors such as silicon, oxide semiconductors, and the like can be used as a material for the semiconductor layer, but oxide semiconductors are more suitable. It is preferable that the oxide semiconductor have at least one of an element in a group including indium (In), gallium (Ga), zinc (Zn), aluminum (Al), and silicon (Si), along with oxygen (O), and it is preferable that the oxide semiconductor includes In, Ga, Zn, and O. If an oxide semiconductor is used, then the mobility of the TFT can be made higher than if amorphous silicon is used.
  • the crystalline structure of the semiconductor layer is not limited in particular, and the semiconductor layer may be monocrystalline, polycrystalline, amorphous, or microcrystalline, and may include two or more of these crystalline structures.
  • a source layer is formed on the gate insulating film 31 and the semiconductor layer, and the lead-out lines 18 aa and 18 ba , the source bus lines 12 a and 12 b , and the drain electrode (not shown) of the TFT are formed in the source layer. Furthermore, as shown in FIG. 1 , other than the lower layer portion 16 a , the common trunk wiring lines 16 has a portion (hereinafter, upper layer portion) 16 b intersecting the lead-out lines 18 c also provided in the source layer.
  • the source layer is formed of a conductive film including materials such as Mo, Ti, Al, Cu, or an alloy of these.
  • the source layer may be formed of a multilayer film of these conductive films.
  • the interlayer insulating film 32 is formed on the source layer and the pixel electrodes.
  • the interlayer insulating film 32 includes an inorganic insulating film 32 a and an organic insulating film 32 b layered on the interlayer insulating film 32 a .
  • Possible materials for the inorganic insulating film 32 a include inorganic insulating materials such as silicon nitride (SiNx) or silicon oxide, for example.
  • Photosensitive resin such as photosensitive acrylic resin can be used as a material of the organic insulating film 32 b , for example.
  • the interlayer insulating film 32 does not need to include the organic insulating film 32 b.
  • the pixel electrode is formed on the interlayer insulating film 32 , and is connected to the drain electrode through a contact hole (not shown) that penetrates the interlayer insulating film 32 .
  • Possible materials for the pixel electrode include transparent conductive materials such as indium tin oxide (ITO) and indium zinc oxide (IZO), for example.
  • the pixel electrode is formed on the gate insulating film 31 . In this case, a portion of the pixel electrode is connected to the drain electrode by overlapping the drain electrode.
  • the opposite substrate 50 has a transparent insulating substrate 51 such as a glass substrate or a plastic substrate, a black matrix (BM) 52 that functions as a light-shielding member, color filters having a plurality of colors (not shown), and a plurality of spacers (not shown) having a pillar shape.
  • the BM 52 is formed so as to shield light for the frame region 8 and the area opposing the bus line.
  • Each of the color filters is provided in the display region 7 , and formed so as to cover the area demarcated by the BM 52 , or in other words, the opening of the BM 52 .
  • the opposite substrate 50 may have an overcoat film that covers all of the color filters.
  • the pillar shaped spacer is disposed within the light-shielding area of the BM 52
  • the liquid crystal mode is not limited in particular, but if the liquid crystal mode is a type that uses vertical electric fields such as TN (twisted nematic) mode, VA (vertical alignment) mode, and MVA (multi-domain vertical alignment) mode, then, in general, the opposite substrate 50 has an opposite electrode to which a common signal is applied on the BM 52 and the color filters.
  • TN twisted nematic
  • VA vertical alignment
  • MVA multi-domain vertical alignment
  • the lead-out lines 18 aa and 18 ba are provided in the source layer, and the lead-out lines 18 ab and 18 bb are provided in the gate layer, and the lead-out lines 18 ab and 18 bb partially overlap the lead-out lines 18 aa and 18 ba , respectively. Therefore, the light transmissive region can be sufficiently secured.
  • the portions 41 a and 41 b are disposed alternately along the extending direction, and the portions 42 a and 42 b are disposed alternately along the extending direction. Furthermore, the lead-out line 18 b is also formed in a similar manner to the lead-out line 18 a . As a result, even if a shift in alignment of the gate layer and/or the source layer takes place, and the area of one of the portions 41 a and 41 b decreases, the area of the other portion increases. The same can be said for the portions 42 a and 42 b .
  • the lead-out lines 18 aa and 18 ab are respectively disposed in a bent state, and thus the parasitic capacitance of the present embodiment can be made even smaller compared to Embodiment 2 mentioned later.
  • each of the lead-out lines 18 aa and 18 ab are formed in a wave shape in a plan view.
  • the presence or absence of the lead-out lines 18 aa and 18 ab can be tested.
  • each of the lead-out lines 18 aa and 18 ab be formed such that a same shape (repeating unit) is repeated (repeated shape).
  • a die-to-die comparison can be efficiently performed for the smallest repeating unit or for a plurality of repeating units.
  • a display device of Embodiment 2 will be described with reference to FIG. 6 .
  • the present embodiment is substantially the same as Embodiment 1 except that the plan view pattern of the lead-out lines under a seal is different. Therefore, in the present embodiment, mainly the characteristics particular to the present embodiment will be described, and explanations covered in Embodiment 1 will be omitted.
  • the display device of the present embodiment has a lead-out line 118 a that corresponds to the lead-out lines 18 aa and 18 ba , and a lead-out line 118 b that corresponds to lead-out lines 18 ab and 18 bb .
  • the lead-out line 118 a is provided in the gate layer, and the lead-out line 118 b is provided in the source layer, the lead out line 118 b partially overlapping the lead-out line 118 a .
  • sufficient light transmissive region can be secured.
  • the lead-out line 118 b is formed in a triangle wave shape and is disposed so as to be bent in a zigzag state, but the lead-out line 118 a is formed in a straight line.
  • Each of the lead-out lines 118 b does not have a flat portion that is parallel to the extending direction, and has a plurality of slanted portions that extend diagonally with respect to the extending direction.
  • the lead-out line 118 a may be formed in a triangle wave shape and the lead-out line 118 b may be formed in a straight line.
  • the lead-out line 118 b has a plurality of portions 142 a (portions corresponding to the fifth portion) located on a side of the lead-out line 118 a , and a plurality of portions 142 b (portions corresponding to the sixth portion) located on another side (bottom side in FIG. 6 ) of the lead-out line 118 a , the portions 142 a and 142 b being disposed alternately along the extending direction, in a plan view.
  • Embodiment 1 the manufacturing of a product having greater parasitic capacitance than a standard product manufactured according to the blueprint can be prevented, and the variation in the characteristic value (area of the light transmissive region, size of the parasitic capacitance, and the like, for example) of each product can be reduced.
  • FIGS. 7 and 8 Results of testing the effects of Embodiments 1 and 2 will be explained with reference to FIGS. 7 and 8 .
  • FIGS. 7 and 8 the results of the measurements performed regarding the plan view pattern of the lead-out lines related to Embodiments 1 and 2, Comparison Examples 1 to 3, and the overlapping area of the respective patterns and the light transmissive area can be shown.
  • the lead-out line provided in the gate layer is formed in a zigzag pattern, and the lead-out line provided in the source layer is formed in a straight line.
  • the lead-out line of the gate layer has a portion that is located on the right side of the lead-out line of the source layer, but does not have a portion located on the left side.
  • the lead-out line of the source layer has a portion that is located on the left side of the lead-out line of the gate layer, but does not have a portion located on the right side.
  • the pattern of Embodiment 1 has a lead-out line provided in the gate layer, and a lead-out line provided in the source layer formed in a zigzag pattern.
  • the lead-out line provided in the source layer is formed in a zigzag pattern
  • the lead-out line provided in the gate layer is formed in a straight line.
  • the location of the lead-out line in the source layer relative to the lead-out line in the gate layer changes in a prescribed pattern.
  • the width of each of the lead-out lines is set to be 3 ⁇ m and the gap between the lead-out lines provided in the same layer is set to be 3 ⁇ m.
  • the overlapping area is an area in which the lead-out line of the gate layer and the lead-out line of the source layer overlap each other, and the light transmissive area is an area in which neither of the lead-out lines exists.
  • the size of the capacitance (parasitic capacitance) formed by the lead-out line of the gate layer and the lead-out line of the source layer is proportionate to the size of the overlapping area.
  • the overlapping area and the light transmissive area of the respective patterns shown in FIGS. 7 and 8 were measured (see column labeled typ). The results correspond to that of a standard product manufactured according to the blue print. Furthermore, the overlapping area and the light transmissive area were measured for a pattern in which the lead-out line of the gate layer or the lead-out line of the source layer is moved for a prescribed distance (value written in the amount of alignment shifting section) in a horizontal direction in FIGS. 7 and 8 . This result is an equivalent of a case in which the alignment of the gate layer and/or the source layer did not go as planned during the photolithography process when manufacturing the array substrate.
  • the parasitic capacitance can be made smaller, and the area of the light transmissive portion can be secured.
  • the change in overlapping area and the light transmissive area is large if the alignment shifts.
  • a product having even greater parasitic capacitance compared to a standard product would be formed. If a standard product having an overlapping area of 135 ⁇ m 2 is not a defective product, and if a product having an overlapping area of 155 ⁇ m 2 is a defective product, then there is a possibility that a defective product will be formed in Comparison Examples 2 and 3 due to shifts in alignment, for example.
  • the light transmissive area can be secured. Furthermore, it was found that the change in overlapping area and the light transmissive area is small if the alignment shifts. In addition, even if the alignment shifts, a product having a larger parasitic capacitance than a standard product will not be manufactured. As a result, in a case in which a standard product having an overlapping area of 135 ⁇ m 2 is not a defective product, a defective product due to shifts in alignment in Embodiments 1 and 2 will not occur.
  • the patterns of Embodiments 1 and 2 has an advantage in that the seal can be tested more easily.
  • a seal test involves examining whether the position of the seal and the width thereof is appropriate, whether the seal has disconnections, whether the sealing member is cured sufficiently, and the like by observation equipment such as a microscope.
  • Embodiment 1 has a smaller capacitance compared to a pattern of Embodiment 2, and it has been found that Embodiment 1 has an advantage over Embodiment 2 in terms of decreasing power consumption.
  • the particular pattern of the lead-out line mentioned above is not a lead-out line for the source bus line, but a lead-out line for the gate bus line.
  • mainly the characteristics particular to the present embodiment will be described, and explanations covered in Embodiment 1 will be omitted.
  • a liquid crystal panel 201 included in the present embodiment has a display unit 202 , and a plurality of pixels 203 are disposed on the display unit 202 .
  • Each of the pixels 203 is formed of horizontally long sub pixels 204 having a plurality of colors (three colors including red, green, and blue, for example).
  • the liquid crystal panel 201 has an array substrate 210 , an opposite substrate 250 , a seal 262 , and a driver chip 205 that functions as a source driver and a gate driver. Furthermore, the liquid crystal panel 201 , the array substrate 210 , and the opposite substrate 250 include an area (display region) 207 corresponding to the display unit 202 , and a region (frame region) 208 surrounding the display region 207 .
  • the array substrate 210 includes at least 2 m number of source bus lines 212 , at least 4 n number of gate bus lines 213 a and 213 b , at least 4 n number of common bus lines 217 , at least 2 n number of lead-out lines 218 a , at least 2 n number of lead-out lines 218 b , at least 2 m number of lead-out lines 218 c , and a common trunk wiring line 216 provided in the gate layer.
  • Each of the source bus lines 212 are connected to the corresponding lead-out lines 218 c .
  • a flexible substrate is mounted in an area surrounded by a bolded two-dot chain line.
  • the gate bus lines 213 a and 213 b are disposed alternately, and the lead-out lines 218 a and 218 b are respectively disposed on the right side and the left side of the display region 207 .
  • Each of the gate bus lines 213 a are connected to the corresponding lead-out lines 218 a .
  • Each of the lead-out lines 218 a extends from the corresponding gate bus line to an edge 210 a of the array substrate 210 , and extends towards the protruding region along the edge 210 a .
  • Each of the gate bus lines 213 b is connected to the corresponding lead-out lines 218 b .
  • Each of the lead-out lines 218 b extends from the corresponding gate bus line to an edge 210 b of the array substrate 210 , and extends towards the protruding region along the edge 210 b . At least a portion of each of the lead-out lines 218 a and 218 b is covered by the seal 262 .
  • the lead-out lines 218 a includes a lead-out line 218 aa connected to gate bus line number 4 n - 3 and a lead-out line 218 ab connected to gate bus line number 4 n ⁇ 1.
  • the lead-out lines 218 b includes a lead-out line 218 ba connected to the gate bus line number 4 n ⁇ 2, and a lead-out line 218 bb connected to the gate bus line number 4 n.
  • the respective lead-out lines 218 ab and 218 bb include a portion in an outer side (hereinafter, also referred to as outer side portion) of the common trunk wiring line 216 , a portion intersecting (hereinafter, also referred to as intersection) the common trunk wiring line 216 , and a portion corresponding to the portion (hereinafter, also referred to as connecting portion) between the intersection and the gate bus lines.
  • the outer side portion is provided in the gate layer
  • the intersection is provided in the source layer
  • the connecting portion is provided in the gate layer.
  • the outer side portion and the intersection are connected to each other through the contact hole, and the intersection and the connecting portion are connected to each other through the contact hole.
  • the lead-out line 218 c includes a lead-out line provided in the source layer and a lead-out line provided in the gate layer. These lead out lines are disposed alternately.
  • the lead-out lines 218 a and 218 b of Embodiment 1 have a similar plan view pattern under the seal 262 . Therefore, the present embodiment can also achieve a similar effect to that of Embodiment 1.
  • Embodiment 4 The display device of Embodiment 4 will be explained with reference to FIG. 10 .
  • the present embodiment has the characteristic pattern mentioned above of the lead-out line provided in another conductive layer that is not the gate layer and the source layer.
  • the present embodiment mainly the characteristics particular to the present embodiment will be described, and explanations covered in Embodiment 1 will be omitted.
  • the display device of the present embodiment is a liquid crystal display of a fringe field switching (FFS) type that is a type of a horizontal alignment mode liquid crystal display.
  • FFS fringe field switching
  • the orientation of the liquid crystal molecules is controlled by applying an electric field (horizontal electric field) that is in a horizontal direction (parallel direction) to the substrate surface to liquid crystal molecules having positive or negative dielectric anisotropy.
  • a liquid crystal panel 301 included in the display device of the present embodiment has a display unit 302
  • the liquid crystal panel 301 includes an array substrate 310 , an opposite substrate 350 , a seal 362 , a horizontal alignment film (not shown) provided on a surface of the array substrate 310 on the liquid crystal layer side, a horizontal alignment film (not shown) provided on a surface of the opposite substrate 350 on the liquid crystal layer side, and a driver chip 305 that functions as a source driver and a gate driver.
  • the liquid crystal panel 301 , the array substrate 310 , and the opposite substrate 350 have an area (display region) 307 corresponding to the display unit 302 , and an area (frame region) 308 surrounding the display region 307 .
  • the common electrode 315 in each of the sub pixel area, slits that are parallel to each other (long and narrow opening, not shown) are formed. Within the frame region 308 , the common electrode 315 is connected to the common trunk wiring line 316 through the contact hole 336 formed in the common trunk wiring line 316 , and a common signal is applied to the common electrode 315 from the common trunk wiring line 316 .
  • the common bus line 317 is provided directly above or below the common electrode 315 , and is connected to the common electrode 315 by being in direct contact to the common electrode 315 .
  • the common bus lines 317 are provided so as to reduce the resistance of the common electrode 315 , and are provided to suppress display defects such as shadowing.
  • the lead-out line 318 a includes a lead-out line 318 aa connected to the source bus line number 4 m ⁇ 3, and a lead-out line 318 ab connected to the source bus line number 4 m ⁇ 1.
  • the lead-out line 318 b includes the lead-out line 318 ba connected to the source bus line number 4 m ⁇ 2, and a lead-out line 318 bb connected to the source bus line number 4 m.
  • each of the lead-out lines 318 aa and 318 ba are provided in a conductive layer that includes the common bus line 317 (hereinafter, also referred to as common layer). It is preferable that each of the lead-out lines 318 aa and 318 ba be located outside the common trunk wiring line 316 and include a portion provided in the common layer, a portion located between the portion in the common layer and corresponding source bus lines, and a portion provided in the source layer. These portions are connected to each other through a contact hole. On the other hand, at least a portion of each of the lead-out lines 318 ab and 318 bb are provided in the gate layer.
  • each of the lead-out lines 318 ab and 318 bb be located outside the common trunk wiring line 316 , and include a portion provided in the gate layer, and a portion disposed in the source layer between the portion in the gate layer and the corresponding source bus line, in which all of these portions are connected to each other through a contact hole.
  • the lead-out line 318 c includes a lead-out line provided in a common layer and a lead-out line provided in a gate layer, and these lead-out lines are disposed alternately.
  • each of the lead-out lines 318 aa and 318 ab extend in a horizontal direction (direction corresponding to the first direction, hereinafter, also referred to as extending direction), and is disposed in a bent state in a plan view.
  • the plurality of lead-out lines 318 aa are disposed so as to be substantially parallel to each other, and are aligned in a direction (direction corresponding to the second direction) perpendicular to the extending direction.
  • the plurality of lead-out lines 318 ab are disposed so as to be substantially parallel to each other, and are aligned in a direction perpendicular to the extending direction.
  • each of the lead-out lines 318 aa and 318 ab is formed in a trapezoid wave shape in a plan view, and the lead-out lines 318 aa and 318 ab include a plurality of flat portions that are parallel to the extending direction, and a plurality of slanted portions that are at an angle with respect to the extending direction.
  • the lead-out line 318 ab partially overlaps the lead-out line 318 aa under the seal 362 .
  • Each of the lead-out lines 318 aa and 318 ab are disposed in a bent state in a plan view. Furthermore, the position of the lead-out line 318 b relative to the lead-out line 318 a changes in a prescribed pattern. Therefore, the present embodiment can also achieve the effect described in Embodiment 1.
  • the array substrate 310 has a transparent insulating substrate 311 .
  • a gate layer is formed on the insulating substrate 311 , and a portion of the lead-out line 318 ab , a portion of the lead-out line 318 bb , and the gate bus line 313 are provided in the gate layer.
  • a gate insulating film 331 is formed on the gate layer.
  • a semiconductor layer (not shown) is formed on the gate insulating film 331 .
  • a source layer is formed on the gate insulating film 331 and the semiconductor layer, and a portion of the respective lead-out lines, the source bus lines 312 a and 312 b , and the drain electrode (not shown) of the TFT are formed in the source layer.
  • the interlayer insulating film 332 is formed on the source layer.
  • the interlayer insulating film 332 includes an inorganic insulating film 332 a and an organic insulating film 332 b on the inorganic insulating film 332 a .
  • the interlayer insulating film 332 does not need to include the organic insulating film 332 b.
  • An interlayer insulating film 334 is formed on the pixel electrodes.
  • Possible materials for the inorganic insulating film 334 include inorganic insulating materials such as silicon nitride (SiNx) and silicon oxide, for example.
  • the common electrode 315 and the common layer are formed on the interlayer insulating film 334 . At least a portion of the lead-out lines 318 aa , at least a portion of the lead-out lines 318 ba , and the common bus lines 317 are provided in the common layer. Possible materials for the common electrode 315 include transparent conductive materials such as ITO and IZO, for example.
  • the common layer is formed of a conductive film including materials such as Mo, Ti, Al, Cu, or an alloy of these.
  • the common layer may be formed of a multilayer film of these conductive films.
  • the lead-out lines provided in the gate layer may be provide in the source layer.
  • three types of lead-out lines that are respectively provided in the gate layer, the source layer, and the common layer may be disposed.
  • the lead-out lines provided in the common layer may instead be provided in a conductive layer having a common electrode.
  • the conductive layer including the common electrode be formed of a conductive film including a material such as Mo.
  • the common bus line may be omitted.
  • the display device of the present embodiment may be a reflective type liquid crystal display or an organic EL display, and the lead-out lines provided in the common layer may be provided in a conductive layer including pixel electrodes.
  • the conductive layer including the pixel electrode be formed of a conductive film including a material such as Al or silver (Ag).
  • the display device of the respective embodiments may have lead-out lines 418 a and 418 b .
  • the lead-out lines 418 a are provided in a lower conductive layer
  • the lead-out lines 418 b are provided in an upper conductive layer.
  • the lead-out lines 418 a and 418 b extend in a horizontal direction (direction corresponding to the first direction, hereinafter, also referred to as extending direction), and are disposed in a bent state in a plan view.
  • the respective lead-out lines 418 a and 418 b are formed in a triangle wave shape in a plan view.
  • Each of the lead-out lines 418 a and 418 b does not have a flat portion that is parallel to the extending direction, and has a plurality of slanted portions that extend diagonally with respect to the extending direction.
  • the angle at which the respective lead-out lines are bent is not limited in particular, and can be set as appropriate, but the angle may be set as approximately 174°, for example.
  • Each of the lead-out lines 518 a and 518 b are formed in a trapezoid wave shape in a plan view, and the lead-out lines 518 a and 518 b include a plurality of flat portions that are parallel to the extending direction, and a plurality of slanted portions that are at an angle with respect to the extending direction.
  • the flat portion of the lead-out line 518 a and the flat portion of the adjacent lead-out line 518 b do not overlap.
  • the size of the respective gaps between the flat portions are not limited in particular, and can be set as appropriate, but may be set as 0.5 ⁇ m, for example.
  • the display device of the respective embodiments may have lead-out lines 618 a and 618 b .
  • the lead-out lines 618 a are provided in a lower conductive layer
  • the lead-out lines 618 b are provided in an upper conductive layer.
  • the lead-out lines 618 a and 618 b extend in a horizontal direction (direction corresponding to the first direction, hereinafter, also referred to as extending direction), and are disposed in a bent state in a plan view.
  • Each of the lead-out lines 618 a and 618 b are formed in a trapezoid wave shape in a plan view, and the lead-out lines 618 a and 618 b include a plurality of flat portions that are parallel to the extending direction, and a plurality of slanted portions that are at an angle with respect to the extending direction.
  • the angle between the extending direction and the slanted portion is set at substantially 12°.
  • the display device of the respective embodiments may have lead-out lines 718 a and 718 b .
  • the lead-out lines 718 a are provided in a lower conductive layer
  • the lead-out lines 718 b are provided in an upper conductive layer.
  • the lead-out lines 718 a and 718 b extend in a horizontal direction (direction corresponding to the first direction, hereinafter, also referred to as extending direction), and are disposed in a bent state in a plan view.
  • the gap between the slanted portions of the lead-out lines provided in the same conductive layer becomes narrow. If the respective gaps between the flat portions of the lead-out lines 718 a and 718 b are set as 5 ⁇ m, then the respective gaps between the slanted portions of the lead-out lines 718 a and 718 b become narrower, such as 4.1 ⁇ m, for example.
  • the display device of the respective embodiments may have the lead-out lines 818 a and 818 b .
  • the lead-out lines 818 a are provided in a lower conductive layer
  • the lead-out lines 818 b are provided in an upper conductive layer.
  • the lead-out lines 818 a and 818 b extend in a horizontal direction (direction corresponding to the first direction, hereinafter, also referred to as extending direction), and are disposed in a bent state in a plan view.
  • Each of the lead-out lines 818 a and 818 b are formed in a trapezoid wave shape in a plan view, and the lead-out lines 818 a and 818 b include a plurality of flat portions that are parallel to the extending direction, and a plurality of slanted portions that are at an angle with respect to the extending direction.
  • the position of the slanted portions of the plurality of lead-out lines provided in the same conductive layer changes gradually, and a gap between the slanted portions is secured.
  • the respective lead-out lines have two types of flat portions having different lengths, and the proportion of the length of the two types of flat portions of the plurality of lead-out lines provided in the same conductive layer is different.
  • the respective edges of the plurality of flat portions included in the lead-out lines provided in the same conductive layer be positioned on the same virtual line (straight line) 43 , the other edge be positioned on the same virtual line (straight line) 44 , and the virtual line 43 be substantially parallel to the virtual line 44 .
  • the angle between the extending direction and the respective slanted portions be less than or equal to 15°.
  • the virtual lines 43 and 44 being substantially parallel means that the angle of the virtual line 43 with respect to the virtual line 44 is less than or equal to 0.1° and it is preferable that the angle be less than or equal to 0.03°.
  • the pattern of the lead-out lines can be appropriately changed according to the number of lead-out lines (resolution), panel size, width of the frame region, and the like.
  • the pattern of the characteristic lead-out lines must be formed in at least the seal forming portion, and the pattern of the lead-out lines outside the seal forming portion is not limited.
  • the characteristic pattern mentioned above may be combined with the pattern shown in FIG. 19 , and the characteristic pattern mentioned above may be combined with the pattern in which the lead-out lines are provided only in one conductive layer (gate layer or source layer, for example).
  • the lead-out lines (lead-out lines 18 a and 18 b and the like, for example) extending in the protruding area along the edge of the array substrate are disposed vertically or horizontally on the display region, but may be disposed only on one side (top, bottom, right, or left side, for example) of the display region. In Embodiment 1, all of the lead-out lines connected to the source bus lines may be disposed on the top side of the display region.
  • the display device of the respective embodiments may be a monochrome display device, and in that case, the respective pixels do not need to be divided into a plurality of sub pixels.
  • the respective embodiments mainly described liquid crystal displays, but the type of display device related to the present embodiment is not limited to liquid crystal displays.
  • the display may be a microcapsule-type electrophoretic electronic paper, an organic or inorganic EL display, or the like, for example.
  • liquid crystal panel of the respective liquid crystal display may be provided with a reflective display unit that performs display through reflecting ambient light.
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