US8394722B2 - Bi-layer, tri-layer mask CD control - Google Patents

Bi-layer, tri-layer mask CD control Download PDF

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Publication number
US8394722B2
US8394722B2 US12/263,662 US26366208A US8394722B2 US 8394722 B2 US8394722 B2 US 8394722B2 US 26366208 A US26366208 A US 26366208A US 8394722 B2 US8394722 B2 US 8394722B2
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layer
etch
mask layer
recited
functionalized organic
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US20100108264A1 (en
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Gerardo A. Delgadino
Robert C. Hefty
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Lam Research Corp
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Lam Research Corp
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Priority to CN200910211371.3A priority patent/CN101726993B/zh
Priority to JP2009251663A priority patent/JP2010109373A/ja
Priority to KR1020090105136A priority patent/KR101611938B1/ko
Priority to TW098137246A priority patent/TWI493619B/zh
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004—Photosensitive materials
    • G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
    • G03F7/091—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers characterised by antireflection means or light filtering or absorbing means, e.g. anti-halation, contrast enhancement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H01L21/0276—Photolithographic processes using an anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics

Definitions

  • the present invention relates to etching an etch layer through a mask during the production of a semiconductor device. More specifically, the present invention relates to controlling critical dimension (CD) of etch features during the production of semiconductor devices.
  • CD critical dimension
  • features of the semiconductor device are defined by a patterned mask.
  • feature size is reduced. This may be achieved by reducing the CD of the features, which requires improved resolution, precision and accuracy.
  • a method for controlling CD of etch features in an etch layer disposed below a functionalized organic mask layer disposed below an intermediate mask layer, disposed below a patterned photoresist mask, which forms a stack is provided.
  • the intermediate mask layer is opened by selectively etching the intermediate mask layer with respect to the patterned photoresist mask.
  • the functionalized organic mask is opened.
  • the functionalized organic mask layer opening comprises flowing an open gas comprising COS, forming a plasma, and stopping the flowing of the open gas.
  • the etch layer is etched.
  • a method of controlling CD of etch features in a functionalized organic layer, which is below an intermediate mask layer, which is below a patterned photoresist mask is provided.
  • the intermediate mask layer is opened with respect to the patterned photoresist mask.
  • the functionalized organic layer is etched, comprising the steps of flowing an etching gas comprising COS, forming a plasma and stopping the flowing of the etching gas.
  • an apparatus for controlling CD of etch features in an etch layer disposed below a functionalized organic mask layer disposed below an intermediate mask layer, disposed below a patterned photoresist mask, which forms a stack comprising a chamber wall forming a plasma processing chamber enclosure, a substrate support for supporting a wafer within the plasma processing chamber enclosure, a pressure regulator for regulating the pressure in the plasma processing chamber enclosure, at least one electrode for providing power to the plasma processing chamber enclosure for sustaining a plasma, a gas inlet for providing gas into the plasma processing chamber enclosure, a gas outlet for exhausting gas from the plasma processing chamber enclosure.
  • a gas source is in fluid connection with the gas inlet and comprises an intermediate mask layer opening gas source, a COS gas source, and an etch layer etch gas source.
  • a controller is controllable connected to the gas source and the at least one electrode and comprises at least one processor and computer readable media.
  • the computer readable media comprises computer readable code for opening the intermediate mask layer, computer readable code for opening the functionalized organic mask layer, comprising computer readable code for flowing an open gas comprising COS flowed from the COS gas source, computer readable code for forming a plasma from the open gas mixture, and computer readable code for stopping the flow of the open gas into the processing chamber before the etch layer is completely etched.
  • the computer readable media further comprises computer readable code for etching the etch layer.
  • FIG. 1 is a high level flow chart of an embodiment of the invention.
  • FIG. 2 is a schematic view of a plasma processing chamber that may be used for etching.
  • FIGS. 3A-B illustrate a computer system, which is suitable for implementing a controller used in embodiments of the present invention.
  • FIGS. 4A-D are schematic views of a stack processed according to an embodiment of the invention.
  • FIG. 5 is a more detailed flow chart of a step of opening a functionalized organic layer with a COS additive.
  • FIG. 1 is a high level flow chart of a process used in an embodiment of the invention.
  • a substrate with an etch layer over which is a functionalized organic layer over which is an intermediate mask layer over which is a patterned photoresist mask is placed in an etch chamber (step 104 ).
  • the intermediate mask layer is opened (step 108 ).
  • the functionalized organic layer is opened using an opening gas with an additive of COS (carbonyl sulfide) (step 112 ).
  • Features are etched into the etch layer through the functionalized organic layer (step 116 ).
  • the substrate is then removed from the etch chamber (step 120 ).
  • FIG. 2 is a schematic view of an etch reactor that may be used in practicing the invention.
  • an etch reactor 200 comprises a top central electrode 206 , top outer electrode 204 , bottom central electrode 208 , and a bottom outer electrode 210 , within a chamber wall 250 .
  • a top insulator ring 207 insulates the top central electrode 206 from the top outer electrode 204 .
  • a bottom insulator ring 212 insulates the bottom central electrode 208 from the bottom outer electrode 210 .
  • a substrate 280 is positioned on top of the bottom central electrode 208 .
  • the bottom central electrode 208 incorporates a suitable substrate chucking mechanism (e.g., electrostatic, mechanical clamping, or the like) for holding the substrate 280 .
  • a gas source 224 is connected to the etch reactor 200 and supplies the etch gas into a plasma region 240 of the etch reactor 200 during the etch processes.
  • the gas source 224 comprises an opening gas source 262 , an intermediate mask layer opening gas source 264 , an etch gas source 266 , and a COS source 268 , which provide the gases used for controlling the CD features, in one example.
  • the CD controlling process may be used to shrink CD.
  • a bias RF source 248 , a first excitation RF source 252 , and a second excitation RF source 256 are electrically connected to the etch reactor 200 through a controller 235 to provide power to the electrodes 204 , 206 , 208 , and 210 .
  • the bias RF source 248 generates bias RF power and supplies the bias RF power to the etch reactor 200 .
  • the bias RF power has a frequency between 1 kilo Hertz (kHz) and 10 mega Hertz (MHz). More preferably, the bias RF power has a frequency between 1 MHz and 5 MHz. Even more preferably, the bias RF power has a frequency of about 2 MHz.
  • the first excitation RF source 252 generates source RF power and supplies the source RF power to the etch reactor 200 .
  • this source RF power has a frequency that is greater than the bias RF power. More preferably, this source RF power has a frequency that is between 10 MHz and 40 MHz. Most preferably, this source RF power has a frequency of 27 MHz.
  • the second excitation RF source 256 generates another source RF power and supplies the source RF power to the etch reactor 200 , in addition to the RF power generated by the first excitation RF source 252 .
  • this source RF power has a frequency that is greater than the bias RF source and the first RF excitation source. More preferably, the second excitation RF source has a frequency that is greater than or equal to 40 MHz. Most preferably, this source RF power has a frequency of 60 MHz.
  • the different RF signals may be supplied to various combinations of the top and bottom electrodes.
  • the lowest frequency of the RF should be applied through the bottom electrode on which the material being etched is placed, which in this example is the bottom central electrode 208 .
  • the controller 235 is connected to the gas source 224 , the bias RF source 248 , the first excitation RF source 252 , and the second excitation RF source 256 .
  • the controller 235 controls the flow of the etch gas into the etch reactor 200 , as well as the generation of the RF power from the three RF sources 248 , 252 , 256 , the electrodes 204 , 206 , 208 , and 210 , and the exhaust pump 220 .
  • confinement rings 202 are provided to provide confinement of the plasma and gas, which pass between the confinement rings and are exhausted by the exhaust pump.
  • FIGS. 3A and 3B illustrate a computer system, which is suitable for implementing the controller 235 used in one or more embodiments of the present invention.
  • FIG. 3A shows one possible physical form of the computer system 300 .
  • the computer system may have many physical forms ranging from an integrated circuit, a printed circuit board, and a small handheld device up to a huge super computer.
  • Computer system 300 includes a monitor 302 , a display 304 , a housing 306 , a disk drive 308 , a keyboard 310 , and a mouse 312 .
  • Disk 314 is a computer-readable medium used to transfer data to and from computer system 300 .
  • FIG. 3B is an example of a block diagram for computer system 300 . Attached to system bus 320 is a wide variety of subsystems.
  • Processor(s) 322 also referred to as central processing units, or CPUs
  • Memory 324 includes random access memory (RAM) and read-only memory (ROM).
  • RAM random access memory
  • ROM read-only memory
  • RAM random access memory
  • ROM read-only memory
  • RAM random access memory
  • ROM read-only memory
  • a fixed disk 326 is also coupled bi-directionally to CPU 322 ; it provides additional data storage capacity and may also include any of the computer-readable media described below.
  • Fixed disk 326 may be used to store programs, data, and the like and is typically a secondary storage medium (such as a hard disk) that is slower than primary storage. It will be appreciated that the information retained within fixed disk 326 may, in appropriate cases, be incorporated in standard fashion as virtual memory in memory 324 .
  • Removable disk 314 may take the form of any of the computer-readable media described below.
  • CPU 322 is also coupled to a variety of input/output devices, such as display 304 , keyboard 310 , mouse 312 , and speakers 330 .
  • an input/output device may be any of: video displays, track balls, mice, keyboards, microphones, touch-sensitive displays, transducer card readers, magnetic or paper tape readers, tablets, styluses, voice or handwriting recognizers, biometrics readers, or other computers.
  • CPU 322 optionally may be coupled to another computer or telecommunications network using network interface 340 . With such a network interface, it is contemplated that the CPU might receive information from the network, or might output information to the network in the course of performing the above-described method steps.
  • method embodiments of the present invention may execute solely upon CPU 322 or may execute over a network such as the Internet in conjunction with a remote CPU that shares a portion of the processing.
  • embodiments of the present invention further relate to computer storage products with a computer-readable medium that have computer code thereon for performing various computer-implemented operations.
  • the media and computer code may be those specially designed and constructed for the purposes of the present invention, or they may be of the kind well known and available to those having skill in the computer software arts.
  • Examples of tangible computer-readable media include, but are not limited to: magnetic media such as hard disks, floppy disks, and magnetic tape; optical media such as CD-ROMs and holographic devices; magneto-optical media such as floptical disks; and hardware devices that are specially configured to store and execute program code, such as application-specific integrated circuits (ASICs), programmable logic devices (PLDs) and ROM and RAM devices.
  • ASICs application-specific integrated circuits
  • PLDs programmable logic devices
  • Computer code examples include machine code, such as produced by a compiler, and files containing higher level of code that are executed by a computer using an interpreter.
  • Computer readable media may also be computer code transmitted by a computer data signal embodied in a carrier wave and representing a sequence of instructions that are executable by a processor.
  • FIG. 4A is a schematic cross-sectional illustration of a stack 400 , with a substrate 404 , over which an etch layer 408 is provided, over which a functionalized organic layer 412 is provided, over which an intermediate mask layer 416 is provided, over which a patterned photoresist mask 420 is provided.
  • the substrate 404 is a silicon wafer and the etch layer 408 is a dielectric layer, such as a doped or undoped silicon oxide.
  • the functionalized organic layer 412 is a polymer, which does not include amorphous carbon.
  • the intermediate mask layer 416 is a silicon containing organic anti-reflective coating (SiARC).
  • the substrate 404 , etch layer 408 , functionalized organic layer 412 , intermediate mask layer 416 , and patterned photoresist mask 420 are placed in the etch reactor 200 (step 104 ).
  • the intermediate mask layer 416 is selectively opened through the patterned photoresist mask 420 to pattern the intermediate mask layer 416 , with respect to the patterned photoresist mask as shown in FIG. 4B (step 108 ).
  • a typical recipe to etch or open an intermediate mask layer provides an opening gas comprising 100 sccm CF 4 , 75 sccm CHF 3 , 6 sccm O 2 at a pressure of 100 mTorr into the chamber. 800 watts at 60 MHz RF is provided to form the opening gas into a plasma.
  • the intermediate mask layer is opened, the flow of the opening gas is stopped.
  • a fluorocarbon gas is used in the opening gas for the intermediate mask layer.
  • FIG. 5 is a more detailed flow chart of the step of opening the functionalized organic layer using a COS additive.
  • An opening gas with a COS additive is flowed into the etch chamber (step 504 ).
  • an opening gas comprising 400 sccm N 2 , 400 sccm H 2 , 20 sccm COS at a pressure of 40 mTorr is provided to the chamber.
  • a gas of 100 sccm N 2 , 20 sccm O 2 , and 20 sccm COS is provided at a pressure of 20 mTorr.
  • the ratio of the flow of the COS to the total flow of the opening gas is 1:41 and 1:7, respectively.
  • the ratio of the flow of the COS to the total flow of the opening gas is between 1:2 and 1:160. More preferable, the ratio of the flow of the COS to the total flow of the opening gas is 1:3 to 1:80. Most preferably, the ratio of the flow of the COS to the total flow of the opening gas is 1:5 to 1:50.
  • the opening gas would have an O 2 or a CO 2 or a NH 3 or a N 2 or a CO, and H 2 component used to open an organic material.
  • the opening gas is formed into a plasma (step 508 ). 600 watts at 60 MHz RF is provided to form the COS containing gas into a plasma.
  • the plasma is a steady state plasma without gas modulation.
  • the COS forms organic sidewalls on sidewalls of the features.
  • the plasma is used to selectively open the functionalized organic layer with respect to the intermediate mask layer.
  • FIG. 4C is a schematic cross sectional view of the stack 400 after the opening process has opened features into the functionalized organic layer 412 . Once the features are opened in the functionalized organic layer 412 , the flow of the opening gas with COS additive is stopped (step 512 ). Most likely, during this step, the patterned photoresist (PR) layer gets completely removed.
  • PR photoresist
  • the substrate chucking mechanism may be maintained at any temperature.
  • the substrate chucking mechanism temperature is maintained at greater than 5° C. More preferably, the substrate chucking mechanism temperature is maintained at greater than 20° C. Most preferably, the substrate chucking mechanism temperature is maintained at greater than 60° C.
  • embodiments of the invention may work at lower substrate temperatures, it is believed that other processes do not work at such high temperatures.
  • etch layer through the opened functionalized organic layer (step 116 ).
  • the recipe used depends on the type of material that has to be etched. For TEOS, BPSG, low-k dielectric, FSG, SiN, etc. different process recipes may be required.
  • the functionalized organic layer opening gas is halogen free. Whether halogen is used depends on the material of the functionalized organic layer. A halogen free opening gas is able to open a functionalized organic layer containing no silicon. In another example, where the functionalized organic layer has a silicon component, the opening gas has a halogen component. The halogen composition has to be properly adjusted in order to have enough selectivity to the intermediate mask layer ( 416 ).
  • FIG. 4D is a schematic cross-sectional view of the stack after the features have been etched into the etch layer 408 .
  • the intermediate mask layer 416 may be the same material or may have similar etch properties as the etch layer 408 . Because the functionalized organic layer 412 has different etch properties than the etch layer 408 , the etch layer 408 is selectively etched with respect to the functionalized organic layer 412 .
  • the etch layer may be un-doped or doped silicon dioxide based material (e.g. TEOS, BPSG, FSG etc), organo-silicate glass (OSG), porous OSG, silicon nitride based material, silicon oxynitride based material, silicon carbide based material, low- ⁇ dielectric or any metal gate or metal mask material.
  • silicon dioxide based material e.g. TEOS, BPSG, FSG etc
  • organo-silicate glass (OSG) organo-silicate glass
  • porous OSG silicon nitride based material, silicon oxynitride based material, silicon carbide based material, low- ⁇ dielectric or any metal gate or metal mask material.
  • the intermediate mask layer is a silicon containing organic anti-reflective coating (SiARC).
  • SiARC organic anti-reflective coating
  • the intermediate mask layer and the etch layer have similar etch properties.
  • the functionalized organic layer may be selectively etched with respect to the intermediate mask layer and the etch layer may be selectively etched with respect to the functionalized organic layer. More preferably, selectivity between the intermediate layer and the functionalized organic layer is larger than 4. Most preferably, selectivity between the intermediate layer and the functionalized organic layer is larger than 6. Because the functionalized organic layer is soft having similar etch properties as photoresist, it is difficult to obtain a high etch selectivity with respect to the intermediate mask layer and maintain CD.
  • COS in an embodiment of the invention provides such a high selectivity, while either maintaining or shrinking CD.
  • the functionalized organic layer and patterned photoresist mask have the same etch properties. More preferably, the functionalized organic layer is made of a photoresist material without photo-sensitive material.
  • Embodiments of the invention may be used to etch various features such as lines, trenches, and contacts.
  • the invention provides an etching process where the etch features are contacts.
  • the etch layer is at least one of a silicon dioxide based material, organo-silicate glass, a silicon nitride based material, a silicon oxynitride based material, silicon carbide based material, silicon or poly-silicon material, titanium nitride, titanium, tantalum nitride, tungsten, polymer, oxide, an inorganic or organic based low- ⁇ material (such as SiLK®TM, manufactured by The Dow Chemical Company), or any metal gate or metal mask material.
  • the functionalized organic layer is the etch layer, over which an intermediate mask layer patterned is provided, over which a patterned photoresist mask 420 is provided.
  • the functionalized organic layer is etched through the intermediate mask layer, where the functionalized organic layer is not used as a mask for etching another layer.
  • the COS additive provides a coating or changes the surface of the functionalized organic mask layer that provides subsequent etch protection.

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  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
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  • Drying Of Semiconductors (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
US12/263,662 2008-11-03 2008-11-03 Bi-layer, tri-layer mask CD control Active 2032-01-11 US8394722B2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
US12/263,662 US8394722B2 (en) 2008-11-03 2008-11-03 Bi-layer, tri-layer mask CD control
CN200910211371.3A CN101726993B (zh) 2008-11-03 2009-10-29 双层、三层掩模cd控制
JP2009251663A JP2010109373A (ja) 2008-11-03 2009-11-02 二重層マスク、三重層マスクのｃｄ制御
KR1020090105136A KR101611938B1 (ko) 2008-11-03 2009-11-02 에칭 피쳐의 cd를 제어하는 방법
TW098137246A TWI493619B (zh) 2008-11-03 2009-11-03 雙層、三層遮罩臨界尺寸控制

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US12/263,662 US8394722B2 (en) 2008-11-03 2008-11-03 Bi-layer, tri-layer mask CD control

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US20100108264A1 US20100108264A1 (en) 2010-05-06
US8394722B2 true US8394722B2 (en) 2013-03-12

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JP (1) JP2010109373A (ko)
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US10440777B2 (en) 2015-05-22 2019-10-08 Applied Materials, Inc. Azimuthally tunable multi-zone electrostatic chuck

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US8394722B2 (en) * 2008-11-03 2013-03-12 Lam Research Corporation Bi-layer, tri-layer mask CD control
US8329585B2 (en) * 2009-11-17 2012-12-11 Lam Research Corporation Method for reducing line width roughness with plasma pre-etch treatment on photoresist
JP5606060B2 (ja) * 2009-12-24 2014-10-15 東京エレクトロン株式会社 エッチング方法及びエッチング処理装置
JP5674375B2 (ja) * 2010-08-03 2015-02-25 東京エレクトロン株式会社 プラズマ処理方法及びプラズマ処理装置
US8053323B1 (en) * 2010-11-03 2011-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. Patterning methodology for uniformity control
US8598040B2 (en) * 2011-09-06 2013-12-03 Lam Research Corporation ETCH process for 3D flash structures
CN102543687B (zh) * 2011-11-30 2015-08-05 中微半导体设备(上海)有限公司 掩膜层的刻蚀方法、刻蚀装置及层间介质层的刻蚀方法
CN103227109B (zh) * 2012-01-31 2015-11-25 中微半导体设备(上海)有限公司 一种有机物层刻蚀方法
JP2013222852A (ja) * 2012-04-17 2013-10-28 Tokyo Electron Ltd 有機膜をエッチングする方法及びプラズマエッチング装置
JP6008771B2 (ja) * 2013-01-21 2016-10-19 東京エレクトロン株式会社 多層膜をエッチングする方法
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US20100108264A1 (en) 2010-05-06

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