US8064739B2 - Three-dimensional die stacks with inter-device and intra-device optical interconnect - Google Patents

Three-dimensional die stacks with inter-device and intra-device optical interconnect Download PDF

Info

Publication number
US8064739B2
US8064739B2 US11/977,350 US97735007A US8064739B2 US 8064739 B2 US8064739 B2 US 8064739B2 US 97735007 A US97735007 A US 97735007A US 8064739 B2 US8064739 B2 US 8064739B2
Authority
US
United States
Prior art keywords
die
optical
electrical
processor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active, expires
Application number
US11/977,350
Other languages
English (en)
Other versions
US20090103855A1 (en
Inventor
Nathan Binkert
Norm Jouppi
Al Davis
Raymond Beausoleil
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hewlett Packard Enterprise Development LP
Original Assignee
Hewlett Packard Development Co LP
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Development Co LP filed Critical Hewlett Packard Development Co LP
Priority to US11/977,350 priority Critical patent/US8064739B2/en
Assigned to HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. reassignment HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: DAVIS, AL, JOUPPI, NORM, BINKERT, NATHAN, BEAUSOLEIL, RAYMOND
Priority to DE112008002822.2T priority patent/DE112008002822B4/de
Priority to PCT/US2008/012116 priority patent/WO2009055029A2/en
Priority to KR1020107008980A priority patent/KR101513324B1/ko
Priority to CN2008801128382A priority patent/CN101836290B/zh
Priority to JP2010531046A priority patent/JP5154652B2/ja
Publication of US20090103855A1 publication Critical patent/US20090103855A1/en
Publication of US8064739B2 publication Critical patent/US8064739B2/en
Application granted granted Critical
Assigned to HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP reassignment HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Active legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/43—Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Definitions

  • the present application relates generally to processors and memory for computer systems.
  • On chip wires may be classified based on their length: (i) local wires which are short and connect the transistors within a single execution unit, such as an adder; (ii) medium length wires which connect adjacent subsystems, such as register files and an execution unit; and (iii) global wires which connect distant subsystems, such as a cache controller and a register file.
  • the problems with global wires are exacerbated by the fact that the quality of the injected signal degrades with wire length. This degradation is due to capacitively-coupled noise issues. In essence, as a wire gets longer it becomes a better antenna.
  • the capacitively-coupled noise issues may be fixed by shielding, but the shielding in turn impacts performance due to a reduction in cross-section bandwidth since the shield wires take up area on the device that could be used for signals which would increase bandwidth.
  • Off chip wires are also problematic in terms of power, signal integrity, energy per bit output bandwidth, and in terms of die area that needs to be allocated for pads.
  • the computer system package includes an electrical die and an optical die coupled to and stacked with the electrical die.
  • the electrical die includes circuitry to process and communicate electrical signals, and the optical die includes structures to transport optical signals.
  • the electrical die has a smaller area than the optical die so that the optical die includes an exposed mezzanine which is configured with optical input/output ports.
  • the packaging can be configured to provide structural support against insertion forces for external optical connections.
  • FIG. 1 is a cross-sectional view of a computer system device packaged in a 3D die stack including an optical die in accordance with an embodiment of the invention.
  • FIG. 2 is a schematic diagram of a multiple-cluster computer system in accordance with an embodiment of the invention.
  • FIG. 3 shows an exploded isometric view of four die layers of the computer system device, shown in FIG. 1 in accordance with an embodiment of the invention.
  • FIG. 4A provides an example processor die layout showing circuitry associated with a single cluster in accordance with an embodiment of the invention.
  • FIG. 4B shows a tile of a memory controller die in accordance with an embodiment of the invention.
  • FIG. 5 is a schematic diagram of circuitry for a single computing cluster in accordance with an embodiment of the invention.
  • FIG. 6 shows an enlarged, exploded isometric view of the four die layers of the computation device, shown in FIG. 1 , in accordance with an embodiment of the invention.
  • FIG. 7 is a top view of an optical die which shows a two-sided optical mezzanine in accordance with an embodiment of the invention.
  • FIG. 8 is a cross-sectional view of a computer system device packaged in a 3D die stack including an optical die in accordance with another embodiment of the present invention.
  • the present application discloses embodiments of a three-dimensional die stack architecture and packaging techniques.
  • the embodiments disclosed herein may be used to advantageously replace wire-based electronic signaling for the global interconnect with an optical interconnect.
  • optical signaling does not suffer from the above-discussed problems with electrical signaling. This is because the energy required to send a bit of information with optics is not dependent on the length of the photonic waveguide for the distances of interest. Furthermore, the energy per bit using optical interconnect scales with VLSI technology and is orders of magnitude less than using an electrical interconnect. This, therefore, substantially mitigates the thermal problem. In addition, optical signaling does not suffer from a length-dependent coupled noise problem and hence the signal integrity problem is not an issue for optical signals.
  • silicon based lasers are of extremely poor quality.
  • Some embodiments disclosed herein allow a multiplicity of externally supplied lasers (or attached lasers) capable of supplying sufficient optical power so as to provide adequate signaling power for on and off die-stack needs.
  • Through-die vias typically require the wafers to be thinned such that fiber attachment insertion forces do not reliably maintain the physical integrity of the die structure.
  • One or more embodiments disclosed herein allow optical fibers to be attached with mechanical integrity to the die stack to support off chip communication.
  • One embodiment of the present invention relates to a packaging method which incorporates a photonic die in a three-dimensional (3D) die stack with an exposed mezzanine.
  • the exposed mezzanine allows either attached or external laser power injection and also exposes optical input/output (I/O) ports for external communication to other devices in the system.
  • the die-stack employs through-die vias. Long-distance inter-die communication and intra-die communication may be carried on optical waveguides placed in an optical die that is configured in the 3D die stack.
  • Each attached or external laser may be configured to inject light into the optical die at a different frequency. Providing laser light at multiple frequencies enables wavelength division multiplexed communication within a single waveguide. This increases the effective bandwidth per cross sectional area.
  • the optical I/O connections may be used to connect neighboring packages through optical fibers or to adjacent packages via fibers or free space waveguides.
  • Optical fibers may be configured to connect to external optical bonding pads located on the optical mezzanine.
  • the attached or external lasers may be configured to inject laser power into the photonic die via a separate interface located on the optical mezzanine.
  • Optical fibers may be configured to go to the side of the package or directly to neighboring packages.
  • FIG. 1 is a cross-sectional view of a computer system device packaged in a 3D die stack employing a photonic interconnect on an optical die in the stack in accordance with an embodiment of the invention.
  • the computer system device 100 comprises a processor die 102 , a memory controller/directory/L2 die (“memory-controller die”) 104 , an optional analog electronic die 106 , an optical die 108 , and four exemplar stacked memory dies 110 - 113 stacked in a package 120 .
  • the stacked memory dies 110 - 113 can be volatile memory, such as dynamic random access memory (“DRAM”), non-volatile memory, or any combination of volatile and non-volatile memory.
  • DRAM dynamic random access memory
  • non-volatile memory or any combination of volatile and non-volatile memory.
  • the stacked memory dies 110 - 113 can be 8 gigabyte (“GB”) DRAM.
  • the computer system device 100 also includes a heat sink 118 positioned on the package 120 near the processor die 102 , and a number of vias, represented by four through vias 115 , that extend from the memory-controller die 104 through the analog electronic die 106 and the optical die 108 to the four memory dies 110 - 113 .
  • the dies 102 , 104 , 106 , 108 , and 110 - 113 can range in thickness from approximately 25 to approximately 50 microns.
  • the heat sink 118 dissipates heat produced by computational operation of the processor die 102
  • the through vias 115 can be metalized or silicon filled vias that electrically interconnect memory controllers in the memory die to each of the four memory dies 110 - 113 .
  • the memory controllers located within the memory-controller die 104 manage the flow of data going to and from the memory dies 110 - 113 and the flow of data going to and from external devices (not shown).
  • the optical die 108 is larger that the other dies resulting in an exposed mezzanine 128 which can include external photonic input/output connections 124 , 126 that can be used to couple light from an external light source such as a laser 126 or transmit data encoded optical signals through a waveguide such as an optical fiber 124 to and from the computer system device 100 .
  • a diamond layer 130 may also be included between the bottom surface of the optical die 108 and the top surface of the memory die 110 - 113 .
  • the diamond layer 130 can be approximately 1-10 ⁇ m thick and can be used to spread out and dissipate heat produced by the processor die 102 and the memory-controller die 104 .
  • the three-dimensional die stacking shown in FIG. 1 permits tight coupling of the optical die 108 with the electronic dies, provides accessibility of the memory dies 110 - 113 at low latency, and, by spreading cluster logic and memory over stacked adjacent dies 102 , and 104 , the electrical intra-cluster wiring is shortened over conventional devices.
  • stacking the memory dies in close proximity to the memory controllers and using vias running through the memory layers provides shorter-length, lower-resistance interconnections than the considerably longer, higher-resistance interconnections used to connect conventional memory to memory controllers.
  • the power, or load, needed to transmit electrical signals between dies of the computer system device 100 is significantly lower than the power needed for conventional memory to memory controllers.
  • the hottest die (the die generating the most heat during operation) may be stacked in a manner that it is the closest die nearest to a heat sink 118 or other cooling apparatus.
  • the hottest die in a stack is typically the processor (processor/L1) die 102 . While configurations with a processor die 102 attached very near or adjacent a heat sink 118 are illustrated, other configurations are also possible.
  • other cooling apparatus may be used. For example, a fan may be provided to actively blow air over the heat sink, or a thermoelectric cooler may be utilized.
  • a non-processor die may be configured to be adjacent to the cooling apparatus, or more than one cooling apparatus may be provided.
  • a memory controller (memory controller/directory/L2) die 104 is configured beneath the processor die 102 by face-to-face bonding 105 .
  • this example illustrates an optional analog electronics die 106 which is configured beneath the memory controller die 104 by back-to-back bonding.
  • the optical die 108 is configured beneath the analog electronics dies 106 by face-to-face bonding 105 .
  • a silicon-germanium waveguide structure may be fabricated on the optical die 108 .
  • the optical die 108 is intentionally fabricated to be larger than the analog electronics die 106 in either the horizontal and/or depth dimension in this figure. This size difference exposes optical mezzanine area or areas 128 (see FIG. 7 , for an example top view).
  • the optical mezzanine areas are exposed planar areas 128 which may contain connection points for attached or external light sources such as non-silicon laser(s) and for the optical I/O (input/output) pads.
  • lasers 126 are directly attached to the mezzanine area 128 of the optical (photonic) die 108 .
  • one or more optical waveguides 124 connected to one or more lasers external to the die stack may be attached to input laser ports on the optical mezzanine area(s).
  • one or more optical fibers 124 for input/output are attached to the optical I/O pads on the mezzanine area(s).
  • the lasers may be fabricated, for example, from a direct bandgap material, such as Indium-Phosphide (InP).
  • the laser light may be split into multiple (for example, ten) wavelengths using a power divider.
  • the wavelengths may be, for example, in the range of 1400 to 1500 nanometers (nm), and the modulation may be at approximately 10 gigahertz. In another implementation, one wavelength may be used and modulated at 100 gigahertz. Other specific implementations may use different wavelengths and modulation frequencies.
  • the external optical waveguides 124 and/or attached lasers 126 are preferably mechanically attached so as to maintain proper alignment.
  • Mechanical strain relief features may be provided for the attached optical fibers.
  • the mechanical strain relief features may be, for example, configured as part of the package 120 and/or near the point of interconnection to the optical die 108 .
  • holographic lenses fabricated on top of the optical die 108 may provide a fiber to optical die interface.
  • a robust structural foundation is provided in order to withstand the mechanical attachment insertion forces without breaking the thin and therefore fragile dies in the stack (particularly, the fragile optical die 108 , but also the other stacked dies).
  • This may be accomplished, for example, by supporting the optical die 108 with an equal (as shown in FIG. 1 ) or larger base die or dies.
  • the illustrated embodiment shows memory dies 110 - 113 as base dies which are configured beneath the optical die 108 by face-to-back bonding 111 .
  • Such memory dies 110 - 113 may be optional, depending on the implementation.
  • one or more additional optical dies may be stacked as base die(s) under the optical die 108 .
  • the base die(s) is (are) in turn supported by a much stronger mechanical package 120 .
  • a solid foundation backed by a rigid and robust package 120 which can withstand the mechanical insertion forces required to attach optical connectors such as optical fibers ( 124 ).
  • the package 120 may comprise a ball grid array 132 package.
  • FIG. 2 is a schematic diagram of a multiple-cluster computer system in accordance with an embodiment of the invention.
  • Multiple computing clusters 202 are shown which are interconnected with an photonic interconnect 204 .
  • Each cluster 202 may also be connected to optically-connected memory 206 .
  • the functionalities for the system components shown within the dashed line in FIG. 2 may be provided by the die stack shown in FIG. 1 .
  • the functionalities for the clusters 202 may be provided by the Processor/L1 die 104 and the Memory Controller/Directory/L2 die 106 .
  • the functionalities for the photonic interconnect 204 may be provided by the optical die 110 .
  • the optically-connected memories (OCMs) 206 may be external memory devices which are optically-connected to the stack by the fiber I/O's 124 shown in FIG. 1 .
  • Each cluster of the processor die 102 has a corresponding memory controller disposed on the memory controller die 104 , each memory controller interfaces to the stacked memory dies 110 - 113 or drives a photonic connection to off-chip memory to provide bandwidth that scales with the processor die 102 performance.
  • the clusters are also photonically coupled to the optical die 108 , offering high bandwidth, modest latency, and very low power consumption.
  • a programmer with the stacked computational device 100 at his/her disposal can express parallelism at a high level, and is not burdened by issues of locality, which greatly reduces the difficulty of parallel program development.
  • the computational device 100 architecture may provide bandwidth of one byte per flop to DRAM.
  • the on-stack memory provides 32 Gbytes of DRAM which is directly connected to the memory controllers through the multiple vias running through the DRAM, such as vias 120 - 123 .
  • the DRAM is provided by 4 memory stack layers, thinned to about 25 to 50 microns to minimize loading of, or the amount of power needed to use, the vias.
  • Each layer of the DRAM stack includes 64 nearly identical regions which map onto the clusters in the processor die 102 above. Each DRAM region can be further subdivided into multiple banks that reduce the row access time, and allows multiple concurrent accesses.
  • each region may provide 1 Gbit of error correcting code protected storage, so that each memory controller in the memory-controller die 104 electronically connects to 0.5 Gbytes of memory.
  • Multiple logical channels provide increased bandwidth into the memory. By providing increased bandwidth, bank conflicts in the DRAM are reduced.
  • Each memory channel consists of 72 data bits and approximately 30 address and control bits.
  • the area overhead of the through vias may be less the 3% of the memory layer, assuming 4 channels per memory controller.
  • Fine pitch through vias allow the DRAM to be structured to supply an entire cache line from a single row access. Additionally, the through-vias can be pitch matched with one or more elements in a layer of the stack.
  • Some examples of such elements can be bit lines, sense amps and input/output buffers in a memory layer.
  • OCM optically connected memory modules
  • the optical die 108 performs two functions. First, the optical die 108 provides an interface to the optical fiber connections, such as external photonic interconnects 124 and 126 . Second, the optical die 108 provides low power, global interconnect for the stack of DRAM. The OCMs and the processor are connected through optical fibers 124 , which provides for as much as 48 logical channels that can be used for commands or other application-specific data exchanges.
  • FIG. 3 shows an exploded isometric view of the processor die 102 , the memory-controller die 104 , the analog electronic die 106 , and the optical die 108 in accordance with embodiments of the present invention.
  • the processor die 102 and the memory-controller die 104 are partitioned into 64 tiles.
  • each tile in the processor die 102 represents four cores called “clusters,” and each tile in the memory-controller die 104 represents an L2 cache, a hub, a memory controller, and other devices that are in electronic communication with a corresponding cluster located approximately directly above in the processor die 102 .
  • tile 302 of memory-controller die 104 represents an L2 cache, a hub, a memory controller and other devices located beneath and in electronic communication with an associated cluster 304 .
  • the clusters and tiles can be approximately 3 mm by 3 mm, but can be made larger or smaller depending on the implementation. Embodiments of the present invention are not limited to clusters having four cores. In other embodiments, a cluster can be comprised of two, three, and four or more cores. An example of a cluster and tile are described below with reference to FIGS. 4A-4B .
  • the optical die 108 includes 16 approximately regularly spaced optoelectronic converters, such as optoelectronic converter 306 , approximately parallel (non-crossing) waveguides having a serpentine configuration, represented by strip 308 , that wind their way through each of the 16 regularly spaced optoelectronic converters, and 16 bundles of 8 approximately parallel waveguides, each bundle emanating from a corresponding optoelectronic converter, such as bundle 310 emanating from the optoelectronic converter 306 .
  • 16 approximately regularly spaced optoelectronic converters such as optoelectronic converter 306
  • approximately parallel (non-crossing) waveguides having a serpentine configuration, represented by strip 308 that wind their way through each of the 16 regularly spaced optoelectronic converters
  • 16 bundles of 8 approximately parallel waveguides each bundle emanating from a corresponding optoelectronic converter, such as bundle 310 emanating from the optoelectronic converter 306 .
  • the serpentine waveguides are called “on-chip waveguides” that provide photonic communication between optoelectronic converters, and the waveguides comprising the 16 bundles of waveguides are called “off-chip waveguides” that provide photonic communication via external photonic connections such as optical fiber 124 with devices located outside the computational device 100 .
  • the 16 optoelectronic converters are each comprised of four optoelectronic converter blocks (see FIG. 6 ). Each of the optoelectronic converter blocks (“converter blocks”) is in electronic communication with one of the four associated tiles in the memory-controller die 104 .
  • FIG. 3 also reveals two, substantially identical, channel sources 702 and 704 positioned at opposite ends of the serpentine on-chip waveguides 308 .
  • the sources 702 and 704 are each configured to output the same set of different channels onto each of the on-chip waveguides in opposite directions.
  • a directional arrow represents the direction channels output from the source 702 are transmitted, and a directional arrow represents the direction channels output from the source 704 are transmitted.
  • the serpentine on-chip waveguides 308 have a width of approximately 1900 microns.
  • These light sources can be on-chip or can be external light sources 126 .
  • External light sources can be made of different materials than silicon such as III-V materials which are more suitable for lasers.
  • the communication of optical signals within the devices in the die stack may be considered as intra-device communications, and that the communication of optical signals with devices external to the die stack may be considered as inter-device communications.
  • the waveguide structure of FIG. 3 provides both inter-device and intra-device optical interconnect.
  • the analog electronic die 106 includes 16 patches, each patch is located between four tiles in the memory-controller die 104 and an optoelectronic converter in the optical die 108 .
  • Each patch comprises a number of metalized or silicon filled through vias that provide for analog electronic communication between the four tiles in the memory-controller die 104 and the corresponding optoelectronic converters.
  • Data is transmitted through the patches in the form of electronic analog signals (“electrical signals”) because producing analog signals typically consumes considerably less power than producing digital electrical signals.
  • electrical signals electronic analog signals
  • Such an analog layer can be used to convert digital signals from the memory controller to analog signals needed to control modulators or other devices on the optical layer, to convert analog outputs of photodetectors to digital signals to be input to the memory controller, or for other uses.
  • the following description is an overview of how an example of a photonic interconnect on an optical die 108 can take advantage of external photonic connections supported by the mezzanine 128 for transmitting data between clusters and external devices.
  • Data generated by a bluster of the processor die 102 , such as cluster 304 , or extracted from a tile of the memory-controller die 104 , such as tile 302 is transmitted as data encoded electrical signals through vias in a patch 312 to a corresponding converter block (not shown) of the optoelectronic converter 306 .
  • the converter block encodes the electrical signals into one or more wavelengths of electromagnetic radiation, called “channels,” propagating in one or more of the on-chip waveguides 308 . Encoding data into unmodulated channels can be accomplished by modulating the intensity of the channels. Channels carrying data are referred to as “encoded channels.”
  • the encoded channels can be destined for (1) a neighboring cluster 314 , which is also in electronic communication with the same optoelectronic converter 306 , (2) a cluster located elsewhere in the processor die 102 such as cluster 315 , or (3) an external device (not shown).
  • a neighboring cluster 314 which is also in electronic communication with the same optoelectronic converter 306
  • its corresponding converter block located within the optoelectronic converter 306 receives the encoded channels and converts them back into encoded electrical signals that are transmitted back through the patch 312 to the cluster 314 .
  • the encoded channels are transmitted along appropriate on-chip waveguides to a converter block corresponding to the cluster 315 located with an optoelectronic converter 316 .
  • the encoded channels are converted back into encoded electrical signals that are transmitted through a patch 318 to the cluster 315 .
  • the converter block of the optoelectronic converter 306 places the encoded channels onto off-chip waveguides of the bundle 310 where the encoded channels exit the optical die 108 through an external photonic connector such as optical fiber 124 .
  • an external device When an external device generates encoded channels destined for one of the four clusters 314 , the encoded channels can be received via optical fiber 124 and be transmitted along the off-chip waveguides in the bundle 310 to the optoelectronic converter 306 where the encoded channels are converted into encoded electrical signals that are transmitted through the patch 312 to the four clusters 314 for processing.
  • FIG. 4A shows a cluster 402 of the processor die 102 in accordance with embodiments of the present invention.
  • the cluster 402 comprises four cores. Each core is in electrical communication with an L1 instruction cache and an L1 data cache.
  • An L1 instruction cache and an L1 data cache are high speed random access memory that temporarily store frequently or recently accessed instructions and data.
  • FIG. 4B shows a tile 404 of the memory-controller die 104 in accordance with embodiments of the present invention.
  • the tile 404 includes an L2 cache and a component region 406 comprising a hub, a memory controller, directory, network interface, a my crossbar connection, and a peer crossbar connection. These crossbar connections may be configured to interface with corresponding portions of the optoelectronic converters.
  • the L2 cache is shared by the four cores of the cluster 402 .
  • An L1-L2 interface 408 is positioned in approximately the center of the cluster 402 and the tile 404 and provides electronic communication between the cluster 402 and the tile 404 .
  • FIG. 5 is a schematic diagram of circuitry for a single computing cluster in accordance with an embodiment of the present invention.
  • multiple processor cores 1 - 4 are shown, each of which includes an associated level 1 (L1) cache.
  • L1 caches can be provided on processor/L1 die 102 .
  • a shared level 2 (L2) cache 504 interconnects with each of the cores 1 - 4 .
  • the L2 cache 504 interfaces with a hub interconnect 506 .
  • the hub interconnect 506 further interfaces with various components, such as a directory module 508 , a memory controller 510 , a network interface 514 , and the photonic interconnect 204 .
  • the directory module 508 may be configured to provide cache coherency, for example, by tracking a global state of memory on a per cache line basis.
  • the memory controller 510 may transfer data to and from main memory (e.g. DRAM).
  • the DRAM may be on-stack DRAM 110 - 113 shown in FIG.
  • the network interface 514 may provide data input/output to components outside of the stack, for example by way of the fiber input/output to components outside of the stack, for example by way of the fiber input/outputs 124 .
  • FIG. 6 shows an enlarged, exploded isometric view of four clusters 602 of the processor die 102 , four corresponding tiles 604 of the memory-controller die 104 , a patch 606 of the analog electronic die 106 , and an optoelectronic converter 608 of the optical die 108 arranged in accordance with embodiments of the present invention.
  • the optoelectronic converter 608 comprises four individual optoelectronic converter blocks 610 - 613 . Each converter block is in electronic communication with one of the four tiles 604 via the patch 606 .
  • tile 615 is in electronic communication with the converter block 610
  • tile 616 is in electronic communication with the converter block 611
  • tile 617 is in electronic communication with the converter block 612
  • tile 618 is in electronic communication with the converter block 613 .
  • the converter blocks 610 - 613 convert encoded electrical signals output from the tiles 615 - 618 , respectively, into encoded channels that can be transmitted on a portion of the on-chip waveguides 308 for processing by other clusters or transmitted on a bundle of waveguides 620 to external devices for processing.
  • the converter blocks 610 - 613 also convert encoded channels transmitted in the bundle 620 and the on-chip waveguides 308 into encoded electrical signals that can be processed separately by the four clusters 602 .
  • FIG. 7 is a top view of an optical die which shows a two-sided optical mezzanine in accordance with an embodiment of the invention.
  • a center portion 710 of a front side of the optical die 108 is face-to-face bonded with the analog electronics die 106 .
  • the exposed mezzanine regions or areas 128 may be on either side of the center portion 710 , as in FIG. 1 . In a different embodiment, the exposed mezzanine regions or areas may be on all four sides of the center portion.
  • lasers 126 external to the optical die 108 may be attached to either or both mezzanine areas 128 .
  • optical fibers connected to lasers external to the die stack may be attached to input laser ports on the optical mezzanine 128 .
  • Optical fibers 124 for input/output may be coupled to the external optical I/O bonds 708 on the optical die 108 .
  • FIG. 8 is a cross-sectional view of a computer system device packaged in a 3D die stack 800 including an optical die in accordance with another embodiment of the present invention.
  • This 3D die stack embodiment bonds the optical die 108 to the processor die in an arrangement where the optical mezzanine 128 is exposed on the bottom side of the optical die.
  • the optical die 108 shares about the same area as the processor die 102 in this example and overhangs a memory die L3 Cache Die 804 and the memory controller die 104 .
  • Through vias 115 extend from the memory controller die 104 through the L3 Cache Die 804 .
  • the external input output bond 802 and the optical fiber 124 are supported by sidewall 810 which has an opening for the fiber 124 to pass through.
  • An additional mechanical strain relief 806 can also be included to assist the sidewall in supporting the optical die 108 and above layers from underneath.
  • the external laser 126 is supported by sidewall 808 .
  • the die material that is optimal for memory and processor/logic fabrication is very different from the material properties that are optimal to generate optical lasing.
  • silicon-based structures are used for memory and logic structures while integrated lasers are generally best fabricated using III-V materials, such as Indium Phosphide or Gallium Arsenide. These III-V materials may be used to make memory and logic structures that are very fast.
  • the thermal properties of these III-V materials typically preclude their use in high performance complex computer systems.
  • the long wire interconnects do not scale well when compared to the transistors.
  • the long wires present an obstacle in terms of signal integrity. This is because their capacitance requires too much current to charge quickly and so results in heat that cannot be economically removed.
  • Long wires are also a barrier to high-speed operation. Fundamentally, the capacitance of a wire is a function of area and resistance is a function of the wire's width to length aspect ratio. The result is that the per bit transport energy and the propagation delay of the wire increase with wire length.
  • Optical communication is relatively independent of path length for the scales of interest.
  • optical interconnect reduces the power needed and the heat generated, as well as improving the performance of computer systems when compared with systems which support long distance communication electrically.
  • Signal integrity in electrical interconnects also degrades with length.
  • Photonic interconnects do not suffer from this length dependent problem.

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Optical Couplings Of Light Guides (AREA)
  • Structure Of Printed Boards (AREA)
  • Optical Integrated Circuits (AREA)
US11/977,350 2007-10-23 2007-10-23 Three-dimensional die stacks with inter-device and intra-device optical interconnect Active 2029-10-20 US8064739B2 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
US11/977,350 US8064739B2 (en) 2007-10-23 2007-10-23 Three-dimensional die stacks with inter-device and intra-device optical interconnect
CN2008801128382A CN101836290B (zh) 2007-10-23 2008-10-23 具有设备间和设备内光学互连的三维管芯叠层
PCT/US2008/012116 WO2009055029A2 (en) 2007-10-23 2008-10-23 Three-dimensional die stacks with inter-device and intra-device optical interconnect
KR1020107008980A KR101513324B1 (ko) 2007-10-23 2008-10-23 3차원 다이 스택을 포함하는 장치 및 반도체 다이의 3차원 스택을 갖는 장치
DE112008002822.2T DE112008002822B4 (de) 2007-10-23 2008-10-23 Dreidimensionale Chipstapel mit einer optischen Verbindung, die zwischen Vorrichtungen und innerhalb einer Vorrichtung vorliegt
JP2010531046A JP5154652B2 (ja) 2007-10-23 2008-10-23 デバイス間およびデバイス内の光相互接続を有する三次元ダイスタック

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/977,350 US8064739B2 (en) 2007-10-23 2007-10-23 Three-dimensional die stacks with inter-device and intra-device optical interconnect

Publications (2)

Publication Number Publication Date
US20090103855A1 US20090103855A1 (en) 2009-04-23
US8064739B2 true US8064739B2 (en) 2011-11-22

Family

ID=40563571

Family Applications (1)

Application Number Title Priority Date Filing Date
US11/977,350 Active 2029-10-20 US8064739B2 (en) 2007-10-23 2007-10-23 Three-dimensional die stacks with inter-device and intra-device optical interconnect

Country Status (6)

Country Link
US (1) US8064739B2 (ko)
JP (1) JP5154652B2 (ko)
KR (1) KR101513324B1 (ko)
CN (1) CN101836290B (ko)
DE (1) DE112008002822B4 (ko)
WO (1) WO2009055029A2 (ko)

Cited By (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100195363A1 (en) * 2009-01-30 2010-08-05 Unity Semiconductor Corporation Multiple layers of memory implemented as different memory technology
US20100242605A1 (en) * 2009-03-27 2010-09-30 Klaus Offterdinger Sensor component
US20120051695A1 (en) * 2010-08-25 2012-03-01 Oracle International Corporation Optical communication in a ramp-stack chip package
US20130243429A1 (en) * 2012-03-15 2013-09-19 Massachusetts Institute Of Technology Photonically-enabled in-flight data reorganization
US20140122802A1 (en) * 2012-10-31 2014-05-01 Oracle International Corporation Accessing an off-chip cache via silicon photonic waveguides
US20140268980A1 (en) * 2013-03-14 2014-09-18 Jeong-Kyoum Kim Memory chip package, memory system having the same and driving method thereof
US20150155876A1 (en) * 2012-08-06 2015-06-04 Advanced Micro Devices, Inc. Die-stacked memory device with reconfigurable logic
US9082632B2 (en) 2012-05-10 2015-07-14 Oracle International Corporation Ramp-stack chip package with variable chip spacing
US9094135B2 (en) 2013-06-10 2015-07-28 Freescale Semiconductor, Inc. Die stack with optical TSVs
US9091820B2 (en) 2013-06-10 2015-07-28 Freescale Semiconductor, Inc. Communication system die stack
US9142746B2 (en) 2013-11-11 2015-09-22 Avago Technologies General Ip (Singapore) Pte. Ltd. Light-emitting diodes on a wafer-level package
US9177884B2 (en) 2012-10-09 2015-11-03 Avago Technologies General Ip (Singapore) Pte. Ltd. Two-sided-access extended wafer-level ball grid array (eWLB) package, assembly and method
US9261556B2 (en) 2013-06-10 2016-02-16 Freescale Semiconductor, Inc. Optical wafer and die probe testing
US9286948B2 (en) 2013-07-15 2016-03-15 Advanced Micro Devices, Inc. Query operations for stacked-die memory device
US9305908B2 (en) 2014-03-14 2016-04-05 Avago Technologies General Ip (Singapore) Pte. Ltd. Methods for performing extended wafer-level packaging (eWLP) and eWLP devices made by the methods
US20160124164A1 (en) * 2014-10-29 2016-05-05 Acacia Communications, Inc. Optoelectronic ball grid array package with fiber
US9435952B2 (en) 2013-06-10 2016-09-06 Freescale Semiconductor, Inc. Integration of a MEMS beam with optical waveguide and deflection in two dimensions
US9443835B2 (en) 2014-03-14 2016-09-13 Avago Technologies General Ip (Singapore) Pte. Ltd. Methods for performing embedded wafer-level packaging (eWLP) and eWLP devices, packages and assemblies made by the methods
US9442254B2 (en) 2013-06-10 2016-09-13 Freescale Semiconductor, Inc. Method and apparatus for beam control with optical MEMS beam waveguide
US9495295B1 (en) * 2015-04-23 2016-11-15 PhotonIC International Pte. Ltd. Photonics-optimized processor system
US9541717B2 (en) 2015-01-30 2017-01-10 Avago Technologies General IP (Singapore) Pta. Ltd. Optoelectronic assembly incorporating an optical fiber alignment structure
US9541503B2 (en) 2014-03-14 2017-01-10 Avago Technologies General Ip (Singapore) Pte. Ltd. Compact systems, compact devices, and methods for sensing luminescent activity
US9697147B2 (en) 2012-08-06 2017-07-04 Advanced Micro Devices, Inc. Stacked memory device with metadata management
US9766409B2 (en) 2013-06-10 2017-09-19 Nxp Usa, Inc. Optical redundancy
US9810843B2 (en) 2013-06-10 2017-11-07 Nxp Usa, Inc. Optical backplane mirror
US9825843B2 (en) 2012-12-23 2017-11-21 Advanced Micro Devices, Inc. Die-stacked device with partitioned multi-hop network
US9874688B2 (en) 2012-04-26 2018-01-23 Acacia Communications, Inc. Co-packaging photonic integrated circuits and application specific integrated circuits
US10230458B2 (en) 2013-06-10 2019-03-12 Nxp Usa, Inc. Optical die test interface with separate voltages for adjacent electrodes
US10255070B2 (en) 2013-09-06 2019-04-09 Massachusetts Institute Of Technology ISA extensions for synchronous coalesced accesses
US10600770B2 (en) 2018-05-14 2020-03-24 Micron Technology, Inc. Semiconductor dice assemblies, packages and systems, and methods of operation
US10734354B2 (en) 2017-12-27 2020-08-04 Sandisk Information Technology (Shanghai) Co., Ltd. Semiconductor device including optically connected wafer stack
US11079936B2 (en) 2016-03-01 2021-08-03 Samsung Electronics Co., Ltd. 3-D stacked memory with reconfigurable compute logic
US11652019B2 (en) * 2019-05-28 2023-05-16 Yazaki Corporation Heat dissipation structure
US11817903B2 (en) 2020-08-06 2023-11-14 Celestial Ai Inc. Coherent photonic computing architectures
US11835777B2 (en) 2022-03-18 2023-12-05 Celestial Ai Inc. Optical multi-die interconnect bridge (OMIB)
US12124095B2 (en) 2023-09-07 2024-10-22 Celestial Ai Inc. Optical multi-die interconnect bridge with optical interface

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8059443B2 (en) * 2007-10-23 2011-11-15 Hewlett-Packard Development Company, L.P. Three-dimensional memory module architectures
US8050256B1 (en) * 2008-07-08 2011-11-01 Tilera Corporation Configuring routing in mesh networks
US8151088B1 (en) 2008-07-08 2012-04-03 Tilera Corporation Configuring routing in mesh networks
US8045546B1 (en) 2008-07-08 2011-10-25 Tilera Corporation Configuring routing in mesh networks
US8831437B2 (en) 2009-09-04 2014-09-09 Luxtera, Inc. Method and system for a photonic interposer
US8877616B2 (en) 2008-09-08 2014-11-04 Luxtera, Inc. Method and system for monolithic integration of photonics and electronics in CMOS processes
US8281074B2 (en) 2008-10-07 2012-10-02 Micron Technology, Inc. Interface device for memory in a stack, storage devices and a processor
US8644030B2 (en) * 2009-01-14 2014-02-04 Micron Technology, Inc. Computer modules with small thicknesses and associated methods of manufacturing
JP2011029535A (ja) 2009-07-29 2011-02-10 Elpida Memory Inc 半導体装置
US9331096B2 (en) * 2009-09-04 2016-05-03 Luxtera, Inc. Method and system for hybrid integration of optical communication systems
WO2011139496A2 (en) * 2010-04-26 2011-11-10 Rambus Inc. Techniques for interconnecting stacked dies using connection sites
US8805132B2 (en) 2010-12-08 2014-08-12 International Business Machines Corporation Integrated circuit package connected to a data transmission medium
US8547769B2 (en) * 2011-03-31 2013-10-01 Intel Corporation Energy efficient power distribution for 3D integrated circuit stack
US10141314B2 (en) * 2011-05-04 2018-11-27 Micron Technology, Inc. Memories and methods to provide configuration information to controllers
US10355001B2 (en) 2012-02-15 2019-07-16 Micron Technology, Inc. Memories and methods to provide configuration information to controllers
CN102624446A (zh) * 2012-03-06 2012-08-01 华中科技大学 一种三维堆叠硅片层间红外通信结构
JP2014035546A (ja) * 2012-08-07 2014-02-24 Luxtera Inc 光通信システムのハイブリッド集積のための方法及びシステム
US9374162B2 (en) * 2012-12-19 2016-06-21 Intel Corporation Semiconductor package with optical port
CN104730653B (zh) * 2013-12-23 2016-08-31 华为技术有限公司 光互连系统和方法
US20150279431A1 (en) 2014-04-01 2015-10-01 Micron Technology, Inc. Stacked semiconductor die assemblies with partitioned logic and associated systems and methods
US9971089B2 (en) * 2015-12-09 2018-05-15 Intel Corporation Chip-to-chip interconnect with embedded electro-optical bridge structures
WO2017131638A1 (en) * 2016-01-26 2017-08-03 Hewlett Packard Enterprise Development Lp Semiconductor assembly
US10361140B2 (en) 2016-06-10 2019-07-23 International Business Machines Corporation Wafer stacking for integrated circuit manufacturing
WO2020036631A2 (en) * 2018-03-06 2020-02-20 The Regents Of The University Of California Network on interconnect fabric
CN113853753A (zh) 2019-03-06 2021-12-28 轻物质公司 光子通信平台
KR20220137062A (ko) 2020-02-03 2022-10-11 라이트매터, 인크. 광자 웨이퍼 통신 시스템들 및 관련 패키지들
US11960438B2 (en) * 2020-09-08 2024-04-16 Rambus Inc. Methods and circuits for streaming data to processing elements in stacked processor-plus-memory architecture
KR102671347B1 (ko) * 2021-03-17 2024-06-03 오프로세서 인코퍼레이티드 광학 모듈 패키지
US11953724B2 (en) 2021-10-13 2024-04-09 Lightmatter, Inc. Multi-tenant isolation on a multi-reticle photonic communication platform
US20240036278A1 (en) * 2022-07-29 2024-02-01 Google Llc 3D High Bandwidth Memory and Optical Connectivity Stacking
US20240078195A1 (en) * 2022-09-01 2024-03-07 Advanced Micro Devices, Inc. Systems, methods, and devices for advanced memory technology

Citations (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5652811A (en) 1996-03-06 1997-07-29 The United States Of America As Represented By The Secretary Of The Air Force Semiconductor on fiber optic substrate (SOFOS)
US20020039464A1 (en) * 1998-10-09 2002-04-04 Tetsuzo Yoshimura Optical reflective structures and method for making
US6477286B1 (en) 1999-07-16 2002-11-05 Canon Kabushiki Kaisha Integrated optoelectronic device, and integrated circuit device
US20030155656A1 (en) 2002-01-18 2003-08-21 Chiu Cindy Chia-Wen Anisotropically conductive film
US6636668B1 (en) 1999-11-23 2003-10-21 Lnl Technologies, Inc. Localized thermal tuning of ring resonators
US20050023656A1 (en) 2002-08-08 2005-02-03 Leedy Glenn J. Vertical system integration
US6885099B2 (en) 2002-10-24 2005-04-26 Sony Corporation Multichip module, manufacturing method thereof, multichip unit and manufacturing method thereof
US6934450B2 (en) 2002-12-10 2005-08-23 Mitsubishi Denki Kabushiki Kaisha Optical path-changing connector
WO2006046801A1 (en) 2004-10-29 2006-05-04 Samsung Electronics Co., Ltd. Multichip system and method of transferring data therein
US20060164882A1 (en) 2004-12-23 2006-07-27 Robert Norman Storage controller using vertical memory
US7138295B2 (en) 1997-04-04 2006-11-21 Elm Technology Corporation Method of information processing using three dimensional integrated circuits
US7177171B2 (en) 2004-02-26 2007-02-13 Renesas Technology Corp. Semiconductor device
US20070090507A1 (en) 2005-10-26 2007-04-26 Chian-Chi Lin Multi-chip package structure
US20080151950A1 (en) 2006-12-20 2008-06-26 Industrial Technology Research Institute Multiwavelength semiconductor laser array and method of fabricating the same
US7464225B2 (en) 2005-09-26 2008-12-09 Rambus Inc. Memory module including a plurality of integrated circuit memory devices and a plurality of buffer devices in a matrix topology
US20090103345A1 (en) 2007-10-23 2009-04-23 Mclaren Moray Three-dimensional memory module architectures
US7532785B1 (en) 2007-10-23 2009-05-12 Hewlett-Packard Development Company, L.P. Photonic interconnects for computer system devices

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5357122A (en) * 1991-09-05 1994-10-18 Sony Corporation Three-dimensional optical-electronic integrated circuit device with raised sections
JPH07249732A (ja) * 1994-03-10 1995-09-26 Fujitsu Ltd 半導体素子の接合方法
US6690845B1 (en) * 1998-10-09 2004-02-10 Fujitsu Limited Three-dimensional opto-electronic modules with electrical and optical interconnections and methods for making
JP2001156243A (ja) * 1999-11-30 2001-06-08 Seiko Epson Corp 基板および半導体装置
JP2002280517A (ja) * 2001-03-22 2002-09-27 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
JP3848210B2 (ja) * 2002-05-29 2006-11-22 キヤノン株式会社 電子回路基板
JP3897688B2 (ja) * 2002-12-11 2007-03-28 キヤノン株式会社 光電融合配線基板
JP4534096B2 (ja) * 2007-04-12 2010-09-01 ローム株式会社 半導体チップおよびその製造方法、ならびに半導体装置

Patent Citations (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5652811A (en) 1996-03-06 1997-07-29 The United States Of America As Represented By The Secretary Of The Air Force Semiconductor on fiber optic substrate (SOFOS)
US7138295B2 (en) 1997-04-04 2006-11-21 Elm Technology Corporation Method of information processing using three dimensional integrated circuits
US20020039464A1 (en) * 1998-10-09 2002-04-04 Tetsuzo Yoshimura Optical reflective structures and method for making
US6477286B1 (en) 1999-07-16 2002-11-05 Canon Kabushiki Kaisha Integrated optoelectronic device, and integrated circuit device
US6636668B1 (en) 1999-11-23 2003-10-21 Lnl Technologies, Inc. Localized thermal tuning of ring resonators
US20030155656A1 (en) 2002-01-18 2003-08-21 Chiu Cindy Chia-Wen Anisotropically conductive film
US20050023656A1 (en) 2002-08-08 2005-02-03 Leedy Glenn J. Vertical system integration
US6885099B2 (en) 2002-10-24 2005-04-26 Sony Corporation Multichip module, manufacturing method thereof, multichip unit and manufacturing method thereof
US6934450B2 (en) 2002-12-10 2005-08-23 Mitsubishi Denki Kabushiki Kaisha Optical path-changing connector
US7177171B2 (en) 2004-02-26 2007-02-13 Renesas Technology Corp. Semiconductor device
WO2006046801A1 (en) 2004-10-29 2006-05-04 Samsung Electronics Co., Ltd. Multichip system and method of transferring data therein
US20060164882A1 (en) 2004-12-23 2006-07-27 Robert Norman Storage controller using vertical memory
US7327600B2 (en) 2004-12-23 2008-02-05 Unity Semiconductor Corporation Storage controller for multiple configurations of vertical memory
US7464225B2 (en) 2005-09-26 2008-12-09 Rambus Inc. Memory module including a plurality of integrated circuit memory devices and a plurality of buffer devices in a matrix topology
US20070090507A1 (en) 2005-10-26 2007-04-26 Chian-Chi Lin Multi-chip package structure
US20080151950A1 (en) 2006-12-20 2008-06-26 Industrial Technology Research Institute Multiwavelength semiconductor laser array and method of fabricating the same
US20090103345A1 (en) 2007-10-23 2009-04-23 Mclaren Moray Three-dimensional memory module architectures
US7532785B1 (en) 2007-10-23 2009-05-12 Hewlett-Packard Development Company, L.P. Photonic interconnects for computer system devices

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
U.S. Appl. No. 11/975,963, Final Rejection dated Jan. 26, 2010, pp. 1-18 and attachments.
U.S. Appl. No. 11/975,963, Non-Final Rejection dated Jun. 25, 2009, pp. 1-14 and attachments.
U.S. Appl. No. 11/975,974, Non-Final Rejection dated Sep. 15, 2008, pp. 1-10 and attachments.
U.S. Appl. No. 11/975,974, Notice of Allowance dated Mar. 31, 2009, pp. 1-5 and attachments.

Cited By (51)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8456880B2 (en) * 2009-01-30 2013-06-04 Unity Semiconductor Corporation Multiple layers of memory implemented as different memory technology
US20100195363A1 (en) * 2009-01-30 2010-08-05 Unity Semiconductor Corporation Multiple layers of memory implemented as different memory technology
US20100242605A1 (en) * 2009-03-27 2010-09-30 Klaus Offterdinger Sensor component
US8584525B2 (en) * 2009-03-27 2013-11-19 Robert Bosch Gmbh Sensor component
US20120051695A1 (en) * 2010-08-25 2012-03-01 Oracle International Corporation Optical communication in a ramp-stack chip package
US8290319B2 (en) * 2010-08-25 2012-10-16 Oracle America, Inc. Optical communication in a ramp-stack chip package
US20130243429A1 (en) * 2012-03-15 2013-09-19 Massachusetts Institute Of Technology Photonically-enabled in-flight data reorganization
US8792786B2 (en) * 2012-03-15 2014-07-29 Massachusetts Institute Of Technology Photonically-enabled in-flight data reorganization
US9874688B2 (en) 2012-04-26 2018-01-23 Acacia Communications, Inc. Co-packaging photonic integrated circuits and application specific integrated circuits
US10578799B2 (en) 2012-04-26 2020-03-03 Acaia Communications Co-packaging photonic integrated circuits and application specific integrated circuits
US9082632B2 (en) 2012-05-10 2015-07-14 Oracle International Corporation Ramp-stack chip package with variable chip spacing
US20150155876A1 (en) * 2012-08-06 2015-06-04 Advanced Micro Devices, Inc. Die-stacked memory device with reconfigurable logic
US9344091B2 (en) * 2012-08-06 2016-05-17 Advanced Micro Devices, Inc. Die-stacked memory device with reconfigurable logic
US9697147B2 (en) 2012-08-06 2017-07-04 Advanced Micro Devices, Inc. Stacked memory device with metadata management
US9177884B2 (en) 2012-10-09 2015-11-03 Avago Technologies General Ip (Singapore) Pte. Ltd. Two-sided-access extended wafer-level ball grid array (eWLB) package, assembly and method
US20140122802A1 (en) * 2012-10-31 2014-05-01 Oracle International Corporation Accessing an off-chip cache via silicon photonic waveguides
US9390016B2 (en) * 2012-10-31 2016-07-12 Oracle International Corporation Accessing an off-chip cache via silicon photonic waveguides
US9825843B2 (en) 2012-12-23 2017-11-21 Advanced Micro Devices, Inc. Die-stacked device with partitioned multi-hop network
US20140268980A1 (en) * 2013-03-14 2014-09-18 Jeong-Kyoum Kim Memory chip package, memory system having the same and driving method thereof
US9449653B2 (en) * 2013-03-14 2016-09-20 Samsung Electronics Co., Ltd. Memory chip package having optically and electrically connected chips, memory system having the same and driving method thereof
US9442254B2 (en) 2013-06-10 2016-09-13 Freescale Semiconductor, Inc. Method and apparatus for beam control with optical MEMS beam waveguide
US9766409B2 (en) 2013-06-10 2017-09-19 Nxp Usa, Inc. Optical redundancy
US9094135B2 (en) 2013-06-10 2015-07-28 Freescale Semiconductor, Inc. Die stack with optical TSVs
US9435952B2 (en) 2013-06-10 2016-09-06 Freescale Semiconductor, Inc. Integration of a MEMS beam with optical waveguide and deflection in two dimensions
US10230458B2 (en) 2013-06-10 2019-03-12 Nxp Usa, Inc. Optical die test interface with separate voltages for adjacent electrodes
US9091820B2 (en) 2013-06-10 2015-07-28 Freescale Semiconductor, Inc. Communication system die stack
US9810843B2 (en) 2013-06-10 2017-11-07 Nxp Usa, Inc. Optical backplane mirror
US9261556B2 (en) 2013-06-10 2016-02-16 Freescale Semiconductor, Inc. Optical wafer and die probe testing
US9286948B2 (en) 2013-07-15 2016-03-15 Advanced Micro Devices, Inc. Query operations for stacked-die memory device
US10255070B2 (en) 2013-09-06 2019-04-09 Massachusetts Institute Of Technology ISA extensions for synchronous coalesced accesses
US9142746B2 (en) 2013-11-11 2015-09-22 Avago Technologies General Ip (Singapore) Pte. Ltd. Light-emitting diodes on a wafer-level package
US9305908B2 (en) 2014-03-14 2016-04-05 Avago Technologies General Ip (Singapore) Pte. Ltd. Methods for performing extended wafer-level packaging (eWLP) and eWLP devices made by the methods
US9541503B2 (en) 2014-03-14 2017-01-10 Avago Technologies General Ip (Singapore) Pte. Ltd. Compact systems, compact devices, and methods for sensing luminescent activity
US9443835B2 (en) 2014-03-14 2016-09-13 Avago Technologies General Ip (Singapore) Pte. Ltd. Methods for performing embedded wafer-level packaging (eWLP) and eWLP devices, packages and assemblies made by the methods
US9425175B2 (en) 2014-03-14 2016-08-23 Avago Technologies General Ip (Singapore) Pte. Ltd. Methods for performing extended wafer-level packaging (eWLP) and eWLP devices made by the methods
US20160124164A1 (en) * 2014-10-29 2016-05-05 Acacia Communications, Inc. Optoelectronic ball grid array package with fiber
US11892690B1 (en) 2014-10-29 2024-02-06 Acacia Communications, Inc. Optoelectronic ball grid array package with fiber
US11360278B2 (en) * 2014-10-29 2022-06-14 Acacia Communications, Inc. Optoelectronic ball grid array package with fiber
US9541717B2 (en) 2015-01-30 2017-01-10 Avago Technologies General IP (Singapore) Pta. Ltd. Optoelectronic assembly incorporating an optical fiber alignment structure
US9495295B1 (en) * 2015-04-23 2016-11-15 PhotonIC International Pte. Ltd. Photonics-optimized processor system
US11079936B2 (en) 2016-03-01 2021-08-03 Samsung Electronics Co., Ltd. 3-D stacked memory with reconfigurable compute logic
US11789610B2 (en) 2016-03-01 2023-10-17 Samsung Electronics Co., Ltd. 3D-stacked memory with reconfigurable compute logic
US10734354B2 (en) 2017-12-27 2020-08-04 Sandisk Information Technology (Shanghai) Co., Ltd. Semiconductor device including optically connected wafer stack
US10600770B2 (en) 2018-05-14 2020-03-24 Micron Technology, Inc. Semiconductor dice assemblies, packages and systems, and methods of operation
US11380665B2 (en) 2018-05-14 2022-07-05 Micron Technology, Inc. Semiconductor dice assemblies, packages and systems, and methods of operation
US11652019B2 (en) * 2019-05-28 2023-05-16 Yazaki Corporation Heat dissipation structure
US11817903B2 (en) 2020-08-06 2023-11-14 Celestial Ai Inc. Coherent photonic computing architectures
US11835777B2 (en) 2022-03-18 2023-12-05 Celestial Ai Inc. Optical multi-die interconnect bridge (OMIB)
US20240272392A1 (en) * 2022-03-18 2024-08-15 Celestial Ai Inc. Multicomponent photonically bridged assembly
US12124095B2 (en) 2023-09-07 2024-10-22 Celestial Ai Inc. Optical multi-die interconnect bridge with optical interface
US12130485B1 (en) 2024-03-20 2024-10-29 Celestial Ai Inc. Stacked-dies optically bridged multicomponent package

Also Published As

Publication number Publication date
DE112008002822T5 (de) 2011-02-17
KR20100087698A (ko) 2010-08-05
US20090103855A1 (en) 2009-04-23
CN101836290A (zh) 2010-09-15
WO2009055029A3 (en) 2009-07-09
KR101513324B1 (ko) 2015-04-17
JP2011501465A (ja) 2011-01-06
CN101836290B (zh) 2012-07-25
WO2009055029A2 (en) 2009-04-30
DE112008002822B4 (de) 2016-01-07
JP5154652B2 (ja) 2013-02-27

Similar Documents

Publication Publication Date Title
US8064739B2 (en) Three-dimensional die stacks with inter-device and intra-device optical interconnect
KR101520130B1 (ko) 광자 상호접속부
Arakawa et al. Silicon photonics for next generation system integration platform
KR101574358B1 (ko) 메모리 모듈
US11367711B2 (en) Optically interfaced stacked memories and related methods and systems
US8768123B2 (en) Three-dimensional macro-chip including optical interconnects
US7961990B2 (en) Multi-chip system including capacitively coupled and optical communication
US11728894B2 (en) Optically-enhanced multichip packaging
US6353264B1 (en) Pseudomonolithic wafer scale module
JP2023513224A (ja) モノリシックインパッケージ光ｉ／ｏによって可能になるリモートメモリアーキテクチャ
US7865084B2 (en) Multi-chip systems with optical bypass
US9939596B2 (en) Optical integrated circuit package
US8121446B2 (en) Macro-chip including a surface-normal device
CN114063229A (zh) 半导体装置
US20240241333A1 (en) Led interconnect with breakout for memory applications
US20240345344A1 (en) Optically interconnected high bandwidth memory architectures
Taira et al. Optical package design for silicon photonic chips
US20220197044A1 (en) Converting multiple light signals into and out of a single wavelength with multiple polarizations to increase optical bandwidth

Legal Events

Date Code Title Description
AS Assignment

Owner name: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P., TEXAS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BINKERT, NATHAN;JOUPPI, NORM;DAVIS, AL;AND OTHERS;REEL/FRAME:020601/0179;SIGNING DATES FROM 20080227 TO 20080303

Owner name: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P., TEXAS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BINKERT, NATHAN;JOUPPI, NORM;DAVIS, AL;AND OTHERS;SIGNING DATES FROM 20080227 TO 20080303;REEL/FRAME:020601/0179

STCF Information on status: patent grant

Free format text: PATENTED CASE

FPAY Fee payment

Year of fee payment: 4

AS Assignment

Owner name: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP, TEXAS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.;REEL/FRAME:037079/0001

Effective date: 20151027

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 8

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 12