US7808085B2 - Semiconductor device and mold for resin-molding semiconductor device - Google Patents
Semiconductor device and mold for resin-molding semiconductor device Download PDFInfo
- Publication number
- US7808085B2 US7808085B2 US11/599,258 US59925806A US7808085B2 US 7808085 B2 US7808085 B2 US 7808085B2 US 59925806 A US59925806 A US 59925806A US 7808085 B2 US7808085 B2 US 7808085B2
- Authority
- US
- United States
- Prior art keywords
- resin
- resin sheet
- semiconductor device
- die pad
- mold
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active, expires
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 84
- 238000000465 moulding Methods 0.000 title claims abstract description 46
- 229920005989 resin Polymers 0.000 claims abstract description 121
- 239000011347 resin Substances 0.000 claims abstract description 121
- 150000001875 compounds Chemical class 0.000 description 17
- 238000004519 manufacturing process Methods 0.000 description 17
- 238000000034 method Methods 0.000 description 14
- 229910052782 aluminium Inorganic materials 0.000 description 9
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 238000001721 transfer moulding Methods 0.000 description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 7
- 239000011888 foil Substances 0.000 description 7
- 229910052737 gold Inorganic materials 0.000 description 7
- 239000010931 gold Substances 0.000 description 7
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 238000009413 insulation Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000012530 fluid Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 239000000470 constituent Substances 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 238000003825 pressing Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 238000007373 indentation Methods 0.000 description 1
- 238000011417 postcuring Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
- H01L23/4334—Auxiliary members in encapsulations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
Definitions
- the present invention relates to a semiconductor device including a group of leads, an integrated circuit (IC) chip mounted on one of the leads, a power chip (semiconductor chip) mounted on a die pad, a resin sheet disposed on a bottom side of the die pad to provide insulation, and a resin casing made of a molded resin compound encapsulating all internal elements of the semiconductor device.
- the invention pertains also to a resin molding die (or mold) used for resin-molding internal elements of such a semiconductor device.
- a semiconductor device to which the invention is directed is manufactured by a process including bonding semiconductor dies, or chips, such as a power chip and an IC chip, to a leadframe, wire-bonding the power chip and the IC chip to the leadframe, resin-molding all these internal elements of the semiconductor device into a single package.
- Wire bonding establishes electrical connections between the power chip and the leadframe by using aluminum wires and between the IC chip and the leadframe by using gold wires. Since the semiconductor device incorporates the power chip which handles a large electric current and generates heat, the semiconductor package must provide high heat dissipation and insulation capabilities.
- this kind of semiconductor device is structured as described in Japanese Patent Application Publication No. 2005-123495, for example.
- the semiconductor device disclosed in this Publication is provided with a resin sheet having first and second surfaces disposed on a bottom side of a die pad, the resin sheet forming an insulating layer having at least a specific thickness to provide high insulation quality.
- Internal elements of the semiconductor device are resin-molded into a single package.
- the resin sheet is made of resin material whose thermal conductivity is higher than that of a resin molding compound used for encapsulation.
- the semiconductor device can provide high heat dissipation and insulation capabilities only if the resin sheet disposed on the back side of the die pad is held in tight adhesion thereto.
- a resin-molding process of the aforementioned Publication employs a transfer molding technique using a resin molding die (or mold) provided with squeeze pins for forcing the die pad against the resin sheet to hold the die pad in tight contact with the resin sheet during the molding process.
- the molding process performed by using the mold provided with the squeeze pins for forcing the die pad against the resin sheet has a problem that the provision of the squeeze pins results in an increase in size of a molding machine due to the need for pressing the squeeze pins against the die pad.
- a semiconductor device including a group of leads having at least one die pad, a power chip for handling a large electric current and a resin sheet disposed on a back side of the die pad, the semiconductor device providing a capability to efficiently dissipate heat generated by the power chip to the exterior of the semiconductor device. It is another object of the invention to provide a resin molding die (or mold) used for resin-molding internal elements of such a semiconductor device.
- a semiconductor device includes a semiconductor chip, a die pad on which the semiconductor chip is mounted, a dielectric resin sheet placed on one side of the die pad opposite the semiconductor chip, the resin sheet being firmly adhered to the die pad, and a resin casing made by molding operation in which the semiconductor chip, the die pad and the resin sheet are molded by a resin in such a manner that one surface of the resin sheet opposite the die pad is exposed to the exterior of the resin casing.
- the resin casing has a groove formed in one surface opposite the exposed surface of the resin sheet, the groove extending parallel to the resin sheet and perpendicular to a runner through which the resin was supplied in the molding operation.
- a mold for manufacturing a semiconductor device includes an upper mold section and a lower mold section together forming a cavity inside.
- the mold is used for performing molding operation in which a dielectric resin sheet is placed on an inside bottom surface of the lower mold section, a die pad is placed on an upper surface of the resin sheet with a semiconductor chip mounted on the die pad, and a resin is supplied into the cavity through a runner formed in the mold from one side thereof to mold internal elements of the semiconductor device including the resin sheet, the die pad and the semiconductor chip.
- the upper mold section has a ridge projecting into the cavity from an upper inside surface of the upper mold section, the ridge extending in a direction perpendicular to the runner.
- the semiconductor device and the mold for manufacturing the semiconductor device are structured such that the resin supplied into the cavity of the mold forces an entire area of the die pad against the underlying resin sheet in a molding process.
- This structure serves to provide excellent adhesion between the die pad and the resin sheet as well as high insulation for the die pad, allowing for an eventual cost reduction of the semiconductor device.
- FIG. 1 is a perspective view of a semiconductor device according to a first embodiment of the invention
- FIG. 2 is a cross-sectional view taken along lines II-II of FIG. 1 ;
- FIG. 3 is a bottom view of the semiconductor device of FIG. 1 ;
- FIGS. 4A-4G are cross-sectional side views showing steps for manufacturing the semiconductor device of FIG. 1 by using a resin molding die (or mold) of the first embodiment;
- FIGS. 5A and 5B are cross-sectional side views showing steps for manufacturing the semiconductor device of FIG. 1 by using the mold of the first embodiment
- FIG. 6 is a cross-sectional side view of a semiconductor device according to one varied form of the first embodiment.
- FIG. 7 is a plan view of a semiconductor device according to a second embodiment of the invention.
- FIG. 8 is a cross-sectional side view of a semiconductor device according to a third embodiment of the invention.
- FIG. 9 is a cross-sectional side view of a semiconductor device according to a fourth embodiment of the invention.
- FIG. 10 is a cross-sectional side view of a semiconductor device according to a fifth embodiment of the invention.
- FIG. 1 is a perspective view of a semiconductor device 100 according to a first embodiment of the invention
- FIG. 2 is a cross-sectional side view taken along lines II-II of FIG. 1
- FIG. 3 is a bottom view of the semiconductor device 100 of FIG. 1
- FIGS. 4A-4G , 5 A and 5 B are cross-sectional side views showing a process of manufacturing the semiconductor device 100 by using a resin molding die (or mold) 20 of the first embodiment
- FIG. 6 is a cross-sectional side view of a semiconductor device 100 according to one varied form of the first embodiment.
- the semiconductor device 100 has a resin-molded package structure in which a plurality of shaped metallic leads 1 stick out from both sides of a molded resin casing 2 which is preferably made of an epoxy resin.
- the semiconductor device 100 includes, in addition to the aforementioned shaped leads 1 , an IC chip 7 , such as a logic chip, and a pair of power chips 5 , such as insulated-gate bipolar transistors (IGBTs) or freewheeling (FW) diodes.
- IC chip 7 such as a logic chip
- power chips 5 such as insulated-gate bipolar transistors (IGBTs) or freewheeling (FW) diodes.
- IGBTs insulated-gate bipolar transistors
- FW freewheeling
- the power chips 5 and the IC chip 7 are connected to one another and to the leads 1 by bonding wires 6 , 8 which are made either of gold or aluminum, for example.
- the IC chip 7 serves as a control IC for controlling the working of the power chips 5 . While the semiconductor device 100 of this embodiment includes two power chips 5 and one IC chip 7 as illustrated in FIG. 2 , the semiconductor device 100 may include any numbers of power chips 5 and IC chips 7 depending on functions to be performed.
- the molded resin casing 2 contains a resin sheet 3 with a metal foil 4 attached to a bottom side of the resin sheet 3 . Extremities 1 c of the leads 1 arranged on both sides of the molded resin casing 2 are aligned parallel to an extending direction of a groove 10 formed in the molded resin casing 2 as shown in FIG. 1 .
- the extending direction of the groove 10 is perpendicular to an extending direction of a later-described runner 12 formed in the mold 20 for feeding a fluid molding compound (resin) in a transfer molding process.
- the resin sheet 3 is preferably made of an epoxy resin containing a filler which is one material selected from the group consisting of silicon dioxide (SiO 2 ), aluminum oxide (Al 2 O 3 ), aluminum nitride (AlN), silicon nitride (Si 3 N 4 ), boron nitride (BN) and any combination thereof.
- the resin sheet 3 has a higher thermal conductivity than the molded resin casing 2 . It is to be understood that the resin sheet 3 need not necessarily be backed with the metal foil 4 but may be embedded alone in the bottom of the molded resin casing 2 as shown in FIG. 6 .
- the leads 1 are fixedly embedded in the molded resin casing 2 in such a way that a bottom side of the die pad 1 a is in direct contact with an upper surface of the resin sheet 3 .
- the bottom side of the die pad 1 a is held in direct contact with the upper surface of the resin sheet 3 in this fashion with no part of the molded resin casing 2 sandwiched in between.
- This structure ensures easy conduction of heat from the die pad 1 a to the resin sheet 3 , thus providing an increased capability of the semiconductor device 100 to dissipate heat from the power chips 5 mounted on the die pad 1 a.
- FIGS. 4A-4G the manufacturing process of the semiconductor device 100 using the aforementioned mold 20 is discussed in a step-by-step fashion below.
- Step 1 Leadframe Preparation and Die Attach
- a leadframe made of a copper sheet, for example, patterned to form the aforementioned multiple leads 1 is prepared as shown in FIG. 4A .
- the IC chip 7 is attached to a die attach portion formed in one of the leads 1 and the power chips 5 are attached to the die pad 1 a formed in the leadframe by use of solder, silver paste or the like.
- the bonding wires 6 are not necessarily limited to aluminum wires but may be made of an alloy containing aluminum as a main constituent or other metallic materials.
- the IC chip 7 is connected to specific bonding sites of the leadframe using gold bonding wires 8 as shown in FIG. 4C .
- the bonding wires 8 may be made of an alloy containing gold as a main constituent or other metallic materials.
- the IC chip 7 While the IC chip 7 is connected to the power chips 5 via one or more leads 1 as illustrated in FIG. 4C , the IC chip 7 may be directly connected to one or both of the power chips 5 . Also, the IC chip 7 may be connected to the leadframe by using metal strips instead of the bonding wires 8 .
- the mold 20 used for resin molding is prepared as shown in FIG. 4D .
- the mold 20 is divided into an upper mold section 21 and a lower mold section 22 together forming a cavity 24 inside.
- the mold 20 has the aforementioned runner 12 formed between the upper and lower mold sections 21 , 22 for feeding the molding compound in fluid form into the cavity 24 from a side of the mold 20 (refer to FIG. 4F ).
- Step 5 Leadframe Placement
- the resin sheet 3 backed with the metal foil 4 is prepared and placed in position inside the mold 20 .
- the resin sheet 3 is placed such that a bottom side the metal foil 4 lies in contact with an inside bottom surface of the lower mold section 22 .
- the leadframe carrying the power chips 5 , the IC chip 7 , the bonding wires 6 , 8 and so on is placed in position inside the mold 20 in such a manner that the bottom side of the die pad 1 a lies in contact with the upper surface of the resin sheet 3 as illustrated in FIG. 4 E.
- this step may be so modified as to temporarily attach the leadframe carrying the chips 5 , 7 and the bonding wires 6 , 8 to the upper surface of the resin sheet 3 and then place the leadframe with the resin sheet 3 on the lower mold section 22 .
- the upper mold section 21 is placed on top of the lower mold section 22 and the two mold sections 21 , 22 are assembled together.
- care must be exercised not to damage the power chips 5 , the IC chip 7 or the bonding wires 6 , 8 especially by the ridge 23 of the upper mold section 21 .
- the molding compound e.g., epoxy resin
- preheated fluid form is forced into the cavity 24 of the mold 20 under pressure through the runner 12 formed therein by transfer molding.
- the molding compound introduced through the runner 12 initially flows in a generally horizontal arrow direction shown in FIG. 5A , progressively filling up the cavity 24 from areas nearer the runner 12 .
- the molding compound turns its path in a direction indicated by an oblique arrow shown below the ridge 23 in FIG. 5B .
- the molding compound flows obliquely downward beneath the vertical ridge 23 in this way.
- This flow of the molding compound applies downward pressure selectively to the die pad 1 a which forces the resin sheet 3 downward against the lower mold section 22 .
- This structure of the mold 20 serves to secure good adhesion between the die pad 1 a and the resin sheet 3 .
- the molding compound introduced through the runner 12 would flow only horizontally all the way through the cavity 24 , so that the aforementioned oblique flow of the compound selectively forcing the die pad 1 a downward against the resin sheet 3 would not be obtained. In this case, adhesion between the die pad 1 a and the resin sheet 3 may potentially become insufficient.
- the die pad 1 a is selectively forced downward against the resin sheet 3 in a reliable fashion. Therefore, even if a small gap is initially formed between the die pad 1 a and the resin sheet 3 due to dimensional tolerances when the leadframe carrying the chips 5 , 7 and the bonding wires 6 , 8 is placed on top of the resin sheet 3 backed with the metal foil 4 in the cavity 24 of the mold 20 , the structure of the embodiment would provide excellent adhesion between the die pad 1 a and the resin sheet 3 as a result of the molding operation.
- Step 7 Frame Cutting and Lead Trimming/Forming
- the semiconductor package with the untrimmed leadframe is removed from the mold 20 as shown in FIG. 4G and subjected to a postcuring process to allow the molding compound to completely harden. Finally, excess parts of the leadframe, such as side rails and tie bars, are cut away and the individual leads 1 are bent at far ends to form the shaped lead extremities 1 c , whereby the finished semiconductor device 100 shown in FIG. 1 is obtained.
- the semiconductor device 100 may be provided with any numbers of power chips 5 and IC chips 7 .
- materials used for producing the aluminum bonding wires 6 and the gold bonding wires 8 are not specifically limited.
- these bonding wires 6 , 8 may be made of an alloy containing aluminum or gold as a main constituent or metallic materials other than aluminum and gold, such as copper.
- FIG. 7 is a plan view of a semiconductor device 100 according to a second embodiment of the invention, in which elements identical or similar to those of the first embodiment are designated by the same reference numerals.
- a groove 10 formed in a molded resin casing 2 is located above the resin sheet 3 as seen in plan view at a position closer to the runner 12 than a centerline of a top surface of the molded resin casing 2 .
- a mold 20 including an upper mold section 21 and a lower mold section 22 used in manufacturing the semiconductor device 100 of the second embodiment differs from that of the first embodiment in the following point.
- the mold 20 for manufacturing the semiconductor device 100 of this embodiment is structured such that a ridge 23 of the upper mold section 21 for forming the groove 10 in the molded resin casing 2 is located to overlie the resin sheet 3 , which is placed on the inside bottom surface of the lower mold section 22 , at a position closer to the runner 12 than a centerline of the ceiling (upper inside surface) of the upper mold section 21 .
- the molding compound fed into the cavity 24 of the mold 20 in the transfer molding process effectively exerts a downward pressing force forcing the die pad 1 a against the resin sheet 3 , thus securing more reliable adhesion between the die pad 1 a and the resin sheet 3 .
- FIG. 8 is a cross-sectional side view of a semiconductor device 100 according to a third embodiment of the invention, in which elements identical or similar to those of the foregoing embodiments are designated by the same reference numerals.
- a groove 10 formed in a molded resin casing 2 has an upward widening inverted trapezoidal shape in side view, an upper end of the groove 10 having a larger width than a lower end thereof.
- a side wall of the groove 10 nearer the runner 12 through which the resin was supplied in the molding operation is preferably inclined by 15 degrees to 45 degrees with respect to a plane perpendicular to an extending direction of the leads 1 .
- a mold 20 including an upper mold section 21 and a lower mold section 22 used in manufacturing the semiconductor device 100 of the third embodiment differs from that of the first embodiment in the following point.
- the mold 20 for manufacturing the semiconductor device 100 of this embodiment is structured such that a ridge 23 of the upper mold section 21 for forming the groove 10 has a trapezoidal cross-sectional shape with a basal end (upper end) of the ridge 23 having a larger width than a far end (lower end) thereof.
- the molding compound fed into the cavity 24 of the mold 20 in the transfer molding process effectively exerts a downward pressing force over a wider area forcing the die pad 1 a against the resin sheet 3 , thus securing more reliable adhesion between the die pad 1 a and the resin sheet 3 .
- FIG. 9 is a cross-sectional side view of a semiconductor device 100 according to a fourth embodiment of the invention, in which elements identical or similar to those of the foregoing embodiments are designated by the same reference numerals.
- a groove 10 formed in a molded resin casing 2 has a U-shaped bottom in cross section.
- a mold 20 including an upper mold section 21 and a lower mold section 22 used in manufacturing the semiconductor device 100 of the fourth embodiment differs from that of the first embodiment in that a ridge 23 of the upper mold section 21 for forming the groove 10 has a U-shaped far end (lower end) in cross section.
- the above-described mold structure of the fourth embodiment is advantageous in that the U-shaped far end of the ridge 23 for forming the groove 10 reduces wear of the ridge 23 caused by the flow of the molding compound during the transfer molding process. This serves to prolong the useful life of mold components and reduce overall equipment cost for manufacturing the semiconductor device 100 .
- FIG. 10 is a cross-sectional side view of a semiconductor device 100 according to a fifth embodiment of the invention, in which elements identical or similar to those of the foregoing embodiments are designated by the same reference numerals.
- each pit 11 there is one or more indentations or pits 11 in a bottom of a groove 10 formed in a molded resin casing 2 , each pit 11 having a diameter smaller than the width of the groove 10 .
- Each pit 11 is a halfway buried remainder of a hole in which a squeeze pin used for forcing a die pad 1 a against a resin sheet 3 was inserted during the transfer molding process.
- a mold 20 including an upper mold section 21 and a lower mold section 22 used in manufacturing the semiconductor device 100 of the fifth embodiment differs from that of the first embodiment in that one or more squeeze pins extend downward from a ridge 23 of the upper mold section 21 for forming the groove 10 in the molded resin casing 2 . Having a diameter smaller than the width of a far end (lower end) of the ridge 23 , individual squeeze pins force the die pad 1 a against the resin sheet 3 when the molding compound is fed into a cavity 24 of the mold 20 .
- This structure of the fifth embodiment is advantageous in that the squeeze pins used in the transfer molding process secure more reliable adhesion between the die pad 1 a and the resin sheet 3 .
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Moulds For Moulding Plastics Or The Like (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005357171A JP4422094B2 (ja) | 2005-12-12 | 2005-12-12 | 半導体装置 |
JP2005-357171 | 2005-12-12 |
Publications (2)
Publication Number | Publication Date |
---|---|
US20070132112A1 US20070132112A1 (en) | 2007-06-14 |
US7808085B2 true US7808085B2 (en) | 2010-10-05 |
Family
ID=38138485
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/599,258 Active 2027-04-10 US7808085B2 (en) | 2005-12-12 | 2006-11-15 | Semiconductor device and mold for resin-molding semiconductor device |
Country Status (4)
Country | Link |
---|---|
US (1) | US7808085B2 (zh) |
JP (1) | JP4422094B2 (zh) |
KR (1) | KR100850147B1 (zh) |
CN (2) | CN1983574A (zh) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080164588A1 (en) * | 2007-01-05 | 2008-07-10 | Fairchild Korea Semiconductor, Ltd. | High power semiconductor package |
US20130043558A1 (en) * | 2009-12-15 | 2013-02-21 | Renesas Electronics Corporation | Semiconductor device and communication method |
US20130109115A1 (en) * | 2011-10-27 | 2013-05-02 | Kabushiki Kaisha Toshiba | Method and jig for manufacturing semiconductor device |
US9269647B2 (en) * | 2014-05-29 | 2016-02-23 | Samsung Electronics Co., Ltd. | Semiconductor package having heat dissipating member |
KR20160143802A (ko) * | 2014-05-12 | 2016-12-14 | 미쓰비시덴키 가부시키가이샤 | 전력용 반도체 장치 및 그 제조 방법 |
US20200031661A1 (en) * | 2018-07-24 | 2020-01-30 | Invensense, Inc. | Liquid proof pressure sensor |
Families Citing this family (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4827851B2 (ja) * | 2005-11-22 | 2011-11-30 | ソニー株式会社 | 半導体装置および半導体装置の製造方法 |
US7808088B2 (en) * | 2006-06-07 | 2010-10-05 | Texas Instruments Incorporated | Semiconductor device with improved high current performance |
DE112006004098B4 (de) * | 2006-11-06 | 2013-01-31 | Infineon Technologies Ag | Halbleiter-Baugruppe mit einer Lead-Frame-Anordnung mit mindestens zwei Halbleiterchips und Verfahren zu deren Herstellung |
US7875962B2 (en) * | 2007-10-15 | 2011-01-25 | Power Integrations, Inc. | Package for a power semiconductor device |
JP5272768B2 (ja) * | 2009-02-05 | 2013-08-28 | 三菱電機株式会社 | 電力用半導体装置とその製造方法 |
CN102668042B (zh) * | 2009-12-24 | 2015-06-24 | 株式会社村田制作所 | 电子元器件的制造方法 |
US8178961B2 (en) * | 2010-04-27 | 2012-05-15 | Advanced Semiconductor Engineering, Inc. | Semiconductor package structure and package process |
JP5876669B2 (ja) * | 2010-08-09 | 2016-03-02 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP2012119488A (ja) * | 2010-11-30 | 2012-06-21 | Sanken Electric Co Ltd | 半導体装置の製造方法及び半導体装置 |
JP5796956B2 (ja) * | 2010-12-24 | 2015-10-21 | セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー | 回路装置およびその製造方法 |
CN102683299B (zh) * | 2011-01-07 | 2015-01-07 | 新电元工业株式会社 | 树脂密封型半导体装置及树脂密封用模具 |
US8598694B2 (en) * | 2011-11-22 | 2013-12-03 | Infineon Technologies Ag | Chip-package having a cavity and a manufacturing method thereof |
JP2013239659A (ja) * | 2012-05-17 | 2013-11-28 | Sumitomo Electric Ind Ltd | 半導体デバイス |
ITTO20120854A1 (it) | 2012-09-28 | 2014-03-29 | Stmicroelectronics Malta Ltd | Contenitore a montaggio superficiale perfezionato per un dispositivo integrato a semiconduttori, relativo assemblaggio e procedimento di fabbricazione |
JP2015065339A (ja) * | 2013-09-25 | 2015-04-09 | 三菱電機株式会社 | 半導体装置 |
KR101983164B1 (ko) * | 2013-12-20 | 2019-08-28 | 삼성전기주식회사 | 전력 반도체 패키지 및 그 제조 방법 |
EP3087599A4 (en) * | 2013-12-23 | 2017-12-13 | Intel Corporation | Package on package architecture and method for making |
JP6183226B2 (ja) * | 2014-01-17 | 2017-08-23 | 三菱電機株式会社 | 電力用半導体装置の製造方法 |
WO2015173906A1 (ja) | 2014-05-14 | 2015-11-19 | 三菱電機株式会社 | 半導体装置の製造方法 |
DE112014007140B4 (de) | 2014-11-07 | 2024-05-02 | Mitsubishi Electric Corporation | Leistungshalbleiteranordnung und Verfahren zum Herstellen derselben |
US10262912B2 (en) * | 2015-04-15 | 2019-04-16 | Mitsubishi Electric Corporation | Semiconductor device |
JP2020053611A (ja) * | 2018-09-28 | 2020-04-02 | 三菱電機株式会社 | 半導体モジュール、および、半導体モジュールの製造方法 |
CN115039220B (zh) | 2020-01-30 | 2023-05-09 | 日立能源瑞士股份公司 | 具有可触及金属夹具的功率半导体模块 |
KR20210148743A (ko) * | 2020-06-01 | 2021-12-08 | 삼성전자주식회사 | 반도체 패키지 |
US20240145325A1 (en) * | 2022-10-31 | 2024-05-02 | Infineon Technologies Austria Ag | Semiconductor Package with Molded Heat Dissipation Plate |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08204064A (ja) | 1995-01-25 | 1996-08-09 | Hitachi Ltd | 半導体装置 |
US5834842A (en) * | 1996-01-17 | 1998-11-10 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device, semiconductor module, and radiating fin |
JP2002329815A (ja) | 2001-05-01 | 2002-11-15 | Sony Corp | 半導体装置と、その製造方法、及びその製造装置 |
US6734571B2 (en) * | 2001-01-23 | 2004-05-11 | Micron Technology, Inc. | Semiconductor assembly encapsulation mold |
JP2004146706A (ja) | 2002-10-28 | 2004-05-20 | Sony Corp | 半導体装置 |
US20050067719A1 (en) | 2003-09-30 | 2005-03-31 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method for producing the same |
US20050082690A1 (en) | 2003-10-20 | 2005-04-21 | Mitsubishi Denki Kabushiki Kaisha | Method for producing semiconductor device and semiconductor device |
JP2005150595A (ja) | 2003-11-19 | 2005-06-09 | Mitsubishi Electric Corp | 電力用半導体装置 |
-
2005
- 2005-12-12 JP JP2005357171A patent/JP4422094B2/ja active Active
-
2006
- 2006-11-15 US US11/599,258 patent/US7808085B2/en active Active
- 2006-11-30 KR KR1020060119782A patent/KR100850147B1/ko active IP Right Grant
- 2006-12-07 CN CNA2006101640903A patent/CN1983574A/zh active Pending
- 2006-12-07 CN CN2010102844393A patent/CN101980357B/zh active Active
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08204064A (ja) | 1995-01-25 | 1996-08-09 | Hitachi Ltd | 半導体装置 |
US5834842A (en) * | 1996-01-17 | 1998-11-10 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device, semiconductor module, and radiating fin |
US6734571B2 (en) * | 2001-01-23 | 2004-05-11 | Micron Technology, Inc. | Semiconductor assembly encapsulation mold |
JP2002329815A (ja) | 2001-05-01 | 2002-11-15 | Sony Corp | 半導体装置と、その製造方法、及びその製造装置 |
JP2004146706A (ja) | 2002-10-28 | 2004-05-20 | Sony Corp | 半導体装置 |
US20050067719A1 (en) | 2003-09-30 | 2005-03-31 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method for producing the same |
KR20050031877A (ko) | 2003-09-30 | 2005-04-06 | 미쓰비시덴키 가부시키가이샤 | 반도체 장치 및 그 제조 방법 |
US20050082690A1 (en) | 2003-10-20 | 2005-04-21 | Mitsubishi Denki Kabushiki Kaisha | Method for producing semiconductor device and semiconductor device |
JP2005150595A (ja) | 2003-11-19 | 2005-06-09 | Mitsubishi Electric Corp | 電力用半導体装置 |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080164588A1 (en) * | 2007-01-05 | 2008-07-10 | Fairchild Korea Semiconductor, Ltd. | High power semiconductor package |
US8350369B2 (en) * | 2007-01-05 | 2013-01-08 | Fairchild Korea Semiconductor, Ltd. | High power semiconductor package |
US20130043558A1 (en) * | 2009-12-15 | 2013-02-21 | Renesas Electronics Corporation | Semiconductor device and communication method |
US8810021B2 (en) * | 2009-12-15 | 2014-08-19 | Renesas Electronics Corporation | Semiconductor device including a recess formed above a semiconductor chip |
US20130109115A1 (en) * | 2011-10-27 | 2013-05-02 | Kabushiki Kaisha Toshiba | Method and jig for manufacturing semiconductor device |
KR20160143802A (ko) * | 2014-05-12 | 2016-12-14 | 미쓰비시덴키 가부시키가이샤 | 전력용 반도체 장치 및 그 제조 방법 |
US9716072B2 (en) * | 2014-05-12 | 2017-07-25 | Mitsubishi Electric Corporation | Power semiconductor device and method of manufacturing the same |
KR101915873B1 (ko) | 2014-05-12 | 2018-11-06 | 미쓰비시덴키 가부시키가이샤 | 전력용 반도체 장치 및 그 제조 방법 |
US9269647B2 (en) * | 2014-05-29 | 2016-02-23 | Samsung Electronics Co., Ltd. | Semiconductor package having heat dissipating member |
US20200031661A1 (en) * | 2018-07-24 | 2020-01-30 | Invensense, Inc. | Liquid proof pressure sensor |
Also Published As
Publication number | Publication date |
---|---|
CN101980357A (zh) | 2011-02-23 |
JP4422094B2 (ja) | 2010-02-24 |
CN101980357B (zh) | 2013-05-01 |
CN1983574A (zh) | 2007-06-20 |
JP2007165425A (ja) | 2007-06-28 |
KR20070062413A (ko) | 2007-06-15 |
US20070132112A1 (en) | 2007-06-14 |
KR100850147B1 (ko) | 2008-08-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7808085B2 (en) | Semiconductor device and mold for resin-molding semiconductor device | |
US7781262B2 (en) | Method for producing semiconductor device and semiconductor device | |
US7410834B2 (en) | Method of manufacturing a semiconductor device | |
US6492739B2 (en) | Semiconductor device having bumper portions integral with a heat sink | |
US6992385B2 (en) | Semiconductor device, a method of manufacturing the same and an electronic device | |
US20110244633A1 (en) | Package assembly for semiconductor devices | |
US7714455B2 (en) | Semiconductor packages and methods of fabricating the same | |
US20070138606A1 (en) | Semiconductor package | |
CN101118895A (zh) | 具有内置热沉的半导体器件 | |
JP2008153432A (ja) | 半導体装置およびその製造方法 | |
KR101561934B1 (ko) | 반도체 패키지 및 그의 제조방법 | |
CN108604578A (zh) | 电力用半导体装置及其制造方法 | |
US9553068B2 (en) | Integrated circuit (“IC”) assembly includes an IC die with a top metallization layer and a conductive epoxy layer applied to the top metallization layer | |
US7667306B1 (en) | Leadframe-based semiconductor package | |
US7402895B2 (en) | Semiconductor package structure and method of manufacture | |
US20040203194A1 (en) | Method of resin-sealing a semiconductor device, resin-sealed semiconductor device, and forming die for resin-sealing the semiconductor device | |
CN101819955B (zh) | 具有增强散热性的半导体封装结构 | |
US7951651B2 (en) | Dual flat non-leaded semiconductor package | |
JP2023077978A (ja) | 半導体装置及びその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: MITSUBISHI ELECTRIC CORPORATION, JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:OZAKI, HIROYUKI;KAWAFUJI, HISASHI;NAKAGAWA, SHINYA;AND OTHERS;SIGNING DATES FROM 20061019 TO 20061023;REEL/FRAME:018603/0524 Owner name: MITSUBISHI ELECTRIC CORPORATION, JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:OZAKI, HIROYUKI;KAWAFUJI, HISASHI;NAKAGAWA, SHINYA;AND OTHERS;REEL/FRAME:018603/0524;SIGNING DATES FROM 20061019 TO 20061023 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552) Year of fee payment: 8 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 12 |