US6867628B2 - Semiconductor memory delay circuit - Google Patents

Semiconductor memory delay circuit Download PDF

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Publication number
US6867628B2
US6867628B2 US10/405,357 US40535703A US6867628B2 US 6867628 B2 US6867628 B2 US 6867628B2 US 40535703 A US40535703 A US 40535703A US 6867628 B2 US6867628 B2 US 6867628B2
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input
circuit
level
voltage
capacitor
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Expired - Fee Related
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US10/405,357
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US20030193359A1 (en
Inventor
Ji-Ho Cho
Seung-Keun Lee
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Assigned to SAMSUNG ELECTRONICS CO., LTD. reassignment SAMSUNG ELECTRONICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHO, JI-HO, LEE, SEUNG-KEUN
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/08—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding
    • H03K5/082—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding with an adaptive threshold
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/153—Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant
    • H03K5/1534—Transition or edge detectors

Definitions

  • the present invention generally relates to semiconductor memories and, in particular, to semiconductor memories employing delay circuits.
  • Semiconductor memories may control internal circuits thereof by way of signals having various operation timings.
  • Delay circuits may be employed along signal propagation paths in order to establish such various signal operation timings.
  • high-frequency memories such as DRAMs, SRAMs, and flash memories, may utilize address transition detection (ATD) circuits to access memory core circuits, such as sense amplifiers and memory cells, in response to address transitions.
  • ATD address transition detection
  • FIG. 1 illustrates a conventional general flash memory.
  • the general flash memory may include an address buffer 110 , a wordline decoder 120 , a bitline decoder 130 , a memory cell block 140 , an ATD circuit 150 , a sense amplifier 160 , and an input/output buffer 170 .
  • the address buffer 110 is generally capable of transferring external address signals to the wordline and bitline decoders, 120 and 130 .
  • a data bit of a memory cell designated by the wordline and bitline decoder 120 and 130 may be driven into the input/output buffer 170 by way of the sense amplifier 160 .
  • the sense amplifier 160 is capable of determining a validity of data read out from the selected memory cell.
  • the sense amplifier 160 may also receive signals from the ATD circuit 150 , which includes a delay circuit 200 . These signals instruct the sense amplifier 160 to exhaust charges on a bitline that may remain after data is sensed. Moreover, the signals from the ATD circuit 150 and the delay circuit 200 may be used to activate the sense amplifier 160 .
  • Vdd power supply voltage
  • a higher Vdd often enhances operating speeds, while a lower Vdd often degrades operating speeds.
  • signals generated from the delay circuit 200 may have different timings as power supply voltage levels vary.
  • FIG. 2 illustrates the conventional delay circuit 200 .
  • the delay circuit 200 may include an inverter 201 , a resistor 202 , a capacitor 203 , an inverter 204 , and a NAND gate 205 .
  • An input signal at input IN may be applied to one input terminal of the NAND gate 205 through the inverters 201 and 24 , and the resistor 202 . As is illustrated, the input signal may also be applied to another input terminal of the NAND gate 205 .
  • FIG. 3 illustrates an operational timing diagram of the conventional delay circuit 200 of FIG. 2 .
  • Output signal fluctuations from an ATD circuit, along variations of a power supply voltage, may result in memory device malfunctions.
  • An exemplary embodiment of the present invention provides a delay circuit having a substantially stable output signal.
  • An exemplary embodiment of the present invention includes a circuit having an input for receiving an input signal, a delay chain connected to the input for delaying the input signal, and a circuit configuration connected to the delay chain downstream of the input, the circuit configuration for supplying a voltage to the delay chain in response to the input signal.
  • Another exemplary embodiment of the present invention provides an arrangement that includes a circuit arrangement having an input and an output, and a voltage source coupled to the circuit arrangement downstream of the input, the voltage source actuatable in response to a signal input at the input.
  • Yet another exemplary embodiment provides a method that includes biasing a transistor to charge a capacitor coupled to a source of the transistor, and discharging the capacitor through another transistor to supply a voltage to a delay circuit.
  • Another exemplary embodiment of the present invention provides a method that provides a circuit arrangement; and that substantially harmonizes transition points of signals input to the circuit arrangement regardless a voltage levels of the signals.
  • FIG. 1 illustrates a conventional general flash memory.
  • FIG. 2 illustrates a conventional delay circuit
  • FIG. 3 illustrates an operational timing diagram of the conventional delay circuit of FIG. 2 .
  • FIG. 4 illustrates a circuit diagram of a delay circuit according to an exemplary embodiment of the present invention.
  • FIG. 5 illustrates a timing diagram showing output characteristics of the delay circuit of FIG. 4 .
  • FIG. 6 illustrates a circuit diagram of a delay circuit according to another exemplary embodiment of the present invention.
  • FIG. 7 illustrates a timing diagram showing output characteristics of the delay circuit shown in FIG. 6 .
  • FIG. 4 illustrates a circuit diagram of a delay circuit according to an exemplary embodiment of the present invention.
  • a delay circuit as illustrated in FIG. 4 may be used in general flash memories.
  • the delay circuits according to the exemplary embodiments of the present invention may be used with a general flash memory as illustrated in FIG. 1 .
  • the exemplary embodiments may be implemented in other circuit arrangements as design requires.
  • the delay circuit may include an inverter 401 , a resistor 402 , a capacitor 403 , an inverter 404 , a NAND gate 405 , a PMOS transistor 406 , a PMOS transistor 407 , and a capacitor 408 .
  • the inverter 401 , the resistor 402 , and the inverter 404 may be connected in series between an input IN and one input of the NAND gate 405 .
  • a node A 1 between the resistor 402 and the inverter 404 may be coupled to one electrode of the capacitor 403 .
  • the other electrode of the capacitor 403 may be grounded.
  • An input signal IN may be directly applied to an input of the NAND gate 405 and a gate of the PMOS transistor 406 connected between a power supply voltage Vdd and a node B.
  • the node B may be connected to the node A 1 through the PMOS transistor 407 , which has a gate coupled to the node T 1 .
  • the capacitor 408 may be coupled between the node B and ground.
  • FIG. 5 illustrates a timing diagram showing output characteristics of the delay circuit of FIG. 4 .
  • the node A 1 is set to a high level through the inverter 401 .
  • the low level signal actuates the PMOS transistor 406 , allowing Vdd through to the node B.
  • the Vdd at node B increases a voltage level of the node A 1 .
  • the capacitor 408 coupled to the node B is charged up to Vdd.
  • the diode-coupled PMOS transistor 407 remains in an off state, even in a channel conduction state, because a voltage difference between its source (the node B) and drain (the node A 1 ) is not present.
  • the node A 1 When a high level signal is input at the input IN, the node A 1 is set to a low level state by way of the inverter 401 . Moreover, the high level signal causes the PMOS transistor 406 to remain in an off state, or causes the transistor 406 to transition to an off state. This allows the capacitor 408 to discharge. The discharge voltage actuates the PMOS transistor 407 , thereby allowing current to flow between the node A 1 and the node B. In an exemplary embodiment of the present invention, the discharge voltage at node B is Vdd.
  • the delay circuit of FIG. 4 reduces the difference of transition speeds (or times) at the node A 1 in accordance with the variation of the power supply voltage.
  • FIG. 5 illustrates a timing diagram showing output characteristics of the delay circuit of FIG. 4 .
  • trigger points TP 1 ⁇ TP 3 occur in a tight cluster as a result of the delay circuit according to an exemplary embodiment of the present invention.
  • a voltage signal at the node A 1 may be applied to the NAND gate 405 after passing through the inverter 404 . Since, an output of the NAND gate 405 may be dependent upon a voltage transition occurring at the node A 1 , an output signal at the output OUT may change to a low level in response to the trigger point at the node A 1 . However, since the trigger points TP 1 ⁇ TP 3 occur in a very tight cluster, output signal transitions occur at substantially the same time regardless of the level of the power supply voltage (1.5V, 2.5V, or 3.5V).
  • FIG. 6 illustrates a circuit diagram of a delay circuit according to another exemplary embodiment of the present invention.
  • FIG. 7 illustrates a timing diagram showing output characteristics of the delay circuit shown in FIG. 6 .
  • the delay circuit illustrated in FIG. 6 is substantially the same as that illustrated in FIG. 4 .
  • the delay circuit of FIG. 4 includes an inverter 605 connected serially between the inverter 604 (corresponding to the inverter 404 of FIG. 4 ) and the input of the NAND gate 606 (corresponding to 405 of FIG. 4 ). Therefore, an output signal from output signal OUT has a logical state opposite than the output signal illustrated in FIG. 5 .
  • the both inverters 604 and 604 may be removed to achieve the output illustrated in the timing diagram of FIG. 7 .
  • exemplary embodiments of the present invention have been described using substantially three voltage levels and three transition points.
  • the exemplary embodiments of the present invention are merely illustrative of the present invention. Therefore, exemplary embodiments that operate with varying voltage levels and transition points are also within the scope of the present invention.
  • circuits As is understood by those of ordinary skill in the art, the exemplary embodiments of the present invention may be realized using conventional circuitry (i.e., resistors, capacitors, etc.), prepackaged logic devices (i.e., integrated circuits (ICs), gates, etc.), and/or software (Matlab®, Labview®, etc.).
  • circuitry i.e., resistors, capacitors, etc.
  • prepackaged logic devices i.e., integrated circuits (ICs), gates, etc.
  • software Matlab®, Labview®, etc.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Pulse Circuits (AREA)
US10/405,357 2002-04-12 2003-04-03 Semiconductor memory delay circuit Expired - Fee Related US6867628B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR2002-19951 2002-04-12
KR10-2002-0019951A KR100521360B1 (ko) 2002-04-12 2002-04-12 전원 전압에 가변되지 않는 지연 회로 및 이를 포함하는반도체 메모리 장치

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US20030193359A1 US20030193359A1 (en) 2003-10-16
US6867628B2 true US6867628B2 (en) 2005-03-15

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US (1) US6867628B2 (de)
JP (1) JP4032008B2 (de)
KR (1) KR100521360B1 (de)
CN (1) CN1452176B (de)
DE (1) DE10317279B4 (de)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100237342A1 (en) * 2001-11-27 2010-09-23 Semiconductor Energy Laboratory Co., Ltd. Light emitting device
US20110199839A1 (en) * 2010-02-12 2011-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Weak bit compensation for static random access memory
US20120106269A1 (en) * 2010-10-27 2012-05-03 Taiwan Semiconductor Manufacturing Company, Ltd. Memory circuit and method of operating the same

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7460441B2 (en) * 2007-01-12 2008-12-02 Microchip Technology Incorporated Measuring a long time period
CN101557211B (zh) * 2009-04-30 2011-05-18 上海新茂半导体有限公司 时序信号源电路
CN103368366B (zh) * 2012-03-29 2016-10-19 深圳市安邦信电子有限公司 变频器过流保护电路
CN103680592B (zh) * 2013-12-05 2017-03-01 中国科学院微电子研究所 一种延时单元电路及地址信号变化检测电路
CN108347232A (zh) * 2017-01-25 2018-07-31 中芯国际集成电路制造(上海)有限公司 延迟电路及存储器电路
CN109921770A (zh) * 2019-03-07 2019-06-21 维沃移动通信有限公司 一种马达驱动电路及终端设备

Citations (12)

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US5767719A (en) * 1993-11-25 1998-06-16 Nec Corporation Delay circuit using capacitor and transistor
US5801567A (en) * 1993-11-09 1998-09-01 Motorola, Inc. Circuit and method for generating a delayed output signal
US5861765A (en) * 1995-10-11 1999-01-19 Nec Corporation Analogue delay circuit with a constant delay time
US5986492A (en) * 1995-06-05 1999-11-16 Honeywell Inc. Delay element for integrated circuits
US6034557A (en) * 1998-07-31 2000-03-07 Xilinx, Inc. Delay circuit with temperature and voltage stability
US6044027A (en) * 1996-12-13 2000-03-28 Micron Technology, Inc. Circuit and method for providing a substantially constant time delay over a range of supply voltages
US6150864A (en) * 1998-08-24 2000-11-21 Yach; Randy L. Time delay circuit which is voltage independent
US6262616B1 (en) * 1999-10-08 2001-07-17 Cirrus Logic, Inc. Open loop supply independent digital/logic delay circuit
US6300813B1 (en) * 1998-10-07 2001-10-09 Nec Corporation Delay circuit
US6323712B1 (en) * 2000-06-26 2001-11-27 Etron Technology, Inc. Delay circuit with voltage compensation
US6529058B2 (en) * 2001-01-11 2003-03-04 Broadcom Corporation Apparatus and method for obtaining stable delays for clock signals
US6624680B2 (en) * 2000-12-29 2003-09-23 Texas Instruments Incorporated Reduction of propagation delay dependence on supply voltage in a digital circuit

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JPH01119114A (ja) * 1987-10-31 1989-05-11 Sony Corp ディレイ回路
JP3472586B2 (ja) * 1992-03-19 2003-12-02 株式会社日立製作所 半導体集積回路装置
JPH11186887A (ja) * 1997-12-22 1999-07-09 Mitsubishi Electric Corp 遅延回路
KR100503958B1 (ko) * 1998-03-26 2005-09-30 주식회사 하이닉스반도체 어드레스 천이 검출 회로
KR100289398B1 (ko) * 1998-04-22 2001-05-02 김영환 주소천이 검출신호 덧셈회로
DE10056881A1 (de) * 2000-11-16 2002-05-29 Infineon Technologies Ag Integrierter Speicher

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5801567A (en) * 1993-11-09 1998-09-01 Motorola, Inc. Circuit and method for generating a delayed output signal
US5767719A (en) * 1993-11-25 1998-06-16 Nec Corporation Delay circuit using capacitor and transistor
US5986492A (en) * 1995-06-05 1999-11-16 Honeywell Inc. Delay element for integrated circuits
US5861765A (en) * 1995-10-11 1999-01-19 Nec Corporation Analogue delay circuit with a constant delay time
US6044027A (en) * 1996-12-13 2000-03-28 Micron Technology, Inc. Circuit and method for providing a substantially constant time delay over a range of supply voltages
US6034557A (en) * 1998-07-31 2000-03-07 Xilinx, Inc. Delay circuit with temperature and voltage stability
US6150864A (en) * 1998-08-24 2000-11-21 Yach; Randy L. Time delay circuit which is voltage independent
US6300813B1 (en) * 1998-10-07 2001-10-09 Nec Corporation Delay circuit
US6262616B1 (en) * 1999-10-08 2001-07-17 Cirrus Logic, Inc. Open loop supply independent digital/logic delay circuit
US6323712B1 (en) * 2000-06-26 2001-11-27 Etron Technology, Inc. Delay circuit with voltage compensation
US6624680B2 (en) * 2000-12-29 2003-09-23 Texas Instruments Incorporated Reduction of propagation delay dependence on supply voltage in a digital circuit
US6529058B2 (en) * 2001-01-11 2003-03-04 Broadcom Corporation Apparatus and method for obtaining stable delays for clock signals

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100237342A1 (en) * 2001-11-27 2010-09-23 Semiconductor Energy Laboratory Co., Ltd. Light emitting device
US20110199839A1 (en) * 2010-02-12 2011-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Weak bit compensation for static random access memory
US8325510B2 (en) 2010-02-12 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Weak bit compensation for static random access memory
US9208855B2 (en) 2010-02-12 2015-12-08 Taiwan Semiconductor Manufacturing Company, Ltd. Weak bit compensation for static random access memory
US20120106269A1 (en) * 2010-10-27 2012-05-03 Taiwan Semiconductor Manufacturing Company, Ltd. Memory circuit and method of operating the same
US8385136B2 (en) * 2010-10-27 2013-02-26 Taiwan Semiconductor Manufacturing Company, Ltd. Memory circuit and method of operating the same

Also Published As

Publication number Publication date
CN1452176A (zh) 2003-10-29
DE10317279A1 (de) 2003-11-06
US20030193359A1 (en) 2003-10-16
JP4032008B2 (ja) 2008-01-16
CN1452176B (zh) 2012-05-23
KR20030081625A (ko) 2003-10-22
JP2003318708A (ja) 2003-11-07
DE10317279B4 (de) 2006-09-28
KR100521360B1 (ko) 2005-10-12

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