US6812102B2 - Semiconductor device manufacturing method - Google Patents

Semiconductor device manufacturing method Download PDF

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US6812102B2
US6812102B2 US10/466,311 US46631103A US6812102B2 US 6812102 B2 US6812102 B2 US 6812102B2 US 46631103 A US46631103 A US 46631103A US 6812102 B2 US6812102 B2 US 6812102B2
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region
buried channel
insulation layer
gate insulation
impurity concentration
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US20040087093A1 (en
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Kenji Fukuda
Kazuo Arai
Junji Senzaki
Shinsuke Harada
Ryoji Kosugi
Kazuhiro Adachi
Seiji Suzuki
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Japan Science and Technology Agency
National Institute of Advanced Industrial Science and Technology AIST
Sanyo Electric Co Ltd
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National Institute of Advanced Industrial Science and Technology AIST
Sanyo Electric Co Ltd
Japan Science and Technology Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/048—Making electrodes
    • H01L21/049—Conductor-insulator-semiconductor electrodes, e.g. MIS contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7838—Field effect transistors with field effect produced by an insulated gate without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide

Definitions

  • This invention relates to a method of manufacturing a metal-insulator-semiconductor (MIS) field-effect transistor that is fabricated on a silicon carbide substrate in which the crystal surface orientation of the substrate is prescribed and the impurity diffusion layer is optimized, particularly to a method of manufacturing a semiconductor device in which the method of forming a gate insulation layer and the following heat treatment are contrived.
  • MIS metal-insulator-semiconductor
  • U.S. Pat. No. 5,864,157 describes a structure that, in a flash memory having dual gates, uses a P-type electrode for the lower gate and an N-type impurity for the buried channel region.
  • this description relates to a flash memory having dual gates, which is different from the structure of the present invention.
  • concentration of the P-type polysilicon electrode and the impurity concentration of the buried channel region there is no description concerning the concentration of the P-type polysilicon electrode and the impurity concentration of the buried channel region, and the relationship between the depth of the source region or drain region and the depth of the channel region.
  • JP-A HEI 8-186179 there is described a structure, in an N-channel transistor having an LDD structure, that uses a P-type electrode for the gate electrode and an N-type impurity for the buried channel region.
  • this JP-A HEI 8-186179 there is no description concerning the impurity concentration of the P-type polysilicon electrode and the relationship between the depth of the source region or drain region and the depth of the channel region.
  • JP-A HEI 7-131016 describes an MIS field-effect transistor structure characterized by the transistor channel formation surface being parallel to the (1, 1, ⁇ 2, 0) surface of the hexagonal silicon carbide single-crystal substrate. However, this JP-A HEI 7-131016 does not describe anything relating to a buried channel region type MIS field-effect transistor that uses a P-type electrode for the gate electrode.
  • U.S. Pat. No. 5,972,801 describes a method that, following formation of the gate oxide layer, includes exposing the gate oxide layer to an atmosphere containing water vapor at a temperature of 600° C. to 1000° C., but this process is carried out under conditions whereby there is no increase in the thickness of the gate oxide layer of the silicon carbide substrate that is thus further oxidized.
  • JP-A HEI 5-129596 discloses a process for dry oxidation and wet oxidation of a silicon substrate. From the description, this is a process that increases the gate layer thickness by using wet oxidation to oxidize a semiconductor substrate, as understood from the description, “(A) is when dry oxidation is performed for 85 minutes, making the thickness of the gate oxide layer 25.3 nm, and (B) is when, similarly, dry oxidation is performed for 80 minutes, after which wet oxidation is performed for 1 minute, making the thickness of the gate oxide layer 26.3 nm.”
  • this JP-A HEI 5-129596 shows no disclosure relating to the composition of a buried channel type MIS field-effect transistor. It is known that in this type of transistor, the performance is highly dependent on the profile of the diffused impurity. Therefore, the relationship between the heat treatment in the oxidizing process and the introduction of the impurity is important. With respect to the impurity that is introduced, because the present invention uses a silicon carbide substrate having a diffusion coefficient that is lower than that of a silicon substrate, it is possible to use heat treatment for the purpose of oxidation, after forming the diffusion layer used for the buried channel, and the source/drain diffusion layer. The present invention differs from the invention of the JP-A HEI 5-129596 in that it discloses a process that allows the use of a silicon carbide substrate.
  • the interfacial level density of an oxide layer-silicon oxide interface using a silicon carbide substrate generally is approximately one order of magnitude higher. Therefore, an MIS field-effect transistor that uses a silicon carbide substrate has a problem that channel mobility is approximately one order of magnitude lower than that of an MIS field-effect transistor that uses a silicon substrate.
  • a silicon MIS transistor it is known that a buried channel region type MIS field-effect transistor is superior because the flow of electrons from the source to the drain is not readily affected by the above interface between oxide layer and silicon carbide.
  • This invention was proposed in consideration of the above and, in a semiconductor device using a silicon carbide substrate, has as its object to provide a method of manufacturing a semiconductor device that is a buried channel region type transistor that by optimizing the structure of the burned channel region type MIS transistor, gate insulation layer formation method and surface orientation of the silicon carbide substrate, does not become normally on and, moreover, has high hot-carrier resistance, high punch-through resistance and high channel mobility.
  • a first aspect of the present invention relates to a method of manufacturing a semiconductor device characterized by including a step of forming a buried channel region, a source region and a drain region, a step of forming a gate insulation layer after the step of forming the buried channel region, source region and drain region, and a step of exposing the gate insulation layer to an atmosphere containing water vapor at a temperature of 500° C.
  • a semiconductor device characterized by having a semiconductor substrate that forms a P-type silicon carbide region, a gate insulation layer formed on the P-type region, a gate electrode that exhibits P-type characteristics formed on the gate insulation layer, an N-type impurity region having an adequate impurity concentration for forming a buried channel region in a semiconductor layer below the gate insulation layer, and transistor-constituting source and drain regions each composed of an N-type impurity region formed respectively adjacent to the gate insulation layer and the gate electrode.
  • a second aspect of the present invention is characterized by including a step of forming a buried channel region, a source region and a drain region, a step of forming a gate insulation layer after the step of forming the buried channel region, source region and drain region, and a step of exposing the gate insulation layer to an atmosphere containing water vapor at a temperature of 500° C.
  • a semiconductor device in which a ratio (L bc ⁇ Xj) between junction depth (L bc ) of the buried channel region from an interface between the gate insulation layer and the silicon carbide region, and depth (Xj) of a junction portion of the source and drain regions from the interface between the gate insulation layer and the silicon carbide region is within a range of not less than 0.2 and not more than 1.0.
  • a third aspect of the present invention is characterized by including a step of forming a buried channel region and a source region and a drain region, a step of forming a gate insulation layer after the step of forming the buried channel region, source region and drain region, and a step of exposing the gate insulation layer to an atmosphere containing water vapor at a temperature of 500° C. or more after the step of forming the gate insulation layer in the semiconductor device that is polycrystalline silicon in which boron is diffused and which has an impurity concentration within a range of 1 ⁇ 10 16 cm ⁇ 3 to 1 ⁇ 10 21 cm ⁇ 3 .
  • a fourth aspect of the present invention that relates to a buried channel region is characterized by including a step of forming the buried channel region a source region and a drain region, a step of forming a gate insulation layer after the step of forming the buried channel region, source region and drain region, and a step of exposing the gate insulation layer to an atmosphere containing water vapor at a temperature of 500° C. or more after the step of forming the gate insulation layer in the semiconductor device in which the buried channel region has diffused therein a nitrogen, phosphorus or arsenic impurity having a maximum concentration of 5 ⁇ 10 15 cm ⁇ 3 to 1 ⁇ 10 18 cm ⁇ 3 .
  • a fifth aspect of the present invention that relates to lowering resistance of a gate electrode is characterized by including a step of forming a buried channel region, a source region and a drain region, a step of forming a gate insulation layer after the step of forming the buried channel region, source region and drain region, and a step of exposing the gate insulation layer to an atmosphere containing water vapor at a temperature of 500° C. or more after the step of forming the gate insulation layer in the semiconductor device in which the gate electrode includes a high-melting-point metal silicide layer.
  • a sixth aspect of the present invention is characterized by including a step of forming a buried channel region, a source region and a drain region, a step of forming a gate insulation layer after the step of forming the buried channel region, source region and drain region, and a step of exposing the gate insulation layer to an atmosphere containing water vapor at a temperature of 500° C. or more after the step of forming the gate insulation layer in the semiconductor device in which the high-melting-point metal silicide layer is a tungsten, molybdenum or titanium silicide layer.
  • a seventh aspect of the present invention that relates to a hot-carrier resistance improvement technology is characterized by including a step of forming a buried channel region, a source region and a drain region, a step of forming a gate insulation layer after the step of forming the buried channel region, source region and drain region, and a step of exposing the gate insulation layer to an atmosphere containing water vapor at a temperature of 500° C.
  • the gate insulation layer in the semiconductor device that has a region between a region in which the buried channel region is formed and the source or drain region having an impurity concentration that is not lower than a maximum impurity concentration of an impurity diffusion layer region used to form the buried channel region, and not higher than an impurity concentration of the source or drain region.
  • an eighth aspect of the present invention that relates to a hot-carrier resistance improvement technology is characterized by including a step of forming a buried channel region, a source region and a drain region, a step of forming a gate insulation layer after the step of forming the buried channel region, source region and drain region, and a step of exposing the gate insulation layer to an atmosphere containing water vapor at a temperature of 500° C. or more after the step of forming the gate insulation layer in the semiconductor device that includes between a region in which the buried channel is formed and the source or drain region, a diffusion layer of nitrogen, phosphorus or arsenic at a maximum concentration that is 5 ⁇ 10 16 cm ⁇ 3 to 5 ⁇ 10 19 cm ⁇ 3 .
  • a ninth aspect of the present invention that relates to punch-through resistance improvement is characterized by including a step of forming a buried channel region, a source region and a drain region, a step of forming a gate insulation layer after the step of forming the buried channel region, source region and drain region, and a step of exposing the gate insulation layer to an atmosphere containing water vapor at a temperature of 500° C. or more after the step of forming the gate insulation layer in the semiconductor device in which, located adjacently beneath the region in which the buried channel is formed, there is a P-type impurity diffusion region having an impurity concentration that is higher than an impurity concentration of the semiconductor substrate.
  • a tenth aspect of the present invention is characterized by including a step of forming a buried channel region a source region and a drain region, a step of forming a gate insulation layer after the step of forming the buried channel region, source region and drain region, and a step of exposing the gate insulation layer to an atmosphere containing water vapor at a temperature of 500° C. or more after the step of forming the gate insulation layer in a semiconductor device having a high-concentration P-type impurity diffusion region located adjacently beneath the region in which the buried channel is formed that includes an aluminum or boron diffusion layer having a maximum impurity concentration of 1 ⁇ 10 17 cm ⁇ 3 to 1 ⁇ 10 19 cm ⁇ 3 .
  • An eleventh aspect of the present invention relates to channel mobility improvement in a method of manufacturing a semiconductor device characterized by any of the first to tenth aspects, characterized by the gate insulation layer being formed by a thermal oxidation method using dry oxygen.
  • FIG. 1 is a diagram showing stages in a preferred process for manufacturing an MIS field-effect transistor having a P-type gate electrode and a buried channel region.
  • Example 1 is shown in FIGS. 1 ( a ), 1 ( b ) and 1 ( c ), and will be explained in order, with the experiments conducted to obtain the data of FIG. 2 through FIG. 5 .
  • N-type impurity such as nitrogen, phosphorus or arsenic
  • an N-type impurity such as nitrogen, phosphorus or arsenic
  • the desired profile is formed using multiple implantations at 40 to 250 keV to provide a total dose to achieve a concentration of 7 ⁇ 10 16 cm ⁇ 3 .
  • a buried channel region 2 was formed at a depth (L bc ) of 0.1, 0.2, 0.3, 0.4 and 0.5 ⁇ m.
  • L bc a depth of 0.1, 0.2, 0.3, 0.4 and 0.5 ⁇ m.
  • ion implantation was used to prepare samples having concentrations of 5 ⁇ 10 15 cm ⁇ 3 to 5 ⁇ 10 17 cm ⁇ 3 at an L bc of 0.3 ⁇ m.
  • thermal oxidation or CVD chemical vapor deposition
  • a SiO 2 layer for an ion implantation mask 4 for the source region and drain region is used for the source region and drain region.
  • an LTO (low-temperature oxide) layer is used for the implantation mask.
  • silane and oxygen at 400° C. to 800° C. to form silicon dioxide deposited on the P-type silicon carbide substrate 1 , thereby forming the LTO layer.
  • HF hydrofluoric acid
  • ion implantation at 500° C. is used to implant nitrogen, phosphorus or arsenic at a depth (Xj) of 0.5 ⁇ m.
  • Xj a depth of 0.5 ⁇ m.
  • multiple implantation steps are used to form a phosphorus concentration of 5 ⁇ 10 19 cm ⁇ 3 .
  • oxygen or inert gas argon, nitrogen or helium
  • a P-type gate electrode 8 is formed. There are a number of methods for doing this, as shown below.
  • P-type polycrystalline silicon is formed using the CVD method to form polycrystalline silicon, followed by boron or boron fluoride ion implantation.
  • P-type polycrystalline silicon is formed using the CVD method to form polycrystalline silicon, followed by the formation of a boron-containing SiO 2 film by the CVD method or by spin-coating, and using heat treatment at 800° C. to 1100° C. to effect diffusion.
  • P-type polycrystalline silicon is formed flowing silane and diborane together and heat-treating at 600° C. to grow the polycrystalline silicon while diffusing boron.
  • method 2 is used.
  • the diffusion time was changed at 900° C. to form P-type polycrystalline silicon with an impurity concentration of 1 ⁇ 10 15 cm ⁇ 3 to 1 ⁇ 10 21 cm ⁇ 3 , and the relationship between the impurity concentration of the P-type gate electrode and the channel mobility was investigated.
  • high-melting-point metal silicide layers 9 of WSi 2 , MoSi 2 and TiSi 2 were formed on the P-type polycrystalline silicon.
  • the P-type polycrystalline silicon or the composite silicide and P-type polycrystalline silicon layer and the gate insulation layer were then etched to form the gate electrode.
  • the oxide film over the source and drain regions was then etched to form contact holes. Then, vapor deposition or sputtering was used to form a metal-containing layer or laminated layer of nickel, titanium or aluminum, and RIE or wet etching was used to form metal wires 10 . In this example, vapor deposition of nickel was used, followed by wet etching. To ensure good ohmic contact, the samples were then heat-treated for 5 minutes at 1000° C. in an argon atmosphere, thereby completing the MIS field-effect transistors.
  • Table 1 shows a comparison of the effect of the gate oxidation method, post-oxidation heat treatment and buried channel structure on the channel mobility of a MOSFET according to the above process.
  • channel mobility is the same with respect to both dry oxidation and wet oxidation (both being 10 cm 2 /Vs), but when heat treatment in a water vapor atmosphere is also used, channel mobility is 25 cm 2 /Vs in the case of dry oxidation and 15 cm 2 /Vs in the case of wet oxidation, so channel mobility is improved by using water vapor treatment after gate layer formation.
  • channel mobility is higher when dry oxidation is used to form the gate oxidation layer. This is the same in the case of a buried channel structure MOSFET. Gate oxidation by dry oxidation using just argon heat treatment resulted in a normally on condition, making the device unusable in practice, but forming the gate insulation layer by water vapor oxidation resulted in a channel mobility that, at 50 cm 2 /Vs, was improved by the buried channel structure.
  • channel mobility is 140 cm 2 /Vs and 125 cm 2 /Vs in the case of water vapor oxidation, showing that a combination of buried channel structure and post-oxidation water vapor treatment produces a major improvement in channel mobility.
  • channel mobility became highest when the gate insulation layer was formed using dry oxidation.
  • channel mobility improves as the water vapor treatment time is increased from 0 (zero).
  • critical time a time at which channel mobility is exhibited that is below the channel mobility when water vapor treatment is not used.
  • this critical time varies depending on substrate impurity concentration and the like, it cannot be uniformly specified. Also, it can be readily understood that there is an optimum time at which maximum channel mobility is reached. It is desirable for the time of the water vapor treatment of the present invention to be carried out in this optimum time.
  • FIG. 2 shows the measurement-based relationship between channel mobility and threshold voltage in a MIS field-effect transistor with a gate electrode using P-type polycrystalline silicon, N-type polycrystalline silicon and aluminum.
  • channel mobility is higher with a gate electrode that uses P-type polycrystalline silicon than that of a gate electrode that uses N-type polycrystalline silicon or aluminum. This is due to the fact that, depending on the gate electrode polarity, a different amount of ion implantation is required to achieve the same threshold voltage; possible reasons are detailed below.
  • Implantation of N-type impurity into the buried channel region 2 results in the center of the channel being formed at a deep location away from the interface between the gate insulation layer and the P-type silicon carbide substrate 1 . Since this increases the number of carriers that are not readily susceptible to the effect of the high field near the interface, channel mobility is increased. Mobility is also increased by a low channel concentration of implanted P-type impurity. However, if the N-type impurity in the buried channel region 2 is increased to increase the channel mobility, the threshold voltage decreases, becoming a negative voltage, creating a state in which current flows even at a zero voltage, that is, a normally on state.
  • the threshold voltage of the MIS field-effect transistor becomes larger as the work function differential between a gate electrode and a semiconductor becomes larger.
  • the work function differential between the gate electrode and the semiconductor it is also known that there is almost no change when aluminum or N-type polycrystalline silicon is used for the gate electrode, but when P-type polycrystalline silicon is used, compared to the semiconductor substrate, it becomes approximately one volt more.
  • the tendency for the threshold voltage to go negative and create a normally on state can be suppressed by using P-type polycrystalline silicon for the gate electrode, so that even with the same threshold voltage, channel mobility can be increased by implanting an impurity concentration for forming the buried channel region that is higher compared to aluminum and N-type polycrystalline silicon used for the gate electrode. This makes it possible to form a channel at a deeper location, therefore making it possible to increase the channel mobility.
  • FIG. 3 is a graph showing the L bc ⁇ Xj dependency of the channel mobility, when the junction depth Xj of the source and drain diffusion layers is 0.5 ⁇ m.
  • the vertical axis shows the normalized channel mobility of a sample having no buried channel region. The evaluation was performed using an L bc of 0.2 or more; it was confirmed that there was an effect even at 0.2. Therefore, the lower limit on the horizontal axis was set at 0.2. At over 1 on the horizontal axis, channel mobility increases, but the threshold voltage goes negative, resulting in a normally on state that makes the device difficult to use in practice. Therefore, the horizontal axis is limited to 0.2 to 1.0. A range of 0.4 to 1.0 is particularly effective.
  • FIG. 4 shows the measured relationship between the impurity concentration of the P-type polycrystalline silicon gate and the threshold voltage.
  • a higher concentration increases the work function differential between the gate electrode and the semiconductor substrate, increasing the threshold voltage.
  • a lower concentration decreases the threshold voltage, which at 1 ⁇ 10 16 cm ⁇ 3 becomes zero. Therefore the lower limit for the impurity concentration is set at 1 ⁇ 10 16 cm ⁇ 3 , and since the concentration of boron capable of being implanted into polycrystalline silicon is 1 ⁇ 10 21 cm ⁇ 3 , the upper limit is set at 1 ⁇ 10 21 cm ⁇ 3 .
  • FIG. 5 shows the measured relationship between channel mobility (using the value at an impurity concentration of zero as the standard value) and the impurity concentration of the buried channel region 2 .
  • the lower limit of the evaluation impurity concentration was 5 ⁇ 10 15 cm ⁇ 3 . Since an adequate effect was achieved with that value, the lower limit was set at 5 ⁇ 10 15 cm ⁇ 3 . With a concentration of 1 ⁇ 10 18 cm ⁇ 3 or more, the threshold voltage goes negative, making the device hard to use, so the upper limit was set at 1 ⁇ 10 18 cm ⁇ 3 .
  • the gate voltage that gives rise to punch-through is the same as when there is no P+ region, which is the same as no effect.
  • a concentration of at least 1 ⁇ 10 17 cm ⁇ 3 increases the gate voltage at which punch-through occurs, so the lower limit is 1 ⁇ 10 17 cm ⁇ 3 .
  • the impurity concentration is 1 ⁇ 10 19 cm ⁇ 3 or higher, the impurity diffuses during activation annealing, offsetting the N-type impurity in the channel region above, making it impossible for the buried channel region to function as required. Therefore, the upper limit is 1 ⁇ 10 19 cm ⁇ 3 .
  • the specific resistance of polycrystalline silicon given a high boron concentration is on the milli ⁇ cm level, but the specific resistances of the high-melting-point metal silicides, for example MoSi 2 , WSi 2 and TiSi 2 are 60 ⁇ cm, 50 ⁇ cm and 15 ⁇ cm, respectively, so the specific resistance of a gate electrode that is a composite of polycrystalline silicon and silicide is lower compared to polycrystalline silicon in which impurity has been implanted.
  • a polycide structure that is a laminated layer of polycrystalline silicon and silicide.
  • FIGS. 1 ( a ), 1 ( b ) and 1 ( d ) show the order of a specific manufacturing process of Example 2.
  • an LTO layer was formed over the whole surface and photolithography was used to leave the gate electrode portion resist, with hydrofluoric acid being used to etch the LTO layer. Then, to investigate the hot-carrier resistance effect of the impurity concentration between the buried channel region 2 and the source 5 or drain 6 , ion implantation of phosphorus at 500° C. was used to form a low-impurity-concentration region 11 having an impurity concentration of 5 ⁇ 10 16 cm ⁇ 3 to 5 ⁇ 10 20 cm ⁇ 3 between the buried channel region 2 of FIG. 1 ( d ) and the source 5 or drain 6 .
  • an LTO layer was formed over the whole surface and photolithography used to form a photoresist to define the source and drain regions, and HF (hydrofluoric acid) was used to etch the LTO layer and expose the ion implantation source and drain regions.
  • the source 5 and drain 6 were then formed using multiple ion implantations of phosphorus at 500° C. to form an impurity concentration of 5 ⁇ 10 19 cm ⁇ 3 . This was followed by activation annealing for 30 minutes at 1500° C. in an argon atmosphere.
  • the P-type polycrystalline silicon and the gate insulation layer were then etched to form the gate electrode.
  • LTO was deposited over the whole surface of the oxide layer and the oxide film over the source 5 and drain 6 was etched to form contact holes.
  • the electron-beam deposition method was then used to form a nickel film over-the layer, and wet etching was used to form metal wires 10 .
  • the samples were then heat-treated for 5 minutes at 1000° C. in an argon atmosphere, thereby completing the MIS field-effect transistors.
  • the transistors were subjected to an electrical stress for a set time, and the degree by which the threshold voltage changed was measured to evaluate hot-carrier resistance. A smaller change in threshold voltage indicated good hot-carrier resistance.
  • the threshold voltage was obtained as the voltage at which, with 0.1 volt applied to the drain and with the source at 0 volt, along a gate voltage of zero to 30 volts, the square of half the drain current intersects the plotted voltage axis.
  • the electrical stress comprised applying 5 volts to the drain and 2.5 volts to the gate, for five minutes.
  • the transistors measured were those in which ion implantation of phosphorus was used to form an impurity concentration of 5 ⁇ 10 16 cm ⁇ 3 to 5 ⁇ 10 19 cm ⁇ 3 between the buried channel region 2 and the source or drain region.
  • a low impurity concentration in this region results in a larger depletion layer owing to which a field is smaller in the vicinity of the drain, making it possible to prevent electrons that pass through the region from entering a high-energy state, thereby improving hot-carrier resistance by decreasing the number of electrons that are implanted into the gate insulation layer from the substrate by scattering.
  • the impurity concentration of this region is too low, the resistance of the region will become too high, reducing the driving force of the transistor, leading to a lower limit of 5 ⁇ 10 16 cm ⁇ 3 . If the concentration is too high, the field in the vicinity of the drain will not be alleviated, making it impossible to attain sufficient hot-carrier resistance. From measurements, it was found that with a concentration of 5 ⁇ 10 19 cm ⁇ 3 or more, the amount of change in threshold voltage exceeded 10%. That much change is too much for practical use. Therefore, the upper limit became 5 ⁇ 10 19 cm ⁇ 3 .
  • the first aspect of the present invention is a method of manufacturing a semiconductor device using a P-type gate electrode that includes heat treatment in an atmosphere containing water vapor, following gate insulation layer formation. This makes it possible to use a relatively high N concentration without the device becoming normally on, making it possible to increase channel mobility.
  • the ratio between the junction depth Xj of the source and drain regions and the junction depth L bc of the buried channel region junction is optimized, and after its formation the gate insulation layer is heat-treated in an atmosphere containing water vapor, which enables the channel mobility to be improved.
  • the concentration of the P-type polycrystalline silicon is optimized, and after its formation the gate insulation layer is heat-treated in an atmosphere containing water vapor, which enables the channel mobility to be improved.
  • the concentration of the buried channel region is optimized, and after its formation the gate insulation layer is heat-treated in an atmosphere containing water vapor, which enables the channel mobility to be improved.
  • the gate electrode resistance value is lowered by overlaying a high-melting-point metal silicide layer on the P-type polycrystalline silicon, and, following its formation, heat-treating the gate insulation layer in an atmosphere containing water vapor, which enables the driving power to be improved.
  • a sixth aspect of the present invention uses a tungsten, molybdenum or titanium silicide layer, and also, following its formation, heat-treats the gate insulation layer in an atmosphere containing water vapor, which enables the operating speed of the semiconductor device to be improved.
  • seventh and eighth aspects of the present invention improve both hot-carrier resistance and driving power by providing a region between the buried channel region and the source or drain region having an impurity concentration that is not lower than the impurity concentration of the buried channel region, and not higher than the impurity concentration of the source or drain region, and by, after formation of the gate insulation layer, heat-treating the gate insulation layer in an atmosphere containing water vapor.
  • ninth and tenth aspects of the present invention improve both punch-through resistance and driving power by providing adjacently beneath the buried channel region, an impurity region of the P-type semiconductor substrate 1 or by optimizing the concentration thereof, and, at the same time, by, following formation of the gate insulation layer, heat-treating the gate insulation layer in an atmosphere containing water vapor.
  • an eleventh aspect of the present invention relates to a method of manufacturing a semiconductor device in which channel mobility can be improved by forming the gate insulation layer by using a thermal oxidation method employing dry oxygen followed by heat treatment in an atmosphere containing vapor.

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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040242022A1 (en) * 2001-09-10 2004-12-02 Ryoji Kosugi Production method for semiconductor device
US20050217510A1 (en) * 2004-03-30 2005-10-06 Cnh America Llc Cotton module program control using yield monitor signal
US20050245034A1 (en) * 2002-06-28 2005-11-03 National Institute Of Advanced Indust Sci& Tech Semiconductor device and its manufacturing method
US20060226482A1 (en) * 2005-03-30 2006-10-12 Suvorov Alexander V Methods of fabricating silicon nitride regions in silicon carbide and resulting structures
US20090242901A1 (en) * 2006-11-06 2009-10-01 General Electric Company SiC MOSFETS AND SELF-ALIGNED FABRICATION METHODS THEREOF
US20110024765A1 (en) * 2009-07-31 2011-02-03 General Electric Company Silicon carbide semiconductor structures, devices and methods for making the same
US20160211333A1 (en) * 2013-09-06 2016-07-21 Sumitomo Electric Industries, Ltd. Silicon carbide semiconductor device and method of manufacturing the same

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4842527B2 (ja) * 2004-08-24 2011-12-21 パナソニック株式会社 半導体装置の製造方法
JP2006269641A (ja) * 2005-03-23 2006-10-05 National Institute Of Advanced Industrial & Technology 半導体装置及びその製造方法
WO2008005092A2 (en) * 2006-06-29 2008-01-10 Cree, Inc. Silicon carbide switching devices including p-type channels and methods of forming the same
US8432012B2 (en) 2006-08-01 2013-04-30 Cree, Inc. Semiconductor devices including schottky diodes having overlapping doped regions and methods of fabricating same
US7728402B2 (en) 2006-08-01 2010-06-01 Cree, Inc. Semiconductor devices including schottky diodes with controlled breakdown
CN101501859B (zh) 2006-08-17 2011-05-25 克里公司 高功率绝缘栅双极晶体管
US8835987B2 (en) 2007-02-27 2014-09-16 Cree, Inc. Insulated gate bipolar transistors including current suppressing layers
JP5135004B2 (ja) * 2008-02-29 2013-01-30 株式会社東芝 不揮発性半導体記憶装置、及びディプレッション型ｍｏｓトランジスタ
US8232558B2 (en) 2008-05-21 2012-07-31 Cree, Inc. Junction barrier Schottky diodes with current surge capability
US8294507B2 (en) 2009-05-08 2012-10-23 Cree, Inc. Wide bandgap bipolar turn-off thyristor having non-negative temperature coefficient and related control circuits
US8193848B2 (en) 2009-06-02 2012-06-05 Cree, Inc. Power switching devices having controllable surge current capabilities
US8629509B2 (en) 2009-06-02 2014-01-14 Cree, Inc. High voltage insulated gate bipolar transistors with minority carrier diverter
US8541787B2 (en) 2009-07-15 2013-09-24 Cree, Inc. High breakdown voltage wide band-gap MOS-gated bipolar junction transistors with avalanche capability
JP2011034004A (ja) * 2009-08-05 2011-02-17 Sony Corp 補正回路および表示装置
US8841682B2 (en) * 2009-08-27 2014-09-23 Cree, Inc. Transistors with a gate insulation layer having a channel depleting interfacial charge and related fabrication methods
US8354690B2 (en) 2009-08-31 2013-01-15 Cree, Inc. Solid-state pinch off thyristor circuits
US9117739B2 (en) 2010-03-08 2015-08-25 Cree, Inc. Semiconductor devices with heterojunction barrier regions and methods of fabricating same
US8415671B2 (en) 2010-04-16 2013-04-09 Cree, Inc. Wide band-gap MOSFETs having a heterojunction under gate trenches thereof and related methods of forming such devices
US9478616B2 (en) * 2011-03-03 2016-10-25 Cree, Inc. Semiconductor device having high performance channel
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US9142662B2 (en) 2011-05-06 2015-09-22 Cree, Inc. Field effect transistor devices with low source resistance
US8680587B2 (en) 2011-09-11 2014-03-25 Cree, Inc. Schottky diode
US9373617B2 (en) 2011-09-11 2016-06-21 Cree, Inc. High current, low switching loss SiC power module
US9640617B2 (en) 2011-09-11 2017-05-02 Cree, Inc. High performance power module
JP2014531752A (ja) 2011-09-11 2014-11-27 クリー インコーポレイテッドＣｒｅｅ Ｉｎｃ． 改善したレイアウトを有するトランジスタを備える高電流密度電力モジュール
US8664665B2 (en) 2011-09-11 2014-03-04 Cree, Inc. Schottky diode employing recesses for elements of junction barrier array
US8618582B2 (en) 2011-09-11 2013-12-31 Cree, Inc. Edge termination structure employing recesses for edge termination elements
JP6041311B2 (ja) * 2013-06-21 2016-12-07 国立研究開発法人産業技術総合研究所 炭化珪素半導体装置の製造方法
JP6295797B2 (ja) 2014-04-10 2018-03-20 住友電気工業株式会社 炭化珪素半導体装置およびその製造方法
JP2016066641A (ja) 2014-09-22 2016-04-28 株式会社東芝 半導体装置及び半導体装置の製造方法
US10446681B2 (en) 2017-07-10 2019-10-15 Micron Technology, Inc. NAND memory arrays, and devices comprising semiconductor channel material and nitrogen
US10559466B2 (en) 2017-12-27 2020-02-11 Micron Technology, Inc. Methods of forming a channel region of a transistor and methods used in forming a memory array
US10297611B1 (en) 2017-12-27 2019-05-21 Micron Technology, Inc. Transistors and arrays of elevationally-extending strings of memory cells
US20200135489A1 (en) * 2018-10-31 2020-04-30 Atomera Incorporated Method for making a semiconductor device including a superlattice having nitrogen diffused therein
US11538919B2 (en) 2021-02-23 2022-12-27 Micron Technology, Inc. Transistors and arrays of elevationally-extending strings of memory cells

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4160987A (en) * 1976-05-14 1979-07-10 International Business Machines Corporation Field effect transistors with polycrystalline silicon gate self-aligned to both conductive and non-conductive regions and fabrication of integrated circuits containing the transistors
US4396438A (en) * 1981-08-31 1983-08-02 Rca Corporation Method of making CCD imagers
US4658278A (en) * 1985-04-15 1987-04-14 Rca Corporation High density charge-coupled device imager and method of making the same
US4866497A (en) * 1984-06-01 1989-09-12 General Electric Company Infra-red charge-coupled device image sensor
JPH08186179A (ja) 1994-12-28 1996-07-16 Sony Corp 相補型半導体装置
US5965919A (en) * 1995-10-19 1999-10-12 Samsung Electronics Co., Ltd. Semiconductor device and a method of fabricating the same
US6084247A (en) * 1993-02-15 2000-07-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having a catalyst enhanced crystallized layer
US6107126A (en) * 1998-01-26 2000-08-22 Texas Instruments-Acer Incorporated Method to form different threshold NMOSFETS for read only memory devices
US6617653B1 (en) * 2000-05-31 2003-09-09 Matsushita Electric Industrial Co., Ltd. Misfet

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4990974A (en) 1989-03-02 1991-02-05 Thunderbird Technologies, Inc. Fermi threshold field effect transistor
JPH05129596A (ja) 1991-11-07 1993-05-25 Mitsubishi Materials Corp ゲート酸化膜の形成方法
US5972801A (en) * 1995-11-08 1999-10-26 Cree Research, Inc. Process for reducing defects in oxide layers on silicon carbide
US6028012A (en) * 1996-12-04 2000-02-22 Yale University Process for forming a gate-quality insulating layer on a silicon carbide substrate

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4160987A (en) * 1976-05-14 1979-07-10 International Business Machines Corporation Field effect transistors with polycrystalline silicon gate self-aligned to both conductive and non-conductive regions and fabrication of integrated circuits containing the transistors
US4396438A (en) * 1981-08-31 1983-08-02 Rca Corporation Method of making CCD imagers
US4866497A (en) * 1984-06-01 1989-09-12 General Electric Company Infra-red charge-coupled device image sensor
US4658278A (en) * 1985-04-15 1987-04-14 Rca Corporation High density charge-coupled device imager and method of making the same
US6084247A (en) * 1993-02-15 2000-07-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having a catalyst enhanced crystallized layer
JPH08186179A (ja) 1994-12-28 1996-07-16 Sony Corp 相補型半導体装置
US5965919A (en) * 1995-10-19 1999-10-12 Samsung Electronics Co., Ltd. Semiconductor device and a method of fabricating the same
US6107126A (en) * 1998-01-26 2000-08-22 Texas Instruments-Acer Incorporated Method to form different threshold NMOSFETS for read only memory devices
US6617653B1 (en) * 2000-05-31 2003-09-09 Matsushita Electric Industrial Co., Ltd. Misfet

Non-Patent Citations (7)

* Cited by examiner, † Cited by third party
Title
Katsunori Ueno et al.: "Counter-doped MOSFET's of 4H-SiC" IEEE Electron Device Letters, vol. 20, No. 12, pp. 624-626 Dec. 1999.
Lori A. Lipkin et al.: "Insulator Investigation on SiC for improved reliability" IEEE Transactions on Electron Devices, vol. 46, No. 3, pp. 525-532 03/99.
Lori A. Lipkin et al.: "SiC devices with ONO stacked dielectrics" Materials Science Forum vols. 338 to 242, Silicon Carbide and Related Materials, pp. 1093-1096 12/99.
Man Pio Lam et al.: "Punchthrough behavior in short channel NMOS and PMOS 6H-silicon carbide transistors at elevated temperatures" IEEE Transactions on Components and Packaging Technology, vol. 22, No. 3, pp. 433-438, 09/99.
Scott T. Sheppard et al.: "Characteristics of inversion-channel and buried-channel MOS devices in 6H-SiC" IEEE Transactions on Electron Devices, vol. 41, No. 7, pp. 1257-1264, 07/94.
Ulrich Schmid et al.: "High temperature performance of NMOS integrated inverters and ring oscillators in 6H-SiC" IEEE Transactions on Electron Devices, vol. 47, No. 4, pp. 687-691 04/00.
William E. Wagner et al.: "characterization of silicon carbide (Sic) epitaxial channel MOSFETs" IEEE Transactions on Electron Devices, vol. 47, No. 11, pp. 2214-2220 11/00.

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040242022A1 (en) * 2001-09-10 2004-12-02 Ryoji Kosugi Production method for semiconductor device
US7256082B2 (en) * 2001-09-10 2007-08-14 National Institute Of Advanced Industrial Science And Technology Production method for semiconductor device
US20050245034A1 (en) * 2002-06-28 2005-11-03 National Institute Of Advanced Indust Sci& Tech Semiconductor device and its manufacturing method
US7338869B2 (en) 2002-06-28 2008-03-04 National Institute Of Advanced Industrial Science And Technology Semiconductor device and its manufacturing method
US20050217510A1 (en) * 2004-03-30 2005-10-06 Cnh America Llc Cotton module program control using yield monitor signal
US20060226482A1 (en) * 2005-03-30 2006-10-12 Suvorov Alexander V Methods of fabricating silicon nitride regions in silicon carbide and resulting structures
US7476594B2 (en) 2005-03-30 2009-01-13 Cree, Inc. Methods of fabricating silicon nitride regions in silicon carbide and resulting structures
US20090242901A1 (en) * 2006-11-06 2009-10-01 General Electric Company SiC MOSFETS AND SELF-ALIGNED FABRICATION METHODS THEREOF
US8377812B2 (en) * 2006-11-06 2013-02-19 General Electric Company SiC MOSFETs and self-aligned fabrication methods thereof
US20110024765A1 (en) * 2009-07-31 2011-02-03 General Electric Company Silicon carbide semiconductor structures, devices and methods for making the same
US20160211333A1 (en) * 2013-09-06 2016-07-21 Sumitomo Electric Industries, Ltd. Silicon carbide semiconductor device and method of manufacturing the same

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