US6406994B1 - Triple-layered low dielectric constant dielectric dual damascene approach - Google Patents

Triple-layered low dielectric constant dielectric dual damascene approach Download PDF

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US6406994B1
US6406994B1 US09/726,657 US72665700A US6406994B1 US 6406994 B1 US6406994 B1 US 6406994B1 US 72665700 A US72665700 A US 72665700A US 6406994 B1 US6406994 B1 US 6406994B1
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dielectric layer
layer
hard mask
overlying
etching
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Ting Cheong Ang
Shyue Fong Quek
Yee Chong Wong
Sang Yee Loong
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GlobalFoundries Singapore Pte Ltd
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Chartered Semiconductor Manufacturing Pte Ltd
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41M—PRINTING, DUPLICATING, MARKING, OR COPYING PROCESSES; COLOUR PRINTING
    • B41M5/00—Duplicating or marking methods; Sheet materials for use therein
    • B41M5/025—Duplicating or marking methods; Sheet materials for use therein by transferring ink from the master sheet
    • B41M5/06—Duplicating or marking methods; Sheet materials for use therein by transferring ink from the master sheet using master sheets coated with jelly-like materials, e.g. gelatin
    • B41M5/08—Sheet materials therefor
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41M—PRINTING, DUPLICATING, MARKING, OR COPYING PROCESSES; COLOUR PRINTING
    • B41M5/00—Duplicating or marking methods; Sheet materials for use therein
    • B41M5/50—Recording sheets characterised by the coating used to improve ink, dye or pigment receptivity, e.g. for ink-jet or thermal dye transfer recording
    • B41M5/52—Macromolecular coatings
    • B41M5/5254—Macromolecular coatings characterised by the use of polymers obtained by reactions only involving carbon-to-carbon unsaturated bonds, e.g. vinyl polymers
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41M—PRINTING, DUPLICATING, MARKING, OR COPYING PROCESSES; COLOUR PRINTING
    • B41M5/00—Duplicating or marking methods; Sheet materials for use therein
    • B41M5/50—Recording sheets characterised by the coating used to improve ink, dye or pigment receptivity, e.g. for ink-jet or thermal dye transfer recording
    • B41M5/502—Recording sheets characterised by the coating used to improve ink, dye or pigment receptivity, e.g. for ink-jet or thermal dye transfer recording characterised by structural details, e.g. multilayer materials
    • B41M5/508—Supports
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41M—PRINTING, DUPLICATING, MARKING, OR COPYING PROCESSES; COLOUR PRINTING
    • B41M5/00—Duplicating or marking methods; Sheet materials for use therein
    • B41M5/50—Recording sheets characterised by the coating used to improve ink, dye or pigment receptivity, e.g. for ink-jet or thermal dye transfer recording
    • B41M5/52—Macromolecular coatings
    • B41M5/5218—Macromolecular coatings characterised by inorganic additives, e.g. pigments, clays
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41M—PRINTING, DUPLICATING, MARKING, OR COPYING PROCESSES; COLOUR PRINTING
    • B41M5/00—Duplicating or marking methods; Sheet materials for use therein
    • B41M5/50—Recording sheets characterised by the coating used to improve ink, dye or pigment receptivity, e.g. for ink-jet or thermal dye transfer recording
    • B41M5/52—Macromolecular coatings
    • B41M5/5263—Macromolecular coatings characterised by the use of polymers obtained otherwise than by reactions only involving carbon-to-carbon unsaturated bonds
    • B41M5/5272—Polyesters; Polycarbonates
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]

Definitions

  • the invention relates to a method of metallization in the fabrication of integrated circuits, and more particularly, to a method of dual damascene metallization using low dielectric constant materials in the manufacture of integrated circuits.
  • the damascene or dual damascene process has become a future trend in integrated circuit manufacturing, especially in the copper metallization process. These processes are discussed in ULSI Technology , by Chang and Sze, The McGraw Hill Companies, Inc., NY, N.Y., c. 1996, pp. 444-445. Low dielectric constant materials have been proposed as the dielectric materials in order to reduce capacitance. In the conventional damascene scheme, one or more etch stop and/or barrier layers comprising high dielectric constant materials, such as silicon nitride, are required. This defeats the purpose of the low dielectric constant materials. It is desired to find a process which does not require a high dielectric constant etch stop/barrier layer.
  • U.S. Pat. No. 5,635,423 to Huang et al teaches various methods of forming a dual damascene opening.
  • An etch stop layer such as silicon nitride or polysilicon is used. This is the conventional approach to dual damascene structure, with no consideration for dielectric constant value.
  • U.S. Pat. Nos. 5,935,762 to Dai et al and 5,877,076 to Dai show a double mask self-aligned process using a silicon nitride etch stop layer.
  • U.S. Pat. No. 5,798,302 to Hudson et al shows a damascene process.
  • a principal object of the present invention is to provide an effective and very manufacturable method of metallization in the fabrication of integrated circuit devices.
  • Another object of the invention is to provide a dual damascene metallization process using low dielectric constant materials.
  • Yet another object of the invention is to provide a dual damascene metallization process using low dielectric constant materials without using a high dielectric constant etch stop material.
  • a further object of the invention is to provide a triple layered low dielectric constant material dual damascene metallization process.
  • a triple layered low dielectric constant material dual damascene metallization process is achieved.
  • Metal lines are provided covered by an insulating layer overlying a semiconductor substrate.
  • a first dielectric layer of a first type is deposited overlying the insulating layer.
  • a second dielectric layer of a second type is deposited overlying the first dielectric layer.
  • a via pattern is etched into the second dielectric layer.
  • a third dielectric layer of the first type is deposited overlying the patterned second dielectric layer.
  • a trench pattern is etched into the third dielectric layer and the via pattern is etched into the first dielectric layer to complete the formation of dual damascene openings in the fabrication of an integrated circuit device.
  • the second type will be a low dielectric constant inorganic material.
  • the second type will be a low dielectric constant organic material.
  • FIGS. 1 through 8 schematically illustrate in cross-sectional representation a dual damascene process of the present invention.
  • FIGS. 2A and 2B illustrate two alternatives in the preferred embodiment of the present invention.
  • the present invention provides a triple-layered low dielectric constant material self-aligned dual damascene process.
  • a high dielectric constant material etch stop/barrier layer is not required in the process of the present invention.
  • FIG. 1 there is illustrated a portion of a partially completed integrated circuit device.
  • a semiconductor substrate 10 preferably composed of monocrystalline silicon.
  • Semiconductor device structures such as gate electrodes, source and drain regions, and metal interconnects, not shown, are formed in and on the semiconductor substrate and covered with an insulating layer.
  • Interconnection lines such as tungsten, copper or aluminum-copper lines 14 , for example, are formed over the insulating layer and will contact some of the underlying semiconductor device structures through openings in the insulating layer, not shown.
  • a passivation or barrier layer 16 is formed over the metal lines and planarized. Now, the key features of the present invention will be described.
  • a first dielectric layer 18 is deposited over the barrier layer 16 to a thickness of between about 6000 and 20,000 Angstroms.
  • This dielectric layer 18 comprises a low dielectric constant organic material, such as polyimides, HOSP, SILK, FLARE, BCB, methylsilsesquioxane (MSQ), or any organic polymers.
  • the dielectric constant should be less than about 3.5.
  • a second low dielectric layer 20 is deposited to a thickness of between about 1000 and 10,000 Angstroms.
  • the second dielectric layer 20 comprises a low dielectric constant inorganic material, such as Black Diamond, CORAL, fluorinated silicate glass (FSG), carbon-doped FSG, nitrogen-doped FSG, Z3MS, XLK, and hydrogen silsesqioxane (HSQ).
  • the dielectric constant should be less than about 3.5.
  • a photoresist layer is coated over the second dielectric layer 20 and patterned to form a photoresist mask 25 for the via pattern.
  • the second dielectric layer 20 is etched where it is not covered by the photoresist mask 25 to form the via pattern, as shown in FIG. 3 .
  • the photoresist mask 25 is removed.
  • the first layer 20 is inorganic, and the second layer 18 is organic, as shown in FIG. 2B.
  • a hard mask layer 24 is deposited over the second dielectric layer.
  • the hard mask layer may comprise silicon oxynitride, silicon oxide, or silicon nitride and have a thickness of between about 500 and 5000 Angstroms.
  • the hard mask layer is necessary when the top dielectric layer is organic to prevent the photoresist removal step from removing also the dielectric layer.
  • the hard mask layer eliminates photoresist poisoning of the low dielectric constant organic dielectric layer. It is not necessary to use a hard mask when the top dielectric layer is inorganic, as in FIG. 2 A.
  • a photoresist layer is coated over the hard mask layer 24 and patterned to form a photoresist mask 25 for the via pattern.
  • the hard mask layer 24 is etched where it is not covered by the photoresist mask 25 to form the via pattern.
  • the photoresist mask 25 is removed.
  • the second dielectric layer 18 is etched where it is not covered by the hard mask 24 to form the via pattern as shown in FIG. 3 .
  • the hard mask layer 24 is stripped.
  • FIG. 3 and the following figures illustrate the alternative in which the inorganic dielectric layer 20 overlies the organic dielctric layer 18 . It will be understood that processing would be the same in the case of the alternative illustrated in FIG. 2B where the organic layer 18 overlies the inorganic layer 20 .
  • a third dielectric layer 26 is deposited over the patterned second dielectric layer 20 to a thickness of between about 2000 and 20,000 Angstroms, as shown in FIG. 4 .
  • this dielectric layer 26 comprises a low dielectric constant organic material, such as polyimides, HOSP, SILK, FLARE, BCB, MSQ, or any organic polymers.
  • this dielectric layer 26 comprises a low dielectric constant inorganic material, such as Black Diamond, CORAL, FSG, carbon-doped FSG, nitrogen-doped FSG, Z3MS, XLK, and HSQ.
  • a second photoresist layer is coated over the third dielectric layer 26 and patterned to form the photoresist mask 29 having a trench pattern. If the third dielectric layer 26 is organic, a hard mask, not shown, must be used underlying the photoresist layer so that photoresist removal will not damage the organic layer.
  • the third and first dielectric materials are etched to form simultaneously both the trench and the via portions of the dual damascene opening, as shown in FIG. 6 . Since both the first and third dielectric materials are of the same type, the etching recipe is chosen to etch these materials with a high selectivity to the second dielectric material. In this way, the second dielectric material acts as an etch stop.
  • the photoresist mask 29 is removed, leaving the completed dual damascene openings 32 , shown in FIG. 7 . If a hard mask was used, this is removed also.
  • the process of the invention has formed the dual damascene openings using a triple layer of low dielectric constant materials. No high dielectric constant material was used as an etch stop. Therefore, low capacitance is maintained.
  • a barrier metal layer is typically deposited over the third dielectric layer and within the openings.
  • a metal layer such as copper, is formed within the openings, such as by sputtering, electroless plating, or electroplating, for example. The excess metal may be planarized to complete the metal fill 34 , as shown in FIG. 8 .
  • the process of the present invention provides a simple and manufacturable dual damascene process where only low dielectric constant materials are used. No high dielectric constant materials are required as etch stops.
  • the process of the invention uses a novel triple layer of low dielectric constant materials to form dual damascene openings in the manufacture of integrated circuits.
  • the novel triple layer of low dielectric constant materials comprises a first and third layer of inorganic material with an organic material therebetween or a first and third layer of organic material with an inorganic material therebetween.

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  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Laminated Bodies (AREA)
  • Thermal Transfer Or Thermal Recording In General (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
US09/726,657 1999-12-03 2000-11-30 Triple-layered low dielectric constant dielectric dual damascene approach Expired - Lifetime US6406994B1 (en)

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EP (1) EP1104702B1 (fr)
KR (1) KR100732903B1 (fr)
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US6524947B1 (en) * 2001-02-01 2003-02-25 Advanced Micro Devices, Inc. Slotted trench dual inlaid structure and method of forming thereof
US6534397B1 (en) * 2001-07-13 2003-03-18 Advanced Micro Devices, Inc. Pre-treatment of low-k dielectric for prevention of photoresist poisoning
US20030153132A1 (en) * 1997-06-19 2003-08-14 Tongbi Jiang Plastic lead frames for semiconductor devices, packages including same, and methods of fabrication
US6624055B1 (en) * 2002-08-14 2003-09-23 United Microelectronics Corp. Method for forming a plane structure
US20040033628A1 (en) * 2002-08-14 2004-02-19 United Microelectronics Corp Method for forming a plane structure
US6716741B2 (en) * 2002-04-09 2004-04-06 United Microelectronics Corp. Method of patterning dielectric layer with low dielectric constant
US20040094839A1 (en) * 2002-11-14 2004-05-20 International Business Machines Corporation Reliable low-k interconnect structure with hybrid dielectric
US20050070098A1 (en) * 2003-09-30 2005-03-31 International Business Machines Corporation Pre-anneal of cosi, to prevent formation of amorphous layer between ti-o-n and cosi
US20060012039A1 (en) * 2003-09-09 2006-01-19 Kim Sarah E Methods of processing thick ILD layers using spray coating or lamination for C4 wafer level thick metal integrated flow
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Cited By (30)

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US20040173882A1 (en) * 1997-06-19 2004-09-09 Tongbi Jiang Plastic lead frames for semiconductor devices and packages including same
US6979889B2 (en) 1997-06-19 2005-12-27 Micron Technology, Inc. Plastic lead frames for semiconductor devices
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EP1104702A2 (fr) 2001-06-06
EP1104702B1 (fr) 2006-05-03
CN1193874C (zh) 2005-03-23
KR20010070262A (ko) 2001-07-25
ATE324989T1 (de) 2006-06-15
DE60027672T2 (de) 2007-05-03
US6592971B2 (en) 2003-07-15
KR100732903B1 (ko) 2007-06-27
TW564222B (en) 2003-12-01
EP1104702A3 (fr) 2003-06-25
US20010003731A1 (en) 2001-06-14
DE60027672D1 (de) 2006-06-08
CN1302729A (zh) 2001-07-11

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