US20060076678A1 - Thick metal layer integrated process flow to improve power delivery and mechanical buffering - Google Patents
Thick metal layer integrated process flow to improve power delivery and mechanical buffering Download PDFInfo
- Publication number
- US20060076678A1 US20060076678A1 US11/281,709 US28170905A US2006076678A1 US 20060076678 A1 US20060076678 A1 US 20060076678A1 US 28170905 A US28170905 A US 28170905A US 2006076678 A1 US2006076678 A1 US 2006076678A1
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- layer
- metal layer
- forming
- bumps
- over
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- 238000000034 method Methods 0.000 title claims abstract description 35
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- 229910052802 copper Inorganic materials 0.000 claims description 14
- 229920001721 polyimide Polymers 0.000 claims description 14
- 238000001465 metallisation Methods 0.000 claims description 13
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- 239000010936 titanium Substances 0.000 description 4
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- 229910052719 titanium Inorganic materials 0.000 description 3
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- 230000009977 dual effect Effects 0.000 description 2
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- 230000000930 thermomechanical effect Effects 0.000 description 2
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- GXBYFVGCMPJVJX-UHFFFAOYSA-N Epoxybutene Chemical group C=CC1CO1 GXBYFVGCMPJVJX-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
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- 229910052759 nickel Inorganic materials 0.000 description 1
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- 238000000059 patterning Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
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- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
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- 229910052721 tungsten Inorganic materials 0.000 description 1
- 238000009827 uniform distribution Methods 0.000 description 1
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Definitions
- CMOS circuits usable in a microprocessor may have more transistors operating at lower voltages and higher frequencies. Since the resistance of transistors in each new generation may decrease more than voltage, and transistors may leak more current, CMOS circuits may demand more current. Higher current may be needed to pass from a substrate through a solder bump and a Controlled Collapse Chip Connection (C4) bump to a die. Each C4 bump may only be able to handle a limited amount of current due to electron migration failure. C4 bumps are known in the semiconductor industry as connections which provide current between a die and a substrate.
- FIG. 1A illustrates a structure which may be part of a microprocessor or other device.
- FIG. 1B illustrates a conventional interconnect structure and bumps of FIG. 1A .
- FIG. 1C illustrates a portion of the structure in FIG. 1A .
- FIG. 1D shows a simplified version of the thick metal interconnect structure shown in FIG. 8A .
- FIGS. 2-8B illustrate various stages of making an interconnect structure, which may be used in the structure of FIG. 1A .
- FIGS. 9A and 9B show two example processes of making the structures of FIGS. 2-8B .
- FIG. 10 illustrates an alternative embodiment of an interconnect structure, which is similar to the interconnect structure of FIG. 8A but with additional diffusion barriers.
- FIG. 11A shows an example of a process flow to make the interconnect structure of FIG. 10 .
- FIG. 11B shows an alternative process flow to make the interconnect structure of FIG. 10 .
- FIG. 12 shows a process flow to make an interconnect structure shown in FIG. 13F .
- FIGS. 13A-13F illustrate stages of an interconnect structure according to the process flow of FIG. 12 .
- FIG. 14 is a table of simulation parameters and simulation results for the interconnect structure of FIG. 8A compared to current and voltage values for the standard interconnect structure of FIG. 1B .
- FIG. 15A illustrates a relationship between C4 via resistance and C4 maximum current for the structures of FIGS. 1B and FIG. 8A .
- FIG. 15B illustrates a relationship between C4 resistance and voltage drop in millivolts for the structures of FIGS. 1B and FIG. 8A .
- FIG. 16 compares stress reduction of the standard interconnect structure of FIG. 1B with the structure of FIG. 8A , which has two thick metal layers.
- FIG. 1A illustrates a structure 150 which may be part of a microprocessor or some other device with integrated circuits.
- the structure 150 may include a motherboard 120 , pins 122 , socket connectors 124 , sockets 126 , a substrate 128 , solder bumps 130 , Controlled Collapse Chip Connection (C4) bumps 112 , an interconnect structure 100 , a die 133 (also called a wafer), a thermal interface material 132 and an integrated heat spreader 134 .
- the motherboard 120 may supply electrical current (power) through the pins 122 to the substrate 128 .
- the substrate 128 may supply current through the solder bumps 130 and C4 bumps 112 to the die 133 .
- the C4 bumps 112 may be coupled to the solder bumps 130 , which are attached to the substrate 128 .
- the C4 bumps 112 may be made of copper, tin, a lead-tin (Pb—Sn) compound, etc.
- FIG. 1B illustrates a conventional interconnect structure 100 of FIG. 1A .
- the interconnect structure 100 may be on the die 133 ( FIG. 1A ) as part of a backend interconnect of a microprocessor.
- the interconnect structure 100 in FIGS. 1A and 1B may include, a top metal layer 104 , a passivation layer 106 , a polyimide layer 108 , a ball limited metallization (BLM) layer 110 and C4 bumps 112 A- 112 B.
- “BLM” may also stand for base layer metallization.
- There may be several metal layers under the top metal layer 104 and there may be transistors under the metal layers.
- the C4 bumps 112 A- 112 B in FIGS. 1A and 1B may transfer current from the solder bumps 130 ( FIG. 1A ) to the top metal layer 104 ( FIG. 1B ).
- the top metal layer 104 may transfer current to the metal layers under the top metal layer 104 , which transfer current to underlying transistors in the die 133 . It may be desirable to limit or reduce a maximum current (Imax) through a specific C4 bump, such as the C4 bump 112 B, to the top metal layer 104 to increase bump reliability.
- a process flow is described to make a Controlled Collapse Chip Connection (C4) bump and interconnect structure with one or more integrated thick metal layers at a die or wafer level.
- the thick metal interconnect structure may be used in a backend interconnect of a microprocessor.
- the one or more integrated thick metal layers may improve power delivery and improve thermo-mechanical ability, i.e., reduce mechanical stress in low k ILD (inter-layer dielectric) and also at a die/package interface (solder bumps 130 and C4 bumps 112 in FIG. 1A ).
- higher resistance vias or higher resistance C4 bumps may be implemented in the thick metal interconnect structure 100 to provide better current spreading, i.e., improve uniform power distribution, and reduce maximum bump current (Imax).
- FIGS. 2-8B illustrate various stages of making bumps 230 and an interconnect structure 800 , which may be used in the structure 150 of FIG. 1A .
- FIGS. 9A and 9B show two example processes of making the structures of FIGS. 2-8B .
- the top metal layer 202 may be made of copper and may be about one micron thick in an embodiment.
- the top metal layer 202 may include an inter-layer dielectric (ILD).
- the ILD may be a conventional silicon dioxide or low K (dielectric constant less than 3, for example) material, such as carbon-doped oxide or low-K organic materials.
- a material with a low dielectric constant may be used to reduce signal delay times.
- a passivation layer 204 such as a nitride, may be deposited over the top metal layer 202 at 900 ( FIG. 9A ).
- the passivation layer 204 may be around 2,400 angstroms thick. Portions of the passivation layer 204 over the metal layer 202 may be removed to form vias 209 after polyimide patterning is completed.
- a polyimide layer 206 may be formed and patterned over the passivation layer 204 at 902 ( FIG. 9A ) and developed with vias 209 at 904 .
- the polyimide layer 206 may comprise a polymer-type material and may be about 3 to 5 microns thick. Instead of polyimide, other materials such as epoxy or BCB (benzocyclobutene) may be used to form the layer 206 .
- FIG. 3 illustrates the structure of FIG. 2 with a first ball limited metallization or base layer metallization (BLM) layer 208 deposited over the patterned and developed polyimide layer 206 at 906 .
- the first BLM layer 208 may be deposited in and along sidewalls of the vias 209 .
- the first BLM layer 208 may include a thin (e.g., 1000 Angstroms) titanium (Ti) layer, which may serve two functions: act as a diffusion barrier for a subsequent metal layer 212 (e.g., for copper) and provide adhesion for a metal seed layer (e.g., for copper).
- the first BLM layer 208 may further include a sputtered metal seed layer (e.g., 2000-Angstrom copper seed layer). The seed layer enables a subsequent metal layer 212 (e.g., copper) to be electroplated in FIG. 4 .
- Materials for a BLM layer may vary with a choice of metal layer.
- a photoresist layer 210 in FIG. 3 may be coated over the first BLM layer 208 at 908 and patterned at 910 for a first thick metal layer 212 in FIG. 4 .
- FIG. 4 illustrates the structure of FIG. 3 with a first thick metal layer 212 electroplated over the first BLM layer 208 at 912 .
- the first thick metal layer 212 may be copper (Cu) and may have a pre-determined thickness, such as 1 to 100 microns ( ⁇ m), preferably 10-50 ⁇ m.
- the first thick metal layer 212 may be deposited in the vias 209 over the first BLM layer 208 .
- the photoresist 210 of FIG. 3 may be stripped at 914 .
- FIG. 5 illustrates the structure of FIG. 4 with the first BLM layer 208 etched back to a top of polyimide 206 at 916 .
- “Ash” is a plasma process to remove photoresist.
- a first thick dielectric layer 214 may be deposited over the first thick metal layer 212 at 918 A.
- a thickness of a thick dielectric layer may vary with a thickness of a thick metal layer.
- the first thick dielectric layer 214 may be about 60 microns thick if the first metal layer is 40-50 micron thick.
- the first thick dielectric layer 214 may be polyimide, epoxy, BCB (benzocyclobutene) or other spin-on polymer or spin-on glass or even silicon oxide.
- the first dielectric layer 214 may be made of a self-planarizing, photo-definable polymer for flows in FIGS. 9A and 11A .
- FIG. 6 illustrates the structure of FIG. 5 with the first dielectric layer 214 photo-patterned and developed for vias 222 at 920 and 922 .
- the actions 906 - 922 in FIG. 9A described above may be repeated at 924 - 940 to form a second BLM layer 216 , a second thick metal layer 218 and a second thick dielectric layer 220 with patterned vias 222 .
- the second thick metal layer 218 may be copper and may be 10 to 50 micrometers thick.
- the second thick metal layer 218 may be orthogonal to the first thick metal layer, as described below with reference to FIG. 8B .
- the first thick metal layer 212 in FIG. 6 may be in electrical contact with the second thick metal layer 218 .
- the second thick dielectric layer 220 may be about 60 microns thick if the second thick metal layer is 40-50 microns thick.
- the second dielectric layer 220 may be polyimide, epoxy, BCB (benzocyclobutene) or other spin-on polymer or spin-on glass or even silicon oxide.
- the second dielectric layer 220 may be made of a self-planarizing, photo-definable polymer for flows in FIGS. 9A and 11A .
- FIG. 7 illustrates the structure of FIG. 6 with a third BLM layer 226 deposited over the second dielectric layer 220 and in the vias 222 at 942 .
- a photoresist 224 may be coated over the third BLM layer 226 at 944 and patterned for subsequently formed bumps 230 A, 230 B at 946 .
- FIG. 8A illustrates the structure of FIG. 7 with a metal, such as copper or a lead-tin (Pb—Sn) compound, plated in the vias 222 of FIG. 7 to form bumps 230 A- 230 B at 948 .
- the plating may be electroplating.
- the photoresist 224 in FIG. 7 may be stripped at 950 .
- the third BLM layer 226 may be etched back at 952 as shown in FIG. 8A .
- the third BLM layer 226 may comprise a first titanium layer (e.g., 1000 Angstroms), an aluminum layer, (e.g., 10,000 Angstroms), a second titanium layer (e.g., 1000 Angstroms), and a nickel layer (e.g., 4000 Angstroms).
- a first titanium layer e.g., 1000 Angstroms
- an aluminum layer e.g., 10,000 Angstroms
- a second titanium layer e.g., 1000 Angstroms
- a nickel layer e.g., 4000 Angstroms
- FIG. 8B illustrates a top view of the interconnect structure 800 of FIG. 8A .
- the second thick metal layer 218 in FIG. 8B may be orthogonal to the first thick metal layer 212 .
- the second thick metal layer 218 may be in electrical contact with at least two bumps 230 B, 230 D.
- a current driver i.e., transistor
- current 162 has to come through one C4 bump 112 A because the current 162 cannot be spread by more than one bump pitch.
- FIG. 1D shows a simplified version of the thick metal interconnect structure 800 shown in FIG. 8A .
- current 250 can be spread by more than one bump pitch.
- Current 250 from the substrate 128 may be spread to multiple solder bumps 130 A, 130 B and then multiple C4 bumps 112 A, 112 B.
- the current 250 may then be spread through one or more thick metal layers 218 to the top metal layer 202 , which is coupled to a high current demand driver 160 .
- current 250 may come from multiple bumps 230 A, 230 B instead of one bump 112 A ( FIG. 1C ), which can reduce current from one bump 230 .
- Bumps 230 which are farther away from the top metal layer 202 may contribute less current to the top metal layer 202 .
- FIG. 14 (described below) lists examples of maximum current values through the bumps 230 A- 230 D.
- a maximum current through each bump 230 A, 230 B in FIGS. 8A and 8B may be lower than the maximum current through each bump 112 A, 112 B in FIG. 1B because the bumps 230 A, 230 B in FIGS. 8A and 8B are coupled to thick metal layers 212 , 218 .
- the bumps 112 A, 112 B in FIG. 1B are not coupled to thick metal layers.
- Each bump 112 in FIG. 1B may have to carry a full desired current, such as 680 mA, to the top metal layer 104 .
- An alternative embodiment may have one thick metal layer instead of two thick metal layers 212 , 218 .
- a single thick metal layer may be coupled to a row of C4 bumps 230 .
- FIG. 9B illustrates an alternative process of making the interconnect structure 800 of FIG. 8A .
- Actions 900 - 916 in FIG. 9B may be similar to actions 900 - 916 in FIG. 9A .
- a non-photo-definable, self-planarizing polymer may be deposited as a first dielectric layer, e.g., an inter-layer dielectric (ILD), over the first thick metal layer 212 of FIG. 4 .
- a photoresist layer may be coated over the dielectric layer at 954 in FIG. 9B . Vias may be patterned in the photoresist at 956 .
- the first dielectric layer may be dry etched at 958 .
- the photoresist may be stripped at 960 .
- ILD inter-layer dielectric
- Actions 924 - 934 in FIG. 9B may be similar to actions 924 - 934 in FIG. 9A .
- a non-photo-definable, self-planarizing polymer may be deposited as a second dielectric layer, e.g., an inter-layer dielectric (ILD), over a second thick metal layer, which may be similar to the second thick metal layer 216 of FIG. 6 .
- a photoresist layer may be coated over the second dielectric layer at 964 . Vias may be patterned in the photoresist at 966 .
- the second dielectric layer may be dry etched at 968 .
- the photoresist may be stripped at 970 .
- Actions 942 - 952 in FIG. 9B may be similar to actions 942 - 952 in FIG. 9A .
- the process of FIG. 9B may produce substantially the same structure 800 ( FIG. 8A ) as the process of FIG. 9A .
- FIG. 10 illustrates an alternative embodiment of a interconnect structure 1000 , which is similar to the interconnect structure 800 of FIG. 8A but with additional diffusion barriers 1002 , 1004 .
- the diffusion barriers 1002 , 1004 are intended to prevent the metal layers 212 , 218 (e.g., copper) from diffusing into the dielectric layers 214 , 220 .
- the diffusion barriers 1002 , 1004 may be formed by electroless (EL) cobalt plating over and on the sides of the metal layers 212 , 218 , which is described below with reference to FIGS. 11A, 11B and 12 .
- EL electroless
- FIG. 11A shows an example of a process flow to make the interconnect structure 1000 of FIG. 10 .
- Actions 900 - 952 in FIG. 11A may be similar to actions 900 - 952 in FIG. 9A .
- Diffusion barriers 1002 , 1004 ( FIG. 10 ) may be electroless (EL) plated at 1100 and 1102 in FIG. 11A .
- FIG. 11B shows an alternative process flow to make the interconnect structure 1000 of FIG. 10 .
- Actions 900 - 952 in FIG. 11 B may be similar to actions 900 - 952 in FIG. 9B .
- Diffusion barriers 1002 , 1004 ( FIG. 10 ) may be electroless (EL) plated at 1100 and 1102 in FIG. 11B .
- FIG. 12 shows a process flow to make an interconnect structure 1350 shown in FIG. 13F .
- FIGS. 13A-13F illustrate stages of the interconnect structure 1350 according to the process flow of FIG. 12 .
- the interconnect structure 1350 of FIG. 13F may have copper diffusion barriers like the diffusion barriers 1002 , 1004 of the interconnect structure 1000 of FIG. 10 .
- a first passivation layer 1300 e.g., nitride, in FIG. 13A may be deposited on a top metal layer 202 at 900 in FIG. 12 .
- a first thick dielectric 1302 e.g., an ILD, may be deposited over the first passivation layer 1300 at 1200 in FIG. 12 .
- the thickness of the first thick dielectric layer depends on thick metal layer thickness. As an example, the first thick dielectric layer 1302 may be about 60 microns thick.
- FIG. 13B shows a dual damascene process.
- a first photoresist may be coated over the first thick dielectric 1302 at 1202 .
- Vias 1304 may be patterned in the first thick dielectric 1302 in FIG. 13B at 1204 .
- the first photoresist may then be removed.
- a second photoresist may be coated over the first thick dielectric 1302 at 1206 .
- the second photoresist may pattern trenches 1306 ( FIG. 13B ) at 1208 .
- the second photoresist may then be removed.
- a first BLM layer 1308 (i.e., barrier seed layer) in FIG. 13C may be deposited in the vias 1304 and trenches 1306 at 1210 .
- a first thick metal layer 1310 (e.g., copper) may be plated over the first BLM layer 1308 in vias 1304 and trenches 1306 at 1212
- the first thick metal layer 1310 may be polished in FIG. 13D at 1214 by, for example, chemical mechanical polishing (CMP).
- CMP chemical mechanical polishing
- Actions 1216 - 1232 of FIG. 12 may be similar to the actions 900 - 1214 of FIG. 12 described above. Actions 1216 - 1232 may form a second passivation layer 1311 , e.g., nitride, a second dielectric layer 1312 , a second BLM layer 1314 and a second thick metal layer 1316 in FIG. 13E .
- a second passivation layer 1311 e.g., nitride
- a second dielectric layer 1312 e.g., a second dielectric layer 1312
- a second BLM layer 1314 e.g., a second BLM layer 1314
- a third passivation layer 1318 may be formed over the second thick metal layer 1316 in FIG. 13F at 1234 .
- a polyimide layer 1320 may be patterned and developed over the third passivation layer 1318 at 1236 .
- a third BLM layer 1322 may be deposited over the polyimide layer 1320 at 1238 .
- Another photoresist may be coated over the third BLM layer 1322 at 1240 .
- Bumps 1324 may be patterned and plated in spaces left by the photoresist at 1242 and 1244 .
- the photoresist around the bumps 1324 may be stripped at 1246 . Then the third BLM layer 1322 may be etched at 1248 .
- FIG. 14 is a table of simulation parameters and simulation results for the interconnect structure 800 of FIG. 8A (with two thick metal layers 212 , 218 ) compared to maximum current and voltage drop for the standard interconnect structure 100 of FIG. 1B .
- the standard interconnect structure 100 of FIG. 1 with no thick metal layers, is represented by row 1310 in FIG. 14 .
- the simulation parameters in FIG. 14 include (a) thickness and (b) width of the two thick metal layers 212 , 218 in FIGS. 8A and 10 , and (c) resistance of the vias 222 ( FIGS. 7-8A ) between the bumps 230 and the second thick metal layer 218 .
- Four sets 1400 - 1406 of parameters and results are shown in FIG. 14 .
- the four sets 1400 - 1406 may have lower Imax current per bump than the standard interconnect structure 100 (represented by row 1410 in FIG. 14 ) because current needed by drivers (i.e., transistors under the top metal layer 202 ) may be obtained from multiple bumps 230 and the two thick metal layers 212 , 218 ( FIG. 8A ).
- the thick metal layers 212 , 218 may reduce Imax and improve power delivery.
- the third set 1404 has a higher via resistance (70 mOhms) than the first set 1400 .
- the third set 1404 has a lower Imax (370 mA) and a higher voltage drop (49 mV) than the first set 1400 .
- Imax a maximum current per bump
- Imax may be improved by about 22 to 35%, depending on metal thickness. Thicker metal may provide better Imax.
- Increasing resistance of the via 222 ( FIG. 8A ) may improve Imax by 46%.
- the vias 222 of FIG. 8A between the bump 230 and the second thick metal layer 218 may be made smaller. Resistance increases if area decreases. Alternatively or additionally, the second BLM layer thickness may be increased. Also, the vias 222 or bump itself may be deposited with materials that have a higher resistance than copper (Cu), such as tungsten (W).
- Cu copper
- W tungsten
- FIG. 15A illustrates a relationship between C4 via resistance and C4 maximum current (Imax) for the structures of FIGS. 1B and FIG. 8A . As C4 via resistance increases, C4 maximum current (Imax) decreases.
- the one or more integrated thick metal layers may improve thermo-mechanical ability, i.e., reduce mechanical stress in low k ILD and also at a die/package interface, e.g., solder bumps 130 and C4 bumps 112 in FIG. 1A .
- FIG. 16 compares stress impact on low k (dielectric constant) ILD layer (a) with the standard interconnect structure 100 of FIG. 1B and (b) with the proposed structure 800 of FIG. 8A , which has two thick metal layers 212 , 218 .
- the bump structure 800 of FIG. 8A with two 45-micrometer thick metal layers 212 , 218 may have 50% less stress on low k layer such as carbon-doped oxide (CDO) than the standard interconnect structure 100 of FIG. 1B .
- CDO carbon-doped oxide
Abstract
A process flow to make an interconnect structure with one or more thick metal layers under Controlled Collapse Chip Connection (C4) bumps at a die or wafer level. The interconnect structure may be used in a backend interconnect of a microprocessor. The one or more integrated thick metal layers may improve power delivery and reduce mechanical stress to a die at a die/package interface.
Description
- This application is a divisional application of and claims priority to U.S. patent application Ser. No. 10/659,044, filed Sep. 9, 2003.
- Each generation of complementary metal oxide semiconductor (CMOS) circuits usable in a microprocessor may have more transistors operating at lower voltages and higher frequencies. Since the resistance of transistors in each new generation may decrease more than voltage, and transistors may leak more current, CMOS circuits may demand more current. Higher current may be needed to pass from a substrate through a solder bump and a Controlled Collapse Chip Connection (C4) bump to a die. Each C4 bump may only be able to handle a limited amount of current due to electron migration failure. C4 bumps are known in the semiconductor industry as connections which provide current between a die and a substrate.
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FIG. 1A illustrates a structure which may be part of a microprocessor or other device. -
FIG. 1B illustrates a conventional interconnect structure and bumps ofFIG. 1A . -
FIG. 1C illustrates a portion of the structure inFIG. 1A . -
FIG. 1D shows a simplified version of the thick metal interconnect structure shown inFIG. 8A . -
FIGS. 2-8B illustrate various stages of making an interconnect structure, which may be used in the structure ofFIG. 1A . -
FIGS. 9A and 9B show two example processes of making the structures ofFIGS. 2-8B . -
FIG. 10 illustrates an alternative embodiment of an interconnect structure, which is similar to the interconnect structure ofFIG. 8A but with additional diffusion barriers. -
FIG. 11A shows an example of a process flow to make the interconnect structure ofFIG. 10 . -
FIG. 11B shows an alternative process flow to make the interconnect structure ofFIG. 10 . -
FIG. 12 shows a process flow to make an interconnect structure shown inFIG. 13F . -
FIGS. 13A-13F illustrate stages of an interconnect structure according to the process flow ofFIG. 12 . -
FIG. 14 is a table of simulation parameters and simulation results for the interconnect structure ofFIG. 8A compared to current and voltage values for the standard interconnect structure ofFIG. 1B . -
FIG. 15A illustrates a relationship between C4 via resistance and C4 maximum current for the structures ofFIGS. 1B andFIG. 8A . -
FIG. 15B illustrates a relationship between C4 resistance and voltage drop in millivolts for the structures ofFIGS. 1B andFIG. 8A . -
FIG. 16 compares stress reduction of the standard interconnect structure ofFIG. 1B with the structure ofFIG. 8A , which has two thick metal layers. -
FIG. 1A illustrates astructure 150 which may be part of a microprocessor or some other device with integrated circuits. Thestructure 150 may include amotherboard 120,pins 122,socket connectors 124,sockets 126, asubstrate 128,solder bumps 130, Controlled Collapse Chip Connection (C4)bumps 112, aninterconnect structure 100, a die 133 (also called a wafer), athermal interface material 132 and an integratedheat spreader 134. Themotherboard 120 may supply electrical current (power) through thepins 122 to thesubstrate 128. Thesubstrate 128 may supply current through thesolder bumps 130 andC4 bumps 112 to the die 133. TheC4 bumps 112 may be coupled to thesolder bumps 130, which are attached to thesubstrate 128. TheC4 bumps 112 may be made of copper, tin, a lead-tin (Pb—Sn) compound, etc. -
FIG. 1B illustrates aconventional interconnect structure 100 ofFIG. 1A . The interconnect structure 100 (FIG. 1B ) may be on the die 133 (FIG. 1A ) as part of a backend interconnect of a microprocessor. Theinterconnect structure 100 inFIGS. 1A and 1B may include, atop metal layer 104, apassivation layer 106, apolyimide layer 108, a ball limited metallization (BLM)layer 110 andC4 bumps 112A-112B. “BLM” may also stand for base layer metallization. There may be several metal layers under thetop metal layer 104, and there may be transistors under the metal layers. - The C4 bumps 112A-112B in
FIGS. 1A and 1B may transfer current from the solder bumps 130 (FIG. 1A ) to the top metal layer 104 (FIG. 1B ). Thetop metal layer 104 may transfer current to the metal layers under thetop metal layer 104, which transfer current to underlying transistors in thedie 133. It may be desirable to limit or reduce a maximum current (Imax) through a specific C4 bump, such as theC4 bump 112B, to thetop metal layer 104 to increase bump reliability. - A process flow is described to make a Controlled Collapse Chip Connection (C4) bump and interconnect structure with one or more integrated thick metal layers at a die or wafer level. The thick metal interconnect structure may be used in a backend interconnect of a microprocessor. The one or more integrated thick metal layers may improve power delivery and improve thermo-mechanical ability, i.e., reduce mechanical stress in low k ILD (inter-layer dielectric) and also at a die/package interface (solder bumps 130 and C4 bumps 112 in
FIG. 1A ). - In addition, higher resistance vias or higher resistance C4 bumps may be implemented in the thick
metal interconnect structure 100 to provide better current spreading, i.e., improve uniform power distribution, and reduce maximum bump current (Imax). -
FIGS. 2-8B illustrate various stages of makingbumps 230 and aninterconnect structure 800, which may be used in thestructure 150 ofFIG. 1A .FIGS. 9A and 9B show two example processes of making the structures ofFIGS. 2-8B . - In
FIG. 2 , thetop metal layer 202 may be made of copper and may be about one micron thick in an embodiment. Thetop metal layer 202 may include an inter-layer dielectric (ILD). The ILD may be a conventional silicon dioxide or low K (dielectric constant less than 3, for example) material, such as carbon-doped oxide or low-K organic materials. A material with a low dielectric constant may be used to reduce signal delay times. - A
passivation layer 204, such as a nitride, may be deposited over thetop metal layer 202 at 900 (FIG. 9A ). Thepassivation layer 204 may be around 2,400 angstroms thick. Portions of thepassivation layer 204 over themetal layer 202 may be removed to form vias 209 after polyimide patterning is completed. - A
polyimide layer 206 may be formed and patterned over thepassivation layer 204 at 902 (FIG. 9A ) and developed withvias 209 at 904. Thepolyimide layer 206 may comprise a polymer-type material and may be about 3 to 5 microns thick. Instead of polyimide, other materials such as epoxy or BCB (benzocyclobutene) may be used to form thelayer 206. -
FIG. 3 illustrates the structure ofFIG. 2 with a first ball limited metallization or base layer metallization (BLM)layer 208 deposited over the patterned anddeveloped polyimide layer 206 at 906. Thefirst BLM layer 208 may be deposited in and along sidewalls of thevias 209. Thefirst BLM layer 208 may include a thin (e.g., 1000 Angstroms) titanium (Ti) layer, which may serve two functions: act as a diffusion barrier for a subsequent metal layer 212 (e.g., for copper) and provide adhesion for a metal seed layer (e.g., for copper). Thefirst BLM layer 208 may further include a sputtered metal seed layer (e.g., 2000-Angstrom copper seed layer). The seed layer enables a subsequent metal layer 212 (e.g., copper) to be electroplated inFIG. 4 . Materials for a BLM layer may vary with a choice of metal layer. - A
photoresist layer 210 inFIG. 3 may be coated over thefirst BLM layer 208 at 908 and patterned at 910 for a firstthick metal layer 212 inFIG. 4 . -
FIG. 4 illustrates the structure ofFIG. 3 with a firstthick metal layer 212 electroplated over thefirst BLM layer 208 at 912. The firstthick metal layer 212 may be copper (Cu) and may have a pre-determined thickness, such as 1 to 100 microns (μm), preferably 10-50 μm. The firstthick metal layer 212 may be deposited in thevias 209 over thefirst BLM layer 208. Thephotoresist 210 ofFIG. 3 may be stripped at 914. -
FIG. 5 illustrates the structure ofFIG. 4 with thefirst BLM layer 208 etched back to a top ofpolyimide 206 at 916. “Ash” is a plasma process to remove photoresist. A firstthick dielectric layer 214 may be deposited over the firstthick metal layer 212 at 918A. A thickness of a thick dielectric layer may vary with a thickness of a thick metal layer. As an example, the firstthick dielectric layer 214 may be about 60 microns thick if the first metal layer is 40-50 micron thick. The firstthick dielectric layer 214 may be polyimide, epoxy, BCB (benzocyclobutene) or other spin-on polymer or spin-on glass or even silicon oxide. Also, thefirst dielectric layer 214 may be made of a self-planarizing, photo-definable polymer for flows inFIGS. 9A and 11A . -
FIG. 6 illustrates the structure ofFIG. 5 with thefirst dielectric layer 214 photo-patterned and developed forvias 222 at 920 and 922. The actions 906-922 inFIG. 9A described above may be repeated at 924-940 to form asecond BLM layer 216, a secondthick metal layer 218 and a secondthick dielectric layer 220 with patternedvias 222. - The second
thick metal layer 218 may be copper and may be 10 to 50 micrometers thick. The secondthick metal layer 218 may be orthogonal to the first thick metal layer, as described below with reference toFIG. 8B . The firstthick metal layer 212 inFIG. 6 may be in electrical contact with the secondthick metal layer 218. As an example, the secondthick dielectric layer 220 may be about 60 microns thick if the second thick metal layer is 40-50 microns thick. Thesecond dielectric layer 220 may be polyimide, epoxy, BCB (benzocyclobutene) or other spin-on polymer or spin-on glass or even silicon oxide. Also, thesecond dielectric layer 220 may be made of a self-planarizing, photo-definable polymer for flows inFIGS. 9A and 11A . -
FIG. 7 illustrates the structure ofFIG. 6 with athird BLM layer 226 deposited over thesecond dielectric layer 220 and in thevias 222 at 942. Aphotoresist 224 may be coated over thethird BLM layer 226 at 944 and patterned for subsequently formedbumps -
FIG. 8A illustrates the structure ofFIG. 7 with a metal, such as copper or a lead-tin (Pb—Sn) compound, plated in thevias 222 ofFIG. 7 to formbumps 230A-230B at 948. The plating may be electroplating. Thephotoresist 224 inFIG. 7 may be stripped at 950. Thethird BLM layer 226 may be etched back at 952 as shown inFIG. 8A . - If the
bumps 230A-230B are made of a lead-tin (Pb—Sn) compound, thethird BLM layer 226 may comprise a first titanium layer (e.g., 1000 Angstroms), an aluminum layer, (e.g., 10,000 Angstroms), a second titanium layer (e.g., 1000 Angstroms), and a nickel layer (e.g., 4000 Angstroms). -
FIG. 8B illustrates a top view of theinterconnect structure 800 ofFIG. 8A . The secondthick metal layer 218 inFIG. 8B may be orthogonal to the firstthick metal layer 212. The secondthick metal layer 218 may be in electrical contact with at least twobumps - As shown in
FIG. 1C , if a current driver (i.e., transistor) 160 demands a high current, current 162 has to come through oneC4 bump 112A because the current 162 cannot be spread by more than one bump pitch. -
FIG. 1D shows a simplified version of the thickmetal interconnect structure 800 shown inFIG. 8A . InFIG. 1D , current 250 can be spread by more than one bump pitch. Current 250 from thesubstrate 128 may be spread to multiple solder bumps 130A, 130B and then multiple C4 bumps 112A, 112B. The current 250 may then be spread through one or morethick metal layers 218 to thetop metal layer 202, which is coupled to a highcurrent demand driver 160. In this way, current 250 may come frommultiple bumps bump 112A (FIG. 1C ), which can reduce current from onebump 230. -
Bumps 230 which are farther away from thetop metal layer 202 may contribute less current to thetop metal layer 202. The closer thebump 230 is to thetop metal layer 202, the more current thatbump 230 may contribute. -
FIG. 14 (described below) lists examples of maximum current values through thebumps 230A-230D. A maximum current through eachbump FIGS. 8A and 8B may be lower than the maximum current through eachbump FIG. 1B because thebumps FIGS. 8A and 8B are coupled tothick metal layers bumps FIG. 1B are not coupled to thick metal layers. Eachbump 112 inFIG. 1B may have to carry a full desired current, such as 680 mA, to thetop metal layer 104. - An alternative embodiment may have one thick metal layer instead of two
thick metal layers structure 800 inFIG. 8A , where each thick metal layer may be coupled to a row of C4 bumps 230. -
FIG. 9B illustrates an alternative process of making theinterconnect structure 800 ofFIG. 8A . Actions 900-916 inFIG. 9B may be similar to actions 900-916 inFIG. 9A . At 918B inFIG. 9B , a non-photo-definable, self-planarizing polymer may be deposited as a first dielectric layer, e.g., an inter-layer dielectric (ILD), over the firstthick metal layer 212 ofFIG. 4 . A photoresist layer may be coated over the dielectric layer at 954 inFIG. 9B . Vias may be patterned in the photoresist at 956. The first dielectric layer may be dry etched at 958. The photoresist may be stripped at 960. - Actions 924-934 in
FIG. 9B may be similar to actions 924-934 inFIG. 9A . At 962 inFIG. 9B , a non-photo-definable, self-planarizing polymer may be deposited as a second dielectric layer, e.g., an inter-layer dielectric (ILD), over a second thick metal layer, which may be similar to the secondthick metal layer 216 ofFIG. 6 . A photoresist layer may be coated over the second dielectric layer at 964. Vias may be patterned in the photoresist at 966. The second dielectric layer may be dry etched at 968. The photoresist may be stripped at 970. Actions 942-952 inFIG. 9B may be similar to actions 942-952 inFIG. 9A . The process ofFIG. 9B may produce substantially the same structure 800 (FIG. 8A ) as the process ofFIG. 9A . -
FIG. 10 illustrates an alternative embodiment of ainterconnect structure 1000, which is similar to theinterconnect structure 800 ofFIG. 8A but withadditional diffusion barriers 1002, 1004. Thediffusion barriers 1002, 1004 are intended to prevent the metal layers 212, 218 (e.g., copper) from diffusing into thedielectric layers diffusion barriers 1002, 1004 may be formed by electroless (EL) cobalt plating over and on the sides of the metal layers 212, 218, which is described below with reference toFIGS. 11A, 11B and 12. -
FIG. 11A shows an example of a process flow to make theinterconnect structure 1000 ofFIG. 10 . Actions 900-952 inFIG. 11A may be similar to actions 900-952 inFIG. 9A . Diffusion barriers 1002, 1004 (FIG. 10 ) may be electroless (EL) plated at 1100 and 1102 inFIG. 11A . -
FIG. 11B shows an alternative process flow to make theinterconnect structure 1000 ofFIG. 10 . Actions 900-952 in FIG. 11B may be similar to actions 900-952 inFIG. 9B . Diffusion barriers 1002, 1004 (FIG. 10 ) may be electroless (EL) plated at 1100 and 1102 inFIG. 11B . -
FIG. 12 shows a process flow to make aninterconnect structure 1350 shown inFIG. 13F .FIGS. 13A-13F illustrate stages of theinterconnect structure 1350 according to the process flow ofFIG. 12 . Theinterconnect structure 1350 ofFIG. 13F may have copper diffusion barriers like thediffusion barriers 1002, 1004 of theinterconnect structure 1000 ofFIG. 10 . - A
first passivation layer 1300, e.g., nitride, inFIG. 13A may be deposited on atop metal layer 202 at 900 inFIG. 12 . A firstthick dielectric 1302, e.g., an ILD, may be deposited over thefirst passivation layer 1300 at 1200 inFIG. 12 . The thickness of the first thick dielectric layer depends on thick metal layer thickness. As an example, the firstthick dielectric layer 1302 may be about 60 microns thick. - Single or dual damascene process may be used depending on the thick metal thickness.
FIG. 13B shows a dual damascene process. A first photoresist may be coated over the firstthick dielectric 1302 at 1202.Vias 1304 may be patterned in the firstthick dielectric 1302 inFIG. 13B at 1204. The first photoresist may then be removed. A second photoresist may be coated over the firstthick dielectric 1302 at 1206. The second photoresist may pattern trenches 1306 (FIG. 13B ) at 1208. The second photoresist may then be removed. - A first BLM layer 1308 (i.e., barrier seed layer) in
FIG. 13C may be deposited in thevias 1304 andtrenches 1306 at 1210. A first thick metal layer 1310 (e.g., copper) may be plated over thefirst BLM layer 1308 invias 1304 andtrenches 1306 at 1212 - The first
thick metal layer 1310 may be polished inFIG. 13D at 1214 by, for example, chemical mechanical polishing (CMP). - Actions 1216-1232 of
FIG. 12 may be similar to the actions 900-1214 ofFIG. 12 described above. Actions 1216-1232 may form asecond passivation layer 1311, e.g., nitride, asecond dielectric layer 1312, asecond BLM layer 1314 and a secondthick metal layer 1316 inFIG. 13E . - A
third passivation layer 1318, e.g., nitride, may be formed over the secondthick metal layer 1316 inFIG. 13F at 1234. Apolyimide layer 1320 may be patterned and developed over thethird passivation layer 1318 at 1236. Athird BLM layer 1322 may be deposited over thepolyimide layer 1320 at 1238. Another photoresist may be coated over thethird BLM layer 1322 at 1240.Bumps 1324 may be patterned and plated in spaces left by the photoresist at 1242 and 1244. - The photoresist around the
bumps 1324 may be stripped at 1246. Then thethird BLM layer 1322 may be etched at 1248. -
FIG. 14 is a table of simulation parameters and simulation results for theinterconnect structure 800 ofFIG. 8A (with twothick metal layers 212, 218) compared to maximum current and voltage drop for thestandard interconnect structure 100 ofFIG. 1B . Thestandard interconnect structure 100 ofFIG. 1 , with no thick metal layers, is represented byrow 1310 inFIG. 14 . Thestandard interconnect structure 100 ofFIG. 1 may have, for example, a maximum current (Imax) through thebump 112 of 680 mA, and a voltage drop (V=IR) from thebump 112 to thetop metal layer 104 of 29 mV. - The simulation parameters in
FIG. 14 include (a) thickness and (b) width of the twothick metal layers FIGS. 8A and 10 , and (c) resistance of the vias 222 (FIGS. 7-8A ) between thebumps 230 and the secondthick metal layer 218. Four sets 1400-1406 of parameters and results are shown inFIG. 14 . The four sets 1400-1406 may have lower Imax current per bump than the standard interconnect structure 100 (represented byrow 1410 inFIG. 14 ) because current needed by drivers (i.e., transistors under the top metal layer 202) may be obtained frommultiple bumps 230 and the twothick metal layers 212, 218 (FIG. 8A ). Thus, thethick metal layers - The
third set 1404 has a higher via resistance (70 mOhms) than thefirst set 1400. Thethird set 1404 has a lower Imax (370 mA) and a higher voltage drop (49 mV) than thefirst set 1400. - More uniform distribution of current through multiple
adjacent bumps 230 may reduce a maximum current per bump (Imax) by 46%. With a thick metal layer integrated flow, Imax may be improved by about 22 to 35%, depending on metal thickness. Thicker metal may provide better Imax. Increasing resistance of the via 222 (FIG. 8A ) may improve Imax by 46%. - To increase via resistance, the
vias 222 ofFIG. 8A between thebump 230 and the secondthick metal layer 218 may be made smaller. Resistance increases if area decreases. Alternatively or additionally, the second BLM layer thickness may be increased. Also, thevias 222 or bump itself may be deposited with materials that have a higher resistance than copper (Cu), such as tungsten (W). -
FIG. 15A illustrates a relationship between C4 via resistance and C4 maximum current (Imax) for the structures ofFIGS. 1B andFIG. 8A . As C4 via resistance increases, C4 maximum current (Imax) decreases. -
FIG. 15B illustrates a relationship between C4 resistance and voltage drop (V=IR in millivolts) for the structures ofFIGS. 1B andFIG. 8A . As C4 resistance increases, V=IR for the via increases. - As stated above, the one or more integrated thick metal layers (e.g., 212, 218 in
FIG. 8A ) may improve thermo-mechanical ability, i.e., reduce mechanical stress in low k ILD and also at a die/package interface, e.g., solder bumps 130 and C4 bumps 112 inFIG. 1A . -
FIG. 16 compares stress impact on low k (dielectric constant) ILD layer (a) with thestandard interconnect structure 100 ofFIG. 1B and (b) with the proposedstructure 800 ofFIG. 8A , which has twothick metal layers bump structure 800 ofFIG. 8A with two 45-micrometerthick metal layers standard interconnect structure 100 ofFIG. 1B . - A number of embodiments have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the application. Accordingly, other embodiments are within the scope of the following claims.
Claims (16)
1. A method comprising:
forming a first metal layer over a first base layer metallization, the first base layer metallization contacting a top metal layer of an integrated circuit die;
forming a first dielectric layer over the first metal layer;
forming vias in the first dielectric layer;
forming a second base layer metallization in the vias of the first dielectric layer; and
forming bumps over the second base layer metallization, the top metal layer being coupled to the first metal layer, the first metal layer being adapted to transfer current from the bumps to the top metal layer of the integrated circuit die.
2. The method of claim 1 , wherein the first and second bumps are Controlled Collapse Chip Connection bumps.
3. The method of claim 1 , wherein the first metal layer is about 10 to 50 microns thick.
4. The method of claim 1 , wherein said forming the first metal layer over the first base layer metallization comprises electroplating copper to the first base layer metallization.
5. The method of claim 1 , further comprising attaching the bumps to solder bumps of a substrate.
6. The method of claim 1 , further comprising forming the first base layer metallization in vias of a polyimide layer.
7. The method of claim 1 , further comprising forming the first base layer metallization in vias of a benzocyclobutene layer.
8. The method of claim 1 , further comprising forming the first base layer metallization in vias of an epoxy layer.
9. The method of claim 1 , wherein said forming a first dielectric layer uses a self-planarizing, photo-definable polymer.
10. The method of claim 1 , wherein said forming a first dielectric layer uses a self-planarizing, non-photo-definable polymer.
11. The method of claim 1 , further comprising forming a second metal layer after forming the first metal layer and before forming the bumps, the second metal layer being coupled to the at least two bumps and the first metal layer, the second metal layer adapted to transfer current from the at least two bumps to the first metal layer, which is adapted to transfer current to the top metal layer of the integrated circuit die.
12. The method of claim 11 , wherein the second metal layer is orthogonal to the first metal layer.
13. The method of claim 1 , further comprising forming diffusion barriers over and on sides of the first metal layer.
14. A method comprising:
forming a first metal layer over a first barrier seed layer, the first barrier seed layer contacting a top metal layer of an integrated circuit die;
forming a passivation layer over the first metal layer;
forming a polyimide layer over the passivation layer;
developing vias in the polyimide layer;
forming a seed barrier layer in the vias; and
forming first and second bumps over the seed barrier layer.
15. The method of claim 14 , wherein the first metal layer is 10-50 μm thick.
16. The method of claim 14 , further comprising:
forming a dielectric layer over a passivation layer over the top metal layer of the integrated circuit die;
developing vias in the dielectric layer; and
forming the first barrier seed layer in the vias and over the dielectric layer.
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Also Published As
Publication number | Publication date |
---|---|
US20050051904A1 (en) | 2005-03-10 |
TW200523986A (en) | 2005-07-16 |
US6977435B2 (en) | 2005-12-20 |
US20050051894A1 (en) | 2005-03-10 |
TWI299510B (en) | 2008-08-01 |
CN1846307B (en) | 2011-05-18 |
DE112004001654T5 (en) | 2013-10-10 |
US6943440B2 (en) | 2005-09-13 |
CN1846307A (en) | 2006-10-11 |
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