US6072242A - Contact structure of semiconductor memory device for reducing contact related defect and contact resistance and method for forming the same - Google Patents

Contact structure of semiconductor memory device for reducing contact related defect and contact resistance and method for forming the same Download PDF

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Publication number
US6072242A
US6072242A US09/209,649 US20964998A US6072242A US 6072242 A US6072242 A US 6072242A US 20964998 A US20964998 A US 20964998A US 6072242 A US6072242 A US 6072242A
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contact
memory device
semiconductor memory
conductive layer
opening
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US09/209,649
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English (en)
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Jin-Yeong Son
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Mosaid Technologies Inc
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Samsung Electronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
    • G03F1/72—Repair or correction of mask defects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a semiconductor memory device and a method for fabricating the same, and more particularly, to a contact structure for a semiconductor memory device that reduces contact defects and contact resistance and a method for forming the same.
  • DRAM dynamic random access memory
  • a semiconductor memory device such as dynamic random access memory (DRAM) devices having a plurality of memory cells each consisting of one access transistor and one storage capacitor
  • DRAM dynamic random access memory
  • a reduction in the size of the semiconductor device leads to a reduction in operating voltage. For instance, a power supply voltage of 1.2 V has been proposed for a 256-Megabit DRAM whereas a power supply voltage of 1 V or less has been proposed for a 1-Gigabit DRAM.
  • a technique for reducing a contact resistance by forming at least two through openings has been proposed.
  • the space between the adjacent through openings is narrow due to the reduction of the semiconductor device. If the through openings are overlapped, a peak point P may be generated as shown in FIG. 1.
  • openings C1 and C2 passing through an interlayer insulation layer 30 are formed on a lower conductive layer 20 on a substrate 10.
  • the through opening C1 has an etched surface 31 formed by isotropic etching at an upper side and has an etched surface 33 formed by anisotropic etching at a lower side.
  • the opening C2 has an etched surface 32 formed by isotropic etching at an upper side and has an etched surface 34 formed by anisotropic etching at a lower side.
  • an isotropic etching of the insulation layer 30 is necessary to form the surfaces 31 and 32.
  • the peak point P is produced by excessive anisotropic etching of the insulation layer 30.
  • a contact is made by filling the openings C1 and C2 with a metal contact plug, contact related defects, for example, poor contact, migration, and the like, can occur during subsequent processes. Moreover, since the lower contact area of the contact plug is considerably smaller in size than the upper contact area, a contact resistance problem arises.
  • a photo masking process for forming the contact has been proposed as indicated in FIG. 2.
  • This technique has a scheme for forming one through opening having the size corresponding to the total size of the adjacent through openings on an interlayer insulation layer.
  • a mask 50 having a rectangular pattern 52 formed on a glass substrate 51 coated with chromium is provided to form a pattern on a photoresist 40.
  • the size of the rectangular pattern 52 is determined by considering the total size of the two through openings.
  • a light beam such as a laser beam or ultraviolet ray pass through the pattern 52 of the mask 50, reaching the upper side of the photoresist 40. Further, the light beam is reflected at the surface of the glass substrate 51, not passing through it. Therefore, an exposed part 41 is distinguished from an unexposed part 42. Only subsequent processes develop the exposed part 41.
  • one contact hole is formed as the through opening on an insulation layer 30 of an oxide layer. If the remaining unexposed part 42 of the photoresist 40 is removed and the through opening is filled with tungsten, there is formed the contact plug for contacting a partial surface of a lower conductive layer 20 with an upper conductive layer to be formed on the insulation layer 30.
  • the plane of the contact plug appears as an elliptical shape instead of circular in shape, the contact area is reduced. In other words, the size of the opening is smaller than the total size of the two openings. This is because the unexposed part 41 is formed as the elliptical shape due to a diffraction of light and an interference phenomenon during an exposing process. Consequently, the contact area is reduced by the pattern of the rectangular shape, and it is difficult to provide a good ohmic contact at lower power supply voltages. Hence, it is necessary to both increase the contact area and reduce the contact related defects.
  • a semiconductor memory device comprises a conductive layer formed on a semiconductor substrate and an insulation layer formed on the conductive layer. An opening is formed through a portion of the insulation layer on a portion of the conductive layer, the opening having a bilobate shape. A contact is formed in the opening.
  • the semiconductor memory device further comprises an upper surface of the conductive layer that is exposed by the opening, the upper surface of the conductive layer having a bilobate shape with a first and a second round portions connected by a bridge portion.
  • a photomask for manufacturing semiconductor devices comprises a first portion, a second portion, and a bridge portion connecting the first and second portions together.
  • the first and second portions are substantially square and the bridge portion is about 0.3 ⁇ m long.
  • a photomask for manufacturing semiconductor devices comprises a first substantially square portion, a second substantially square portion, and a predetermined distance between the first and the second portion.
  • the predetermined distance is about 0.3 ⁇ m.
  • a method for forming a contact in a semiconductor memory device comprises forming a conductive layer on a substrate; forming an insulation layer on the conductive layer; depositing a photoresist on the insulation layer; exposing the photoresist using a photomask; the photomask having a first and a second portions; developing the exposed photoresist; etching the exposed photoresist to form an opening having a substantial bilobate shape; the opening passing through a part of the insulation layer to an upper surface of the conductive layer; removing unexposed photoresist; and filling the opening with a conductive material.
  • FIG. 1 is a cross-sectional view of a double contact structure for a semiconductor memory device according to the prior art
  • FIG. 2 is an enlarged perspective view of a photo masking process for forming a contact structure according to the prior art
  • FIG. 3 is a top view of a photomask according to a preferred embodiment of the present invention.
  • FIG. 4 is a top view of a latent image pattern of a photoresist exposed to a light beam using the photomask shown in FIG. 3;
  • FIG. 5 illustrates a top view of a photomask according to another embodiment of the present invention.
  • FIG. 6 is a cross-sectional view of a contact structure formed by etching the pattern shown in FIG. 4.
  • a photomask 50 is applied.
  • the photomask 50 includes a pattern 56, square portions 53 and 54, and a bridge portion 55 formed on a glass substrate 51.
  • the square portions 53 and 54 are separated from each other.
  • the bridge portion 55 forms a closed curved surface by connecting the angled parts 53 and 54 with each other.
  • FIG. 3 illustrates the photomask 50 for a positive photoresist process, it should be apparent to one skilled in the art that a similar structure for a negative photoresist process is also possible. That is, the photomask 50 may have a structure in which the pattern 56 is coated with chromium and ultraviolet rays, laser beams, or electronic beams pass through the glass substrate 51.
  • a photoresist 40 is deposited on the insulation layer 30.
  • Using the photomask 50 having the structure shown in FIG. 3 exposes the photoresist 40.
  • the exposed photoresist is developed and etched thereby forming a through opening 34 passing through the top of the insulation layer 30 to the upper surface of the conductive layer 20.
  • the photoresist that is not developed is removed and the through opening 34 is filled with conductive material to form a contact plug 35.
  • a latent image pattern 43 of the positive photoresist 40 exposed to the light beam by using the photomask 50 is distinguished from an unexposed portion 44.
  • the latent image pattern 43 having a bilobate shape has round portions a and c. Round portions a and c are separated from each other by a bride portion b. Bridge portion b forms a closed curved surface by connecting the round portions a and c.
  • a semiconductor exposing apparatus is used to transfer the pattern 56 on the photomask 50 to the photoresist 40 formed on the interlayer insulation layer 30 (FIG. 6).
  • the light beam generated by the semiconductor exposing apparatus is preferably light having about a 248-nanometer wavelength.
  • the semiconductor exposing apparatus is preferably an eximer laser or a mercury lamp.
  • FIG. 6 shows a contact structure formed by etching the pattern shown in FIG. 4. If only the latent image pattern 43 is developed during a developing process, a portion of the top of the interlayer insulation layer 30 is exposed. The shape of the exposed interlayer insulation layer is the same as that of the latent image pattern 43. If the exposed interlayer insulation layer is etched, one contact hole 34 is formed as the through opening. While wet etching is performed for a prescribed time and dry etching is performed until the upper portion of the lower conductive layer 20 is exposed, the isotropic etching and the anisotropic etching are implemented. Therefore, the contact hole 34 has a round etching surface 31 and a linear etching surface 33 as shown in FIG. 6. The upper surface of the conductive layer 20 exposed by the through opening 34 has a bilobate shape similar to the pattern 43.
  • the contact plug 35 is formed by removing the unexposed part 44 remaining on the photoresist 40 and filling the through opening 34 with a metal (e.g., tungsten).
  • the contact plug 35 connects a part of the lower conductive layer 20 with an upper conductive layer later formed on the insulation layer 30. Since the plane shape of the contact plug 35 has the larger area than the elliptical shape of the prior art, the contact area is increased thereby improving the ohmic contact even at lower power supply voltages. That is, since there is no peak point on the insulation layer even contact related defects and the contact resistance are both reduced. Importantly, no fabrication processes are added to achieve these reductions.
  • the photomask 50 having square portions 53 and 54 separated from each other on the glass substrate 51 coated with chromium.
  • the structure of the photomask 50 may be changed.
  • the photomask 50 may have a structure in which the pattern is coated with the chromium and ultraviolet rays, laser beams, or electronic beams pass through the glass substrate 51.
  • a distance L between the two square portions 53 and 54 is a notable parameter. In a preferred embodiment of the present invention, the distance L is less than 0.3 ⁇ m.
  • the pattern similar to the latent image pattern 43 shown in FIG. 4 is obtained by exposure using the semiconductor exposing apparatus.
  • the lower conductive layer 20 shown in FIG. 6 may be one of a polycide layer consisting of a polycrystalline silicon layer formed on a gate oxide layer of each MOS transistor and a refractory metal silicide layer, a surface layer of a drain/source doping region, and a metal layer.
  • the plug 35 may be formed with a doped polycrystalline silicon or tungsten.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
US09/209,649 1997-12-12 1998-12-10 Contact structure of semiconductor memory device for reducing contact related defect and contact resistance and method for forming the same Expired - Lifetime US6072242A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1019970068246A KR100273703B1 (ko) 1997-12-12 1997-12-12 콘택관련 결함 및 콘택저항을 감소하기 위한 반도체 장치의 콘택구조 및 그 제조 방법
KR97-68246 1997-12-12

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Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6353266B1 (en) * 1999-05-19 2002-03-05 Nec Corporation Semiconductor device having improved pad coupled to wiring on semiconductor substrate
US20020195707A1 (en) * 2001-06-20 2002-12-26 International Business Machines Corporation Extension of fatigue life for C4 solder ball to chip connection
US6737748B2 (en) * 1999-08-23 2004-05-18 Infineon Technologies Ag Stacked via with specially designed landing pad for integrated semiconductor structures
US20040099960A1 (en) * 2001-04-05 2004-05-27 Sylvia Adae-Amoakoh Economical high density chip carrier
US20050072998A1 (en) * 2003-10-07 2005-04-07 Fujitsu Limited Semiconductor device and manufacturing method thereof
US20060055043A1 (en) * 2004-09-13 2006-03-16 Taiwan Semiconductor Manufacturing Company, Ltd. Connection structure for semiconductor devices
US20090039275A1 (en) * 2002-05-14 2009-02-12 Kabushiki Kaisha Toshiba Processing method, manufacturing method of semiconductor device, and processing apparatus
US20090302479A1 (en) * 2008-06-06 2009-12-10 Avago Technologies Wireless Ip (Singapore) Pte. Ltd. Semiconductor structures having vias
US20100202208A1 (en) * 2009-02-06 2010-08-12 Masato Endo Semiconductor device including contact plug having an elliptical sectional shape
US20120074583A1 (en) * 2010-09-28 2012-03-29 Dao Thuy B Semiconductor structure having a through substrate via (tsv) and method for forming
US8178981B2 (en) 2004-02-26 2012-05-15 Renesas Electronics Corporation Semiconductor device
US10374085B2 (en) * 2017-11-15 2019-08-06 Samsung Electronics Co., Ltd. Semiconductor device

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JP4509521B2 (ja) * 2003-10-01 2010-07-21 東芝マイクロエレクトロニクス株式会社 自動設計方法、自動設計装置、レチクルセット、半導体集積回路及び設計プログラム
KR100687863B1 (ko) * 2004-12-29 2007-02-27 주식회사 하이닉스반도체 아령형 금속 콘택 형성 방법
JP5094019B2 (ja) * 2005-01-21 2012-12-12 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP2006287216A (ja) * 2005-03-10 2006-10-19 Nec Electronics Corp 半導体装置及び半導体装置の製造方法
KR100911873B1 (ko) * 2006-10-09 2009-08-11 주식회사 하이닉스반도체 반도체 메모리 소자의 커패시터 스토리지 노드 형성용 노광마스크
KR102114315B1 (ko) * 2013-08-21 2020-05-25 삼성디스플레이 주식회사 박막 트랜지스터 어레이 기판, 이를 포함하는 표시 장치, 및 박막 트랜지스터 어레이 기판의 제조 방법

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US5523920A (en) * 1994-01-03 1996-06-04 Motorola, Inc. Printed circuit board comprising elevated bond pads

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US5523920A (en) * 1994-01-03 1996-06-04 Motorola, Inc. Printed circuit board comprising elevated bond pads

Cited By (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6353266B1 (en) * 1999-05-19 2002-03-05 Nec Corporation Semiconductor device having improved pad coupled to wiring on semiconductor substrate
US6737748B2 (en) * 1999-08-23 2004-05-18 Infineon Technologies Ag Stacked via with specially designed landing pad for integrated semiconductor structures
US20040099960A1 (en) * 2001-04-05 2004-05-27 Sylvia Adae-Amoakoh Economical high density chip carrier
US6753612B2 (en) 2001-04-05 2004-06-22 International Business Machines Corporation Economical high density chip carrier
US6998290B2 (en) 2001-04-05 2006-02-14 International Business Machines Corporation Economical high density chip carrier
US20020195707A1 (en) * 2001-06-20 2002-12-26 International Business Machines Corporation Extension of fatigue life for C4 solder ball to chip connection
US20050224973A1 (en) * 2001-06-20 2005-10-13 Bernier William E Extension of fatigue life for C4 solder ball to chip connection
US7067916B2 (en) 2001-06-20 2006-06-27 International Business Machines Corporation Extension of fatigue life for C4 solder ball to chip connection
US7119003B2 (en) 2001-06-20 2006-10-10 International Business Machines Corporation Extension of fatigue life for C4 solder ball to chip connection
US7727853B2 (en) * 2002-05-14 2010-06-01 Kabushiki Kaisha Toshiba Processing method, manufacturing method of semiconductor device, and processing apparatus
US20090039275A1 (en) * 2002-05-14 2009-02-12 Kabushiki Kaisha Toshiba Processing method, manufacturing method of semiconductor device, and processing apparatus
US20070184595A1 (en) * 2003-10-07 2007-08-09 Fujitsu Limited Semiconductor device and manufacturing method thereof
US7211850B2 (en) * 2003-10-07 2007-05-01 Fujitsu Limited Semiconductor device with specifically shaped contact holes
US20050072998A1 (en) * 2003-10-07 2005-04-07 Fujitsu Limited Semiconductor device and manufacturing method thereof
US8178981B2 (en) 2004-02-26 2012-05-15 Renesas Electronics Corporation Semiconductor device
CN100394594C (zh) * 2004-09-13 2008-06-11 台湾积体电路制造股份有限公司 半导体元件及半导体元件的连接结构
US20060055043A1 (en) * 2004-09-13 2006-03-16 Taiwan Semiconductor Manufacturing Company, Ltd. Connection structure for semiconductor devices
US7705464B2 (en) * 2004-09-13 2010-04-27 Taiwan Semiconductor Manufacturing Company, Ltd. Connection structure for semiconductor devices
US20090302479A1 (en) * 2008-06-06 2009-12-10 Avago Technologies Wireless Ip (Singapore) Pte. Ltd. Semiconductor structures having vias
US8169824B2 (en) * 2009-02-06 2012-05-01 Kabushiki Kaisha Toshiba Semiconductor device including contact plug having an elliptical sectional shape
US20100202208A1 (en) * 2009-02-06 2010-08-12 Masato Endo Semiconductor device including contact plug having an elliptical sectional shape
US20120074583A1 (en) * 2010-09-28 2012-03-29 Dao Thuy B Semiconductor structure having a through substrate via (tsv) and method for forming
US8890324B2 (en) * 2010-09-28 2014-11-18 Freescale Semiconductor, Inc. Semiconductor structure having a through substrate via (TSV) and method for forming
US10374085B2 (en) * 2017-11-15 2019-08-06 Samsung Electronics Co., Ltd. Semiconductor device
US10886404B2 (en) 2017-11-15 2021-01-05 Samsung Electronics Co., Ltd. Semiconductor device
US11362211B2 (en) 2017-11-15 2022-06-14 Samsung Electronics Co., Ltd. Semiconductor device

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Publication number Publication date
JP3683110B2 (ja) 2005-08-17
KR19990049318A (ko) 1999-07-05
JPH11243067A (ja) 1999-09-07
KR100273703B1 (ko) 2001-03-02

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