US5345378A - Method and apparatus for operating a programmable controller for controlling a technical process - Google Patents

Method and apparatus for operating a programmable controller for controlling a technical process Download PDF

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US5345378A
US5345378A US07/905,807 US90580792A US5345378A US 5345378 A US5345378 A US 5345378A US 90580792 A US90580792 A US 90580792A US 5345378 A US5345378 A US 5345378A
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Prior art keywords
input signals
cycle
signals
input
output
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US07/905,807
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Georg Lang
Georg Trummer
Edgar Sigwart
Werner Fraas
Andrea Misler
Gerhard Reinert
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Siemens AG
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Siemens AG
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Assigned to SIEMENS AKTIENGESELLSCHAFT reassignment SIEMENS AKTIENGESELLSCHAFT ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: FRAAS, WERNER, LANG, GEORG, MISLER, ANDREA, REINERT, GERHARD, SIGWART, EDGAR, TRUMMER, GEORG
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors

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  • the present invention relates to a method for operating a programmable controller for controlling a technical process and, in particular a modular programmable controller having a process interface system linked to it, comprising the following cyclically executed steps:
  • the present invention improves the cycle time by processing the input signals of one cycle at, least in part, simultaneously with the outputting of the output signals of the preceding cycle and, at least in part, simultaneously with the reading in of input signals of the subsequent cycle.
  • the output signals of the preceding cycle are advantageously copied from a working storage into a buffer storage, and the input signals of the cycle are copied from the buffer storage into the working storage, so that the input signals of the subsequent cycle and the output signals of the preceding cycle are not altered as a result of the processing.
  • output signals of the second cycle are copied into the buffer storage after the input signals of said second cycle are processed and the output signals of said first cycle are provided to the output interface from the buffer storage;
  • the input signals of a third cycle are read into the buffer storage after the output signals of said first cycle have been output and the input signals of said second cycle have been copied into said working storage;
  • each process step is advantageously begun immediately upon reaching its acceptability conditions.
  • the cycle time can be shortened still further if the output signals of the first cycle are output to the process interface system, at least in part, while the input signals of the second cycle are copied into the working storage and/or the input signals of the third cycle from the process interface system are read in, at least in part, while the output signals of said second cycle are copied into the buffer storage.
  • Another possibility for simultaneously implementing input/output and processing includes steps of:
  • a programmable controller for controlling a technical process according to a method as provided by the present invention includes the following elements:
  • At least one processor for processing input signals supplied by a process interface system
  • At least one input and one output unit preferably a combined input/output unit, for reading in the input signals and for outputting the output signals to the process interface system;
  • a working storage for storing the input signals and the output signals
  • a buffer storage for temporarily storing the input and the output signals
  • an input/output controller for reading in the input signals from the process interface system and for outputting the output signals to the process interface system.
  • Providing the buffer storage with a storage area for storing change indicators, and providing the programmable controller with a counter for counting the cycles permits the programmable controller to advantageously minimize data transfer.
  • the resources required to copy the output signals into a buffer storage and the input signals into a working storage can be minimized when the working storage and the buffer storage have the same design and when both the processor and the controller can access both the working storage and the buffer storage.
  • FIG. 1 is a block diagram illustrating a programmable controller which can execute a method according to an embodiment of the present invention.
  • FIG. 2 is a flow chart of a single cycle in accordance with an embodiment of the present invention.
  • FIGS. 3 to 6 show examples of typical program execution schemata according to an embodiment the present invention.
  • FIG. 7 depicts a principle of data management in the buffer storage.
  • FIG. 8 is another block diagram illustrating a second embodiment of a programmable controller which can execute the method of the present invention.
  • FIG. 9 is a block diagram depicting the structure of an intelligent input/output module which may be used in an embodiment of the present invention.
  • a central processing unit 1 of a programmable controller of a modular design is linked via bus 2 to modules 3 which can be input modules, output modules, or combined input/output modules, both for digital as well as for analog data input/output.
  • the modules 3 are connected via lines 4 to process control elements (not shown), for example final controlling elements or sensors.
  • the process P is controlled and monitored through the process control elements.
  • the central processing unit 1 has an internal bus 5, to which the following components are linked:
  • microprocessor 6 which executes a program stored in the program storage 7;
  • the input/output controller 9 has a buffer storage 10, a component 11 having internal logic, and a counter 12 for counting cycles.
  • the component 11 can be a complete processor, for example, but can also be an application specific integrated circuit (ASIC). Both the working storage 8, as well as the buffer storage 10, can consist of several partial storage units, for example only for the input signals and the output signals.
  • the internal bus 5 is essentially completely independent of the external bus 2. As a result, it is possible to use a newly developed central processing unit 1 with an internal bus 5 of, for example, a 32-bit data capacity without developing a completely new backplane bus system even when the external bus 2 has a lower data capacity such as 8 bits.
  • input signals are cyclically supplied by the process interface system (not shown), from all types of sensors, and are read into the programmable controller.
  • the input signals are then processed.
  • the output signals for the process interface system to be supplied to all types of final controlling elements, are determined based on the input signals. Further, status messages and alarm indications may be output to the user.
  • the output signals are output to the process interface system. For this purpose, the following steps are carried out.
  • the processor 6 calculates the process image PAA' of the outputs from the input signals, as well as possible additional variables while executing the program stored in the storage 7, and then files this process image PAA' in the working storage 8 (this step is designated by the symbol B)
  • the component 11 reads process image PAA from the buffer storage and sends it to the modules 3 via the bus 2 (this step is designated by the symbol A);
  • the modules 3 output the output signals to the final controlling elements and thereby control the process P in the desired manner.
  • FIG. 2 depicts the chronological sequence of steps E, E', B, A' and A of one cycle.
  • the present invention utilizes the times when the processor 6 or the controller 9 are idle.
  • the controller 9 may carry out step E for the next cycle before step A of the present cycle is performed.
  • the processor 6 can continue processing with step E' of the next cycle (transfer of input from buffer storage 10 to working storage 8) immediately after the completion of step A' (transfer of output from working storage 8 to the buffer storage 10). This is indicated by the small box drawn with a dotted line to the right.
  • controller 9 can execute step A of the preceding cycle during its idle time between steps E and A for the present cycle, so that also step A' of the preceding cycle can directly adjoin step E', as indicated by the small box drawn with a dotted line to the left.
  • steps E, E' as well as A, A' must not be allowed to overlap temporally, otherwise inconsistencies could arise in the data.
  • steps E and A' as well as A and E' can overlap temporally. This fact is used advantageously in the following to further shorten the cycle time.
  • FIGS. 3 to 5 show various processing examples which are possible depending on the length of the program to be executed and the scope of the data transfer. The same subscripts refer to the same cycle.
  • steps E and A are carried out only once per cycle, whereby each of the five process steps begins immediately after reaching its acceptability conditions.
  • steps A and E are continuously executed until the process step B is complete.
  • the processor 6 then waits until the currently running or, in case step A was just carried out, the next step E is complete, before executing steps A' and E'.
  • the controller 9 again begins with steps A and E.
  • This procedure is advantageous because the processor 6 always has available "fresh" input signals, while in the procedure referring to FIGS. 3-5 described above, (compare in particular FIG. 3), the last read-in operation can already have taken place some time ago.
  • the cycle time of the process according to FIG. 6 is not quite as optimal as the former process.
  • step B n+1 begins at the same time as step A n .
  • step A n could begin after step A' n is complete, however, it is easier to realize the procedure depicted in FIG. 6.
  • the process can be optimized even further when only the read-in operation E n is executed again and again, while the output operation A n is executed only the first time.
  • FIG. 7 illustrates the organization of the dataword of the buffer storage 10 of the controller 9.
  • Each input or output signal has a definite value, which is stored in the value storage area of a data word.
  • each data word also has two bits, exist and change, which serve to further optimize steps E and A timewise.
  • a bit corresponding to whether the input or output that correlates with the data word exists at all in or rather is linked to the particular configuration of the programmable controller is stored in the exist bit.
  • a bit corresponding to whether the value of the data word has changed since the last input or output is stored in the change bit.
  • the controller 9 Before the controller 9 emits the output signals or reads in the input signals, it checks if the signal in question exists at all and whether it has changed since the last output or since the last read-in operation based on the exist bit and the change bit. Only the changes are output by the controller 9 to the modules 3 or read in by the modules 3. As a result, the time required to execute steps E and A can be considerably reduced.
  • all existing signals are transmitted after a preselectable number of cycles.
  • the number of cycles is typically in the range of from 10 to 1000, preferably around 100.
  • the counter 12 signals the component 11, which, as a result, queries all existing input/outputs (not only those whose value has changed) during the next data transfer A, E.
  • the counter 12 is then reset.
  • monitoring any change in the signals is particularly simple because all necessary information is available within the central processing unit 1 and is automatically transmitted to the controller 9 when the process image PAA' is copied into the buffer storage 10.
  • the buffer storage has to exhibit the change bits only for the output values, not on the other hand for the input signals.
  • the units 3 To compare the data read at a given moment to the previously read data, the units 3 must possess a minimum storage capacity for intermediately storing the last input signals read in, as well as a logic for comparing the newly reading input signals to the input signals read in last and must be able to actively access the bus 2, at least by emitting an interrupt signal.
  • the number of input signals to be transmitted can be reduced still further when the input signals are read into the input units 3 only when a read-in command sent out by the central processing unit 1 is present. Therefore, only the signal values last and currently read into the input units 3 decide if the input signal in question must be transmitted rather than interim fluctuations.
  • the read-in command is advantageously transmitted immediately after an output operation A is complete.
  • FIG. 8 depicts such a module 3.
  • the module 3 exhibits an application specific integrated circuit 13 which, for example, enables the latches 14 and, thus, reads in the input signals applied to the lines 4 based on a "read data" command transmitted via the control line RD.
  • the ASIC 13 compares the newly read-in data to the data stored in the storage 15, which had been read in during the preceding read-in operation, and notes which input signals have changed. This comparison preferably takes place in the same manner as the comparison of the output signals, in the controller 9.
  • the ASIC 13 can transmit a "read request" via the control line RR to the central processing unit 1 signifying that input signals are to be read from the module 3 into the central processing unit.
  • the data are read out of the module 3 by the controller 9. Therefore, except for transmitting the read-out request, the module 3 is purely a passive component, as well as a storage module. In much the same way, the system may be configured so that the module 3 may request the allocation of the bus 2 via the line BR through the command "bus request". Therefore, the module 3 can actively transmit its data via the address bus 16 and the data bus 17 to the controller 9.
  • FIG. 9 A further possible development of the design of the central processing unit 1 depicted in FIG. 1 is shown in FIG. 9.
  • the buffer storage 10 is not a component of the controller 9, but rather is configured on the central processing unit on a par with the working storage 8. Access to the storage 8, 10 follows from bus 2, is via a switch 18'. Access to the storage 8, 10 follows from bus 5 via a switch 18. Therefore, process images no longer have to be copied from the working storage 8 into the buffer storage 10 and vice versa.
  • the processor 6 accesses only the working storage 8 via the switch 18, independent of what happens to the buffer storage 10.
  • the controller 9 can only access the buffer storage 10 via the switch 18'.
  • the storages 8 and 10 must have the same design. Furthermore, at least the switches 18, 18' should have tri-state buffers, so that, for example, the switches 18 accessing of the storage 8 does not disturb the switches 18' accessing of the storage 10 and vice versa. In the same way, however, designing the storages 8 and 10 as dual-port RAMs is also possible.
  • the switching over of the switches 18, 18' can also take place via the processor 6, instead of via the flag F, when this processor receives corresponding status information from the controller 9.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Automation & Control Theory (AREA)
  • General Engineering & Computer Science (AREA)
  • Programmable Controllers (AREA)
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US07/905,807 1991-06-28 1992-06-29 Method and apparatus for operating a programmable controller for controlling a technical process Expired - Lifetime US5345378A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP91110763.9 1991-06-28
EP91110763A EP0525214B1 (de) 1991-06-28 1991-06-28 Verfahren zum Betreiben eines Automatisierungsgeräts

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EP (1) EP0525214B1 (ja)
JP (1) JP2710151B2 (ja)
AT (1) ATE121855T1 (ja)
DE (1) DE59105332D1 (ja)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010034830A1 (en) * 1999-05-27 2001-10-25 Kenji Seki Programmable controller
EP1435548A2 (en) * 1996-11-29 2004-07-07 Omron Corporation Controller
US20110098790A1 (en) * 2009-10-26 2011-04-28 Albert Daxer Methods for treating corneal disease
US9274993B2 (en) 2012-03-23 2016-03-01 Siemens Aktiengesellschaft Interface device and method for consistently exchanging data
US20160077509A1 (en) * 2013-04-16 2016-03-17 Siemens Aktiengesellschaft Programmable logic controller having low latency

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10127264A1 (de) * 2001-06-05 2002-12-12 Siemens Ag Verfahren zur Unterstützung des unterbrechbaren, geschachtelten konsistenten Datenaustausches

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GB2033624A (en) * 1978-10-27 1980-05-21 Fujitsu Ltd Digital signal processing system
EP0082722A2 (en) * 1981-12-21 1983-06-29 General Electric Company Computer system with auxiliary service computer
US4658356A (en) * 1982-11-22 1987-04-14 Hitachi, Ltd. Control system for updating a change bit
EP0298396A2 (en) * 1987-07-08 1989-01-11 Hitachi, Ltd. Function-distributed control apparatus
US4858101A (en) * 1987-08-26 1989-08-15 Allen-Bradley Company, Inc. Programmable controller with parallel processors
US4916600A (en) * 1982-06-04 1990-04-10 Michell Ropelato Modular device for controlling industrial processes
US4956785A (en) * 1987-01-23 1990-09-11 Fanuc Ltd. Numerical control method with a parallel processing function
US5042002A (en) * 1989-03-31 1991-08-20 Allen-Bradley Company, Inc. Programmable controller with a directed sequencer
US5068778A (en) * 1988-11-28 1991-11-26 Reliance Electric Industrial Company Industrial control system device
US5164894A (en) * 1990-04-26 1992-11-17 Elsag International B.V. Method of data entry into a plant loop

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JPS5746698A (en) * 1980-09-03 1982-03-17 Hitachi Ltd Controller for self-excited ac generator
JPS58201136A (ja) * 1982-05-20 1983-11-22 Mitsubishi Electric Corp 通信制御装置
JPS59200303A (ja) * 1983-04-27 1984-11-13 Yokogawa Hokushin Electric Corp プログラマブル制御装置

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2033624A (en) * 1978-10-27 1980-05-21 Fujitsu Ltd Digital signal processing system
EP0082722A2 (en) * 1981-12-21 1983-06-29 General Electric Company Computer system with auxiliary service computer
US4916600A (en) * 1982-06-04 1990-04-10 Michell Ropelato Modular device for controlling industrial processes
US4658356A (en) * 1982-11-22 1987-04-14 Hitachi, Ltd. Control system for updating a change bit
US4956785A (en) * 1987-01-23 1990-09-11 Fanuc Ltd. Numerical control method with a parallel processing function
EP0298396A2 (en) * 1987-07-08 1989-01-11 Hitachi, Ltd. Function-distributed control apparatus
US4858101A (en) * 1987-08-26 1989-08-15 Allen-Bradley Company, Inc. Programmable controller with parallel processors
US5068778A (en) * 1988-11-28 1991-11-26 Reliance Electric Industrial Company Industrial control system device
US5042002A (en) * 1989-03-31 1991-08-20 Allen-Bradley Company, Inc. Programmable controller with a directed sequencer
US5164894A (en) * 1990-04-26 1992-11-17 Elsag International B.V. Method of data entry into a plant loop

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1435548A2 (en) * 1996-11-29 2004-07-07 Omron Corporation Controller
EP1435548A3 (en) * 1996-11-29 2005-09-07 Omron Corporation Controller
US20010034830A1 (en) * 1999-05-27 2001-10-25 Kenji Seki Programmable controller
US20110098790A1 (en) * 2009-10-26 2011-04-28 Albert Daxer Methods for treating corneal disease
US9274993B2 (en) 2012-03-23 2016-03-01 Siemens Aktiengesellschaft Interface device and method for consistently exchanging data
US20160077509A1 (en) * 2013-04-16 2016-03-17 Siemens Aktiengesellschaft Programmable logic controller having low latency
US10274922B2 (en) * 2013-04-16 2019-04-30 Siemens Aktiengesellschaft Programmable logic controller having low latency

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JP2710151B2 (ja) 1998-02-10
ATE121855T1 (de) 1995-05-15
EP0525214A1 (de) 1993-02-03
EP0525214B1 (de) 1995-04-26
DE59105332D1 (de) 1995-06-01
JPH05189232A (ja) 1993-07-30

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