GB2033624A - Digital signal processing system - Google Patents

Abstract

in a digital signal processing system, a data input cycle, an arithmetic operation cycle and a data output cycle are serially arranged in each time slot. The data input cycle of the (k+1)th (k=0,1,2,3...) time slot, the arithmetic operation cycle of the (k)th time slot and the data output cycle of the (k-1)th time slot are parallelly allotted into the same duration. These cycles are executed by using a data set having a fixed data format and an instruction code which is included in the head of the data set.

Description

SPECIFICATION Digital signal processing system The present invention relates to a digital signal processing system, and more particularly relates to a digital signal processing system which is most preferably utilized in a MODEM (Modulator - DEModulator).

The MODEM is used at each end of a telephone channel to convert binary digital information to audio signals suitable for transmission over the line, and vice versa.lt is the latest tendency to operate the MODEM with a very high speed operation, for the purpose of dealing with a very large amount of data for data communication or achieving a high speed facsimile transmission. Accordingly, although many kinds of digital processing techniques have been provided, it is necessary to develop a digital processing technique which is most suitable for such a high speed operating MODEM. Further, such a digital processing technique should preferably be realized by the aid of LSls (Large Scale Integrated Circuits).

Careful consideration is required in choosing the LSI architecture in order to obtain efficient and economical LSI realization of the modem functions described. The LSI architecture must be sufficiently flexible and expandable so that it allows accomodation of various changes in the specifications or adaption to other systems.

Designing different LSl's for each different function inevitably results in developing too many different kinds of LST's and, moreover, although this approach may be very efficient, it often suffers from lack of flexibility, There have been several reports describing successful utilization of off-the-shelf microprocessors to data modems. Although this approach seems to provide the highest degree of flexibility, there is a slight problem in that the current microprocessors cannot efficiently perform the multiplication operations abundant in modem functions.

The approach taken here is to develop an LSI processor matched to the DSP (Digital Signal Processor) applications and, when necessary, employ more than one of these LSl's to manage the total required quantity of arithmetic operations. The processor will thus be equipped with a powerful arithmetic unit and will have the ability to operate in multiprocessor mode. It will also include as many useful features of the common microprocessor as possible; the most important one being the firmware programmability. It is possible to significantly reduce the number of different LSl's needed to be developed and also achieve a high degree of flexibility using this approach.

Therefore, it is an object of the present invention to provide a digital signal processing system which is useful for fabricating the MODEM by using a few kinds of LSls. However, it should be understood that, as will be apparent from the following explanation, the digital signal processing system of the present invention may be applied not only to the aforementioned MODEM, but also to other digital data processing apparatuses.

The present invention will be more apparent from the ensuring description with reference to the accompanying drawings wherein: Figure lisa block diagram of MODEM adopted quadature amplitude modulation method; Figure 2 depicts timing charts used for schematically explaining the basic processing sequence utilized in a digital signal processing system according to the present invention; Figure 3 illustrates one example of a data set which is suitable for conducting the digital signal processing system according to the present invention; Figure 4 is a block diagram illustrating an example of the digital processing system according to the present invention; Figure 5 depicts timing charts representing statuses of the system shown in Figure 4;; Figure Sdepicts timing charts used for explaining the operation for the starting program which runs in the system shown in Figure 4; Figure 7schematically illustrates contents of the control storage (ROM) 430 shown in Figure 4; Figures depicts timing charts used for explaining an initial starting of the processing adapted to the digital signal processing system according to the present invention; Figure 9 is an example of a circuit diagram illustrating hardware for executing an initial starting of the program to be processed by the digital signal processing system; Figure 10A depicts timing charts used for explaining the operation of the hardware shown in Figure 9;; Figure 108 depicts timing charts used for explaining the hardware shown in Figure 9, the scale of timing is expanded compared to that of Figure 1 OA; Figure 11 depicts timing charts used for explaining a unique method preferably employed in the digital processing system shown in Figure 4; Figure 12 schematically illustrates a flow of programs stored in the control storage (ROM) 430 shown in Figure 4, according to the present invention; Figure 13 illustrates a circuit diagram of one example of the hardware for carrying out the unique method, explained with reference to Figures 11 and 12, employed preferably in the digital signal processing system; Figure 14 depicts timing charts used for explaining the processes of the unique method, and;; Figure 15 is a block diagram of improved MODEMs 110 and 150 shown in Figure 1, which improved MODEMs are constructed by utilizing the digital signal processing system according to the present invention.

Although, as previously mentioned, the digital signal processing system of the present invention can be applied to various kinds of digital data processing apparatuses, the following explanation of the present invention is effected by taking, for example, a digital signal processing system utilized in the MODEM.

In Figure 1, which is a block diagram of a MODEM, the reference numeral 110 represents a transmitter and the reference numeral 150 represents a receiver. The transmitter 110 is comprised of a code converter (CODE CONT) 111, a signal point generator (SIGNAL POINT) 112, a roll-off filter (ROF) 113, a roll-off filter (ROF) 114, a mixer 115, a mixer 116, a phase shifter (900)117, an adder 118, digital/analogue converter (D'A) 119, a low pass filter 120, a sequence controller (SEQUENCER) 121 and a digital phase-locked loop circuit (D.PLL) 122.

The transmitter 110 is connected to the receiver 150 over a telephone line 130. The receiver 150 is comprised of a code converter (CODE CO NV) 151, a decision circuit (DEC) 152, a carrier phase tracking circuit (CAPC) 153, an automatic equalizer (AEQL) 154, a roll-off filter (ROF) 155, a roll-off filter (ROF) 156, a mixer 157, a mixer 158, a phase shifter (900)159, an analogue,digital converter (A/D) 160, an automatic gain controller (AGC) 161, a band pass filter (BPF) 162, a sequence controller (SEQUENCER) 163, a digital phase-locked loop circuit (D.PLL) 164, a timing signal extracting circuit (TIMING) 165 and a carrier dector (DET) 166.The reference symbols Di, denotes an input digital data signal, Dout denotes an output digital data signal, W denotes a carrier wave signal, and CLK denotes a clock signal. Other symbols RS, CS, ST2 and CD are commonly defined by the o-called C.C.I.T.T. Recommendation.

In the transmitter 110, the date to be transmitted (Din) are scrambled and then grouped to 4 bits at a time to form guad bits. The generator 112 determines a specified signal point among the sixteen signal points according to the quad bits. Then the generator 112 applies both the in-phase and quadrature components of the specified signal point, respectively, to the filters 113 and 114. The roll-of filters 113,114 and also the roll-off filters 155, 156 are employed so as to achieve a proper spectram shaping. The two outputs of filters 113 and 114 modulate the carrier wave signal W having the frequency of, for example 1700 Hz by means of the mixers 115,116 and a shifter 117, and the modulated signals are added up together by means of the adder 118 to form the final QAM signal.The output from the adder 118 is converted into an analogue signal by means of the DIA converter 119 and transmitted to the receiver over the line 130, 110 after filtering by the filter 120.

The sequence of the digital signal processing steps in the transmitter 110 is determined by the sequence controller 121. The synchronzation of the digital signals in the transmitter 110 is performed by the clock signal CLK produced from the D.PLL circuit 122.

In the receiver 150, after eliminating out-of-band noise with the band pass filter 162, the received modulated signal is passed through AGC 161 to obtain constant signal level. The output of AGC 161 is fed into AID converter 160 and changed to digital form. The digitalized signal is demodulated by mixer 157, 158 and passed through the roll-off filters 155,156 to eliminate unnecessary components and complete (together with the roll-off filter placed at the transmitter) the cosine roll-off spectrum shaping. Both the in-phase and quadrature components produced from the filters 155 and 156 are applied to the automatic equalizer 154.

The equalizer 154 compensates the distortion of the transmitted data signal. THe output from the equalizer is then applied to the carrier phase tracking circuit 153 which compensates both a frequency offset and a phase jitter included in the transmitted data signal. The equalized output from the circuit 153 is applied to the decision circuit 152, and after proper code conversion and descrambling by the circuit 151, the correct received date (Dout) can be obtained. The circuit 152 also transfers the error signal between the equalized data from the circuit 153 and the reference symbol point through a feed back path F to accomodate with the adaptive equalization abnd the carrier phase tracking. The detector 166 detects the arrival of a transmitted signal and activates the sequence controller 163.The circuit 165 extracts the timing signal included in the transmitted data signal and activates the D PLL circuit 164 so as to generate the reference clock signal CLK.

This MODEM which are constructed by utilizing the digital processing system of the present invention, can be fabricated by eight chips of LSls which are classified into only three different kinds of LSls. The reason why the number of kinds of LSls could be reduced is as follows. The circuit elements which construct the MODEM is divided into 2 parts, namely those functions which can be realized by digital signal processing operations and those which are more random logic type in nature and cannot be expressed by arithmetic operations. The latter part includes code conversion, frequency dividers, sequence controllers, and other miscellaneous functions. For these functions, it is necessary to design random logic LSls dedicated to each purposes. The former part can all be reduced to the Ax B+C < D type operations which includes, in the transmitter 110, the roll-off filters 113, 114, and the modulation means comprised of the mixers 115, 116, the adder 118 and the shifter 117 and, in the receiver 150, the roll-off filters 155, 156, the demodulation means comprised of the mixers 157, 158 and the shifter 159, the automatic equalizer 154, the timing signal extracting circuit 165 and the carrier phase tracking circuit 153. Thus, each of the above recited circuit elements (113),(114)... (165) can be constructed by the indentical chip of LSl. In each thereof, the above formula A x B + C is operated repeatedly. For example, the transversal-type digital filter can be expressed by the following equation.

The symbol Yk denotes the filtered output signal from the transversal-type digital filter and the symbols Ci is coefficient and Xk~o is input data. The above recited equation may be rewritten as follows.

Y-CX CX CX CX Yk 1 k-1C1Xk#l + C2Xk-2 + C3Xk-3 + C4Xk-4 + ... + CnXk-n The item C1Xk#l corresponds to the value C in the formula A x B + C. The values C2 and Xk-2 correspond, respectively to the values A and B in this formula A x B + C. That is, C2Xk#2 corresponds to A x B. In the next stage, the items (C1Xk#l + C2Xk-2) correspond to the value C. The values C3 and Xk-3 correspond, respectively, to the values A and B. Thus, the value of C1Xk-1 + C2Xk-2 + C3Xk-3 is obtained.Then the resultant value Yk may be obtained by executing the identical formula A x B +C with respect to C4Xk#4...

CnXk#n, repeatedly.

The digital signal processing system of the present invention will be explained hereinafter. This digital signal processing system can execute the above mentioned arithmetic function (A x B + C) with a very high degree of efficiency. It is important to note that the MODEMs should be operated under a so-called real time processing mode, and accordingly the digital signal processing system must execute the desired function, such as the above mentioned arithmetic function (A x B + C), with a high degree of efficiency.

Generally, the digital signal processing system of the prior art is operated by the following steps, (I) a) decoding an instruction, b) reading a data, c) executing an arithmetic operation, and further (II) d) decoding an instruction to be transmitted to an external device, and e) producing the resultant output data.

As will be apparent from the above recited steps a) through e), all the individual operations are executed one by one sequentially. Therefore, the digital signal processing system of the prior art cannot execute the desired arithmetic function with a high degree of efficiency. Further, the processing system of the prior art has the following shortcomings. Firstly, it is not easy to build up a microprogram being subject to a sequence of a desired function. Secondly, it requires much time and labour to revise the microprogram. Thirdly, it is not easy to simplify the construction of a clock means and a control means in the processing system. The above mentioned three shortcomings are derived from the fact that, in the processing system of the prior art, the number of the machine cycles are not the same with respect to the respective kinds of instructions.

The digital signal processing system of the present invention can execute the desired arithmetic function with a high degree of efficiency and also creates no shortcomings similar to the above mentioned three shortcomings of the prior art. Figure 2 depicts timing charts used for schematically explaining the basic processing sequence utilized in the digital signal processing system according to the present invention. In Figure 2, operation blocks 210,220,230,240,250,260 ... are respectively performed in (i)th, (i+1 )th, (i+2)th, (i+3)th, (i +4)th, (i+5)th processing steps.Each of the operation blocks, for example the operation blocks 210 through 240, is operated through a first cycle, a second cycle and a third cycle sequentially, and the first cycles are data input cycles (INPUT) 211,221,231 and 241, the second cycles are arithmetic operation cycles (OPERATION) 212,222,232 and 242 and the third cycles are data output cycles, if wanted, (OUTPUT) 213, 223, 233 and 243. Further, all the cycles are allotted so as to have the same constant duration. Furthermore, every two adjacent operation blocks are shifted from each other by a constant duration as the time t elapsed.

Consequently, the data input cycle 231, the arithmetic operation cycle 222 and the data output cycle 213 overlap with each other and are executed parallely.

When the above mentioned overlap processing is conducted, it is important to suitably determine the number of steps to be completed in each cycle, in order to complete the execution of each cyle within a same constant duration. In order to suitably determine the number of steps, two factors must be taken into consideration. The first factor is an algorithm, for operation and the second factor is a format for transferring the input and output data.

The number of steps to be completed in each cycle is determined, in the present invention to be, for example, five, when the aforesaid function A x B +C is operated. Accordingly, the read operation of the instruction code and also the feed operation of the input data, must be completed with a high degree of efficiency within the five steps. One example of a data set for completing each cycle within the five steps, is illustrated in Figure 3. In Figure 3, the data set 300 is composed of five data, that is instruction code 310, word "P" 320, word "Q" 330, word "R" 340 and word "S" 350. Each of the data 310 through 350 has 8 bits pattern (see the digits 1 through 8 on the top of the data 310). The data 310 through 350 are all 1 byte data. The five 1 byte data 310 through 350 are read from a storage device in the respective five steps mentioned above.

Specifically, regarding the aforesaid function A x B + C, the words "P" and "Q" are, respectively an upper 1 byte data and a lower 1 byte data of the multiplicand A which is composed of 2 byte data, the words "R" and "S" are, respectively an upper 1 byte data and a lower 1 byte data of the multiplier B which is also composed of 2 byte data. Since each arithmetic operation (see 212,222,232... in Figure 2) is conducted by using 2 byte data, both the multiplicand A and the multiplier B are composed of 2 byte data.

Figure 4 is a block diagram illustrating an example of the digital signal processing system according to the present invention, which system is operated according to the overlap processing (refer to Figure 2) and by using the data set 300 (see Figure 3). In Figure 4, members 401 through 409 constitute a microprocessor and members 420 and 430 constitute external devices with respect to the microprocessor.The reference numeral 401 represents an arithmetic unit which continuously performs the A x B + C - D type operations, 402 represents an input data selector, 403 represents an input buffer data register, 404 represents an instruction decoder, 405 represents a decoder buffer register, 406 represents a RAM address selector, 407 represents a RAM (Random Access Memory) address buffer register, 408 represents an output data selector, 409 represents a program counter. The reference numeral 420 represents a program counter. The reference numeral 420 represents a storage device made of a RAM, the reference numeral 430 represent program memories by ROMs (Read Only Memory) and the reference numeral 440 represents a common data bus. The programm memories 430 store the data set 300 shown in Figure 3.The instruction decoder 404 decodes the data stored in the buffer 405 so as to control the members 401, 402, 406, 408 and 409 via respective paths indicated by dotted lines. The address buffer register 407 stores the words "P", "Q", "R" and "S" (shown in Figure 3) sequentially. The storage device (RAM) 420 store operand data. The data selector 402 selects the desired one of the input data to be supplied to the arithmetic unit 401. The arithmetic unit 401 achieves the operation according to, for example, the aforesaid arithmetic function A x B + C. The selector 408 selects the desired one of the output data. The selector 406 is available to be used as a means for a modifying RAM addressing.

The operation of the system shown in Figure 4 will be explained with reference to Figure 5 which depicts timing charts representing the statuses of the system shown in Figure 4. The clock signals shown in a row a) are basic clock signals for synchronizing the operations performed in the system of Figure 4. The aforementioned five steps ...... (ss) shown in a row g) are allotted sequentially in synchronous with the clock signals. At first, the program counter 409 executes an access to the control storage 430 via a line 451 in synchronous with a clock signal C, in row a) of Figure 5. Then a first one of the data set 300 (see Figure 3), that is the instruction code 310 (see Figure 3), is read from the storage 430.A first data set is indicated by the reference symbol DS-1 in a row c) of Figure 5 and also the instruction code is indicated by the reference sumbol INST-1 in a row b) thereof. The instruction code INST-1 is applied, via a line 452, to the decoder buffer register 405, and then to the instruction decoder 404 where the decoder 404 decodes the instruction code INST-1 in synchronous with the clock signal C2. A duration in which the instruction code INST-1 is effective is defined by the time between the clock signals C2 through C6 (refer to "INST-1 effective" in a row d) ). All the operations during the INST-1 effective" are subject to the instruction code INST-1. At the same time, the word "P" shown in Figure 3 (refer to the reference symbol P-1 in the row b) ) is read from the control storage 430 in synchronous with the same clock signal C2.This word P-1 which is read from the storage 430, is stored in the RAM address buffer register 407, via lines 452 and 453 in synchronous with the clock signal C3. The reference symbol P-1 in a row e) indicates the stored word P-1.At the same time, the word "Q" shown in Figure 3 (refer to the reference symbol Q-1 in the row b) ) is read from the storage 430 in synchronous with the same clock signal C3. This word Q-1 is also stored in the register 407 (refer to the reference symbol Q-1 in the row e) ), in synchronous with the clock signal C4.In a similar way, the words "R" and "S" shown in Figure 3 are read from the storage 430 (refer to the reference symbols R-1 and S-1 in the row b) ) and stored in the register 407 (refer to the reference symbols R-1 and S-l in a row f) ), in synchronous with the respective clock signals C4, C5 and C6.

The words P-1 and R-1 are directly supplied to the RAM address buffer register 407, via the lines 452 and 453 from the storage 430. The words Q-1 and S-1 are supplied to the register 407, via lines 452,453 and a line 454 and the selector 406, from the storage 430. In a case where the words P-1 and Q-1 themselves are the operand data, as a multiplicand, to be arithmetically operated in the arithmetic unit 401, these words are directly supplied from the register 407 to the unit 401, via a line 455 and the input/output data selector 402.

Contrary to this, in a case where the words P-1 and Q-1, as a multiplier, are the access address information for the storage device (RAM) 420, the register 407 executes an access to the storage device 420 via a line 456.

The operand data read from the storage device 420 is supplied, as a multiplicand, to the arithmetic unit 401 via a line 457 and the selector 402. Depending on whether the words P-l and Q-1 are the operand data itself or whether these words P-1 and Q-1 are the access address information (in other words, depending on whether the words P-1 and Q-1 are the data read from the RAM 420 or the data read from the ROM 430), these words P-l and Q-1 can be supplied, via the lines 455 and 457, to the arithmetic unit 401 within a specified duration 457, to the arithmetic unit 401 within a specified duration until the rising edge of the clock signal C6 is generated, due to the presence of the register 407.Similarly, the words R-1 and 5.1 can be supplied to the unit 401 within a specified duration until the rising edge of the clock signal C7 is generated. It should be noted that, in the digital signa processing system of the prior art, although the data from the ROM can be directly supplied to the arithmetic unit, the data from the RAM must be supplied thereto through an addressing operation and a reading operation in synchronous with the next coming clock signal. However, in the present invention, since firstly the function of all the data to be supplied to the arithmetic unit is determined, in advance, by the instruction code, and secondly the five data 310 through 350 of each data set are fixedly alloted the respective five steps (, (2).. ~(see in row g) of Figure 5), the above mentioned addressing operation and all the reading operation to be conducted in synchronous with the next coming clock signal can be eliminated.

At the time when the clock signal C7 is generated, a second instruction code "INST-2" (see the row b) of Figure 5) of a second data set DS-2 (see the row c) of the same) is decoded by the instruction decoder 404.

Then the operation A x B of the aforesaid function A x B + C is carried out, in the unit 401, in accordance with the second instruction code INST-2, by using the above mentioned data P-1, Q-1, R-l and S-l which have already been supplied to the unit 401. This operation A x B, that is (P-1, Q-1) x (R-1,S-1), is completed within a second time slot TS-2 indicated in a row h) of Figure 5. This time slot TS-2 is also created along and within the five steps ()),0, ~... (ss) in a row g) of Figure 5.The resulting data A x B is added to the remained data C in the same time slot TS-2, which resulting data C was obtained, in a first time slot Sti, as a result of the identical operation A x B + C, and has been stored in an output data buffer register (not shown) contained in the arithmetic unit 401. At the same time, the words P-2, Q-2, R-2 and S-2 of a second data set DS-2 are read from the control storage and supplied to the arithmetic init 401 in the same manner as described before with respect to the words P-1, Q-1, R-l and S-1. Thus, the overlap processings are performed sequentially.

Whichever the data 320 through 350 (see Figure 3) of the data set, read from ROM 430, represent the operand data or the access address information, the operand data to be supplied to the arithmetic unit 401 can be transferred in synchronous with the specified clock signals, due to the presence of the RAM access address buffer register 407 which momentarily stores the data 320 through 350 therein.

Usually, the operand data to be supplied to the arithmetic unit 401 are produced from the control storage (ROM) 430 and the storage device (RAM) 420. However, the data to be supplied to the unit 401 are not limited to the above mentioned operand data. For example following data are also supplied to the unit 401.Firstly, the so-called ROM data stored in the control storage 430; secondly, the so-called RAM data stored in the storage device 420; thirdly, the so-called EXT (external) data (see the reference symbol EXT in Figure 4) which is supplied from the data bus 440 which is connected to external devices such as the sequence controller 121 in Figure 1; fourthly, the D data as a result of operation kept in the output data buffer register, which is supplied to the selector 408 via a line 458 and finally to the storage device 420 via a line 461; and lastly, the E data supplied from the input buffer data register 403. The above mentioned data EXT, D and E are provided to the arithmetic unit 401 by means of the selector 402. A line 462 transfers data to be operated repeatedly in the unit 401.During the process of these EXT, D and E data, it is not necessary to read the operand data from the storage device 420. Therefore, by utilizing this duration in which these EXT, D and E data are processed, the output data from the selector 408 can be written in the storage device 420. The selector 408 receives the data transferred on the line 458 and also the data transferred on a line 459.

In the above mentioned digital signal processing system, the serial processing is achieved in accordance with the series of the data sets (DS-1, DS-2... ) which are stored in the control storage 430. Accordingly, once the series of the data sets are stored in the storage 430, only the fixed serial processing is achieved. In other words, it is impossible to carry out an optional processing rather than the fixed serial processing.

Consequently, it is inconvenient to apply this system to, for example the MODEM shown in Figure 1. In the MODEM, it is often required to change the parameters to maintain the MODEM at a high level of quality, especially in the training period. In such case, the selector 406 in Figure 4 is available for simply changing the address to the RAMS. The selector 406 produces either the data via the line 454 or a data via a line 460. The data applied through the line 460 is an external control data ECD. Usually, on one hand, the upper byte of the data from the ROM 430 is directly applied, via the line 453, to the buffer register 407 and, on the other hand, the lower byte of the data therefrom is applied, via the line 454 and the selector 406.Thus, the selector 406 can produce either the lower byte of the data read from the storage 430 or the external control data ECD as a lower byte of the data to be used as RAM address data. In this case, it is not necessary for the processor to change the usual program in order to run the operation under the changed addresses, but merely to provide the external control data ECD instead of the data transferred through the line 454. Thus, the operand data to be supplied to the arithmetic unit 401 can be modified without changing the contents of the data sets stored in the ROM 430, and accordingly, the selector 406 together with the data ECD is very useful for the real time processing apparatus such as MODEM.

As mentioned above, the microprocessor is operated in accordance with the predetermined program by using the series of data sets (see Figure 3). Since the digital signal processing system of the present invention is utilized preferably in the MODEM, it is further necessary to provide a suitable method for starting the predetermined program adapted to activate the MODEM. The suitable method therefor will be explained hereinafter. The digital processing system executes the process in increments one by one in the program counter 409. That is, the program counter 409 executes the incremental access to the control storage 430, and the respective instruction codes are read from the storage 430. Then the system functions in accordance with the decoded instruction codes.At this time, an idle state of the system is established by executing an instruction code indicating a wait, that is a wait instruction. When the wait instruction is provided, the program counter 409 stops executing the access to the ROM 430. In the present invention, the system is designed to stop, once the wait instruction is detected, the data processing until a start pulse SP is supplied from an external device (not shown in Figure 4). The reason why the above mentioned idle state must be established in the system, is as follows. Generally, the MODEMs have various kinds of types, such as 9600 bits type MODEM, 7200 bit/s type MODEM, 4800 bit/s type MODEM and so on. Which type of the MODEMs will be employed, is decided by the user. Consequently, the system of the present invention must be designed so as to be adapted to any type of the MODEMs. In order to comply with such demand as mentioned above, it is necessary to establish an idle state in the system, during which idle state preparation for adapting the system to the specified type of the MODEMs is effected. This preparation will be clarified by the following explanation. Figure 6 depicts timing charts used for explaining the operation for starting the program for the purpose of accomplishing preparation mentioned above. In Figure 6, the clock signals CLK are shown in a row a). At first, the program counter 409 (see Figure 4) produces a ROM address data RA-1 (shown in a row b) ) so as to execute an access to the control storage 430 (see Figure 4). The data specified by the address RA-1, that is a ROM output data RO-1 (shown in a row c) ) is produced from the storage 430. This data RO-1 represents the wait instruction (see "WAIT"in a row d) ).When the wait instruction "WAIT" is decoded by the instruction decoder 404 (see Figure 4), a count enable signal CE becomes logic "0" as shown in row f). As a result, the program counter 409 stops executing the incremental access to the storage 430. At this time, the program counter 409 produces a next ROM address data RA-2 as shown in the row b) and a ROM output data RO-2 is produced from ROM 430 according to the address data RA-2. Since the count enable signal CE is now logic "0" subject to the wait instruction "WAIT", the output data RO-2 is held as it is for a while. Afterwards the start pulse SP having logic "1" is generated as shown in a row g).The start pulse SP induces a counter preset signal CP having logic "1" (see a row h) ) in synchronous with, for example, a processing phase PH4 shown in a row #). Processing phase PH1 through PH5 shown in rows i) through m) correspond to the respective five steps 0 through ( > shown in the row g) of Figure 5. The signal CP may be induced by the signal SP in synchronous with one of the processing phases other than PH4. However, the phase PH4 is preferable for inducing the signal CP, if a jitter included in the pulse SP is taken into consideration. Thus, a counter preset processing is completed by the signal CP. Then the output data RO-2 which has been left as it is, is now loaded in the program counter 409.After this, the program counter 409 starts executing the incremental access to the control storage 430 according to the sequence defined by the counter 409. In a row e), instruction decoder latch clock signals IL are illustrated. The first latch clock signal IL latches the state of the instruction decoder 404 so as not to decode the data RO-2 (see the row c) ), by mistake, in accordance with the forthcoming programs generated by the program counter 409. The second latch clock signal IL also latches the instruction decoder 404 so as to maintain an instruction "INST" (see the row d) ) defined by a data RO-3 (see the row c) ). The data RO-3 is specified by a data RA-(2+1) (see the row b) ). The data RA-(2+1) is preset in the program counter 409 based on the data RO-2.

During the above mentioned initial starting of the program, that is the aforesaid preparation for adapting the system to the specified type of the MODEMs, following four operations must be completed: I) a first operation for determing one specified processing program according to an external selection signal SYS; II) a second operation for clearing all the contents of the storage device (RAM) 420; III) a third operation for storing, in the device (RAM) 420, initial values adapted to the specified processing program mentioned in the above paragraph I), and; IV) a fourth operation for executing the specified processing program.

Figure 7 schematically illustrate contents of the control storage (ROM) 430 as an example. In Figure 7, a wait instruction "WAIT" is stored at, for example an address "00". Following addresses "01", "02", "03" and "04" are allotted for a system selection area 700. A part of the area 700 is selected by the above mentioned selection signal SYS. For example, the addresses "01", "02" and "03" correspond, respectively to the previously mentioned 9600 bit/s type MODEM, 7200 bitis type MODEM and 4800 bit/s type MODEM. In the system selection area, a jump instruction is stored. This jump instruction indicates, for example, a head address AD2 which specifies an initial program for a selected system No. 2. (see the reference numeral 702-0), which selected system corresponds to, for example, the 7200 bitis type MODEM system.Each last instruction of an initial program for a system No. 1 (see the reference numeral 701-0), a usual program for the system No. 1 (see 701-2), the initial program for the system No. 2 (702-0) and an usual program for the system No.2 (see 702-2), must be the wait instruction "WAIT" (see the row d) in Figure 6). Each of the usual programs 701-2 and 702-2 instructs the execution the overlap processing (refer to Figure 2).

Since the last instruction of the program is, as mentioned above, the wait instruction, when the wait instruction is executed at the last of the initial program 702-0, for example, the digital signal processing system is left in the idle state. During this idle state, a data which has read from the control storage 430, is left as it is, which data is an address "b" which designates a destination of the jump instruction. The data of address "b", which is left as it is during the idle state, is identical with the ROM output data RO-2 (see the row c) in Figure 6). This address "b" designates a head address ADb (see 702-1) of the usual program 702-2 of the system No. 2, and at the time when the start pulse SP (see the row gin Figure 6) is generated, the head address ADb is preset in the program counter 409.After this, the processing system executes the process in accordance with the usual program 702-2.

The above mentioned initial starting of the processing will be more apparent by the following description with reference to Figure 8 which depicts timing charts used for explaining the initial starting of the processing. In Figure 8, the sequential start pulses SP-0, SP-1, SP-2... are shown in a row a). At the beginning of the supply of power, a sequence signal SS-0 (see a row b) ) of the processing system is caused to be logic "1", thereby the signal SS-0 causes the contents of the program counter 409 to be clear (see a state "0" in a row c) and also a mode "idle" in a row e) ). A little time after the beginning of the supply of power, a sequence signal SS-1 is caused to be logic "1 " and then, the digital signal processing system initially starts the processing.During the time between the start pulses SP-1 and SP-2, it is determined which of the systems (No. 1, No.2...) is specified by the aforesaid external selection signal SYS, by means of a detecting circuit (explained hereinafter). The detecting circuit causes the program counter 409 to execute the incremental counting of the contents of the counter 409 so that one of the addresses "01 " through "04" of the system selection area 700 (see Figure 7) is selected according to the information contained in the signal SYS. The operation for executing the system selection is carried out in a duration V shown in a row d).At the same time, the RAM 420 is operated under a write mode so as to clear all the contents of the device (RAM) 420 (see the mode "CLEAR RAM" in the row e) ). in this case, since the input data to the device (RAM) is maintained to be "0" all the contents of the device (RAM) are cleared one by one, regardless of the contents of the programs, every time each clock signal is applied to the RAM address buffer register 407. Soon after, all the contents of the device (RAM) are cleared. The operation for clearing all the contents of the device (RAM), is very important in the processing system utilized in the MODEM. If the RAM is not cleared, when the automatic equalizer 154 (Figure 1) starts operating, it takes a relatively long time to be in an stable state.

During the existence of the sequence signal SS-1 when the start pulse SP-2 is generated, a head address AD2 (see Figure 7), for example, is set in the program counter 409, then the processing system starts processing in accordance with the initial program 702-0 (see Figure 7). The head address AD2 is determined by the aforementioned detecting circuit based on the external selection signal SYS. The processing system starts executing the initial program at the beginning of the duration W (see the row d) ) and finishes executing when the wait instruction is detected. The beginning of the duration W is in synchronous with the generation of the start pulse SP-2. Thus, the mode for executing the initial program 702-0 (see Figure 7) is established with the mode "INITIAL PROGRAM" shown in the row e). This initial program is available for loading initial values in the device (RAM).The initial values are the constant like 0, 1 and so on which are used in the operation.

After executing the initial program, a mode of "IDLE" state (see the row e) ) follows. At the beginning of the start pulse SP-5, the sequence signal SS-2 appears (see the row b) ). The sequence signals SS-2, SS-1 and SS-0 are provided from, for example, the aforesaid sequence controller 121 (163) of the MODEMs shown in Figure 1. Then the processing system executes the usual program 702-2, the head address of which program 702-2 is designated by the head address ADb (see Figure 7). The usual program 702-2 is executed in a duration X shown in the row d). In the duration X, the usual program 702-2 is executed repeatedly so as to operate, for example, the aforesaid arithmetic function A x B + C cyclicly, in synchronous with the start pulses, every time each five steps (g,...... (0 elapse.This is because, a head address ADb (see 702-3 in Figure 7) existing at the end of the program 702-2, designates the head of the same program 702-2.

Figure 9 is a circuit diagram of a hardware for executing the above mentioned initial starting of the program to be processed by the processing system. In Figure 9, the program counter 409 and the RAM address buffer register 407 have already been explained. Also, the sequence signals SS-0 and SS-1, the wait instruction "WAIT", the start pulse SP, the processing phases PH1 through PH5 and the external selection signal (SYS1, SYS2), have already been explained. The reference numerals 905 through 910, respectively, representflip4lops. The reference numerals 911 through 915, respectively represent NAND gates. The reference numerals 916 through 921, respectively, represent AND gates. The reference numerals 922 through 926, respectively represent NOR gates. 927 represents a coincidence circuit (EXCLUSIVE NOR).The numerals 928 through 933, respectively represent NOT gates. 934 represents a kind of OR gates. Figure 1 OA depicts timing charts used for explaining the operation of the hardware shown in Figure 9. The waveforms of signals (i)through~ appearing at respective portions in the hardware of Figure 9, are illustrated, respectively, in rows a) through n) of Figure 1 OA. In Figure 9, when the sequence signal SS-0 (~) is logic "1 " (see a row a) ), the program counter 409 is cleared (corresponding to the address "00" (see Figure 7) of the control storage 430).Therefore, the wait instruction "WAIT" ( @ ) which is logic "0", is produced (see a row i) ) and the Q-output signal~ of the flip-flop 907 becomes logic "1 " (see a row h) ). Next, the sequence signal SS-1 0is provided (see a row a') ). A signal Q from the NAND gate 911 has logic "0", after which the start pulse SP-3 (i) (see a row b) ) is generated and also the sequence signal SS-1 is logic "1". In the duration when the signal Q is logic "0" (see a row c) ), the AND gate 916 produces logic "0". A signal (j) from the NAND gate 912 is created by differentiating the sequence signal SS-1 and becomes logic "0" from the time when the start pulse SP-1 is generated to when the start pulse SP-2 is generated.Therefore, on one hand, the output of the AND gate 916 is caused to be logic "0" by a signal~. On the other hand, the signal~ is used as a start signal for clearing all the contents of the RAM address buffer register 407 (refer to "CLEAR RAM" in the row e) of Figure 8). A signal Q from the NOR gate 923 is created by differentiating the start pulse in synchronous with the clock signal CLK generated at the processing phase PH3 (see a row e) ).The clock signal CLK, the start pulse SP, the processing phase, and also the signals Q, ~, 3 are depicted in Figure 1 OB. However, Figure 1 OB is depicted by using an expanded scale of elapsed time compared to the scale used in Figure 1 OA.

In Figure 9, a signal (ij) from the Q-output of the flip-flop 907 is used for determining the provision of the count - enable signal CE (refer to the row f) of Figure 6) for activating the program counter 409. The signal (ji) becomes logic "0" in synchronous with the start pulses and the clock signals, and the signal @ has the waveforms as shown in the row h) in Figure 1 OA. As a result, a signal~, that is the count enable signal CE is obtained, which has the waveforms as shown in row m). A signal @ (see a row g) of Figure 1 OA and Figure 10B) from the AND gate 917 is used as a clock signal of the flip-flop 907, which clock sgnal is generated after the time when the count enable signal is provided and also after the start pulse is generated. Since the signal (i) has a relationship with the signal by means of the AND gate 917, a clock signal per each start pulse is produced. A signal ~ from the NAND gate 914 is logic "1" corresponding to the external selection signals SYS1 and SYS2 in the duration (see a row I) ). It is provided as an elongated clock signal 2 for the system selection in the duration between the start pulses SP-1 and SP-2 when the sequence signal SS-1 is provided.

This NAND gate 914 receives a signal (3from the OR gate 934. The signal~ is a clock signal used for executing the system selection (refer to the duration V in the row d) of Figure 8 and the area 700 in Figure 7).

This OR gate 934 produces sequential clock signals generated in synchronous with the processing phases PH3, PH4, PH5 and PH1 under the relationship with the aforesaid external selection signals SYS1 and SYS2.

The signals SYS1 and SYS1/4 DETERMINE WHICH SYSTEM, FOR EXAMPLE, & /4?? BIT1/3S TYPE MODEM, 7200 bit/s type MODEM or 4800 bit/s type MODEM, is to be selected. When logics of the signals SYS1 and SYS2 are preset to be ("0""0"), ("0""1"), ("1 ", "0") and ,"1"),thenumberoftheaforesaidsequential clock signals, generated in synchronous with the processing phases PH3, PH4, PH5 and PH1 are, for example one, two, three and four, respectively. A signal (3 from the AND gate 916 is a load pulse of the program counter which is made by differentiating the start pulses except for SP-1, SP-3 and SP-4. A signal (3 from the NAND gate 913 is caused to be a logic "1 " signal so as to count up the program counter in the duration except for D4.A signal ~from the NAND gate 915 (see a row n) ) is an inverted pulse signal of a signal~ in synchronous with PH4 signal. A row 0) indicates durations D1 through D6. D1 corresponds to a duration for clearing the content of the program counter 409, D2 to a duration for clearing the device 420 and also carrying out the system selection, D3 to a duration for executing the initial program D4 to a duration of the "IDLE" and D5 to a duration for executing the usual program. D6 is identical with D5.

Since the system selection is carried out by using the external selection signals SYS1 and SYS2, the selection is achieved not by a software mode but by a hardware mode. The hardware is the aforesaid detecting circuit comprised of the gate members located at the input stages of the signals SYS1 and SYS2.

Therefore, the volume of the instructions which must be loaded in the control stage (ROM) 430 is considerably reduced.

The RAM address register 407 shown at the bottom in Figure 9 acts, on one hand, as a register for storing the RAM addresses and, on the other hand, as a scrambler by cooperating with the gates 925,926,927 and the flip-flop 910. A line 951 acts as a serial input line for a first input stage and a line 952 acts as an output line from a fifth output stage so that the scrambler produces (29-1) random patterns. This scrambler is available for clearing all the contents of the storage device (RAM) 420 (refer to "CLEAR RAM" in the row e) of Figure 8).

The register 407 is utilized as the scrambler when the signal ~ (see the row d) of Figure 1 0A) having logic "0" is applied to a control terminal 953 thereof. When the signal is logic "1", the register 407 is operated as the RAM address register. It should be noted that the register 407 may also be comprised as a counter, instead of a scrambler, for clearing all the contents of the device (RAM) 420.

Returning to Figure 1, the MODEM must be operated under the real time processing mode. For example, both the automatic equalizer 154 and the carrier phase tracking circuit 153 must process each respective input data one by one intermittently with a frequency of, for example 2.4 KHz. The roll-off filters 113, 114, 155, 156, the modulating means (115 through 118), the demodulating means (157 through 159) and the timing signal extracting circuit 165 must process each respective input data one by one intermittently with a frequency of, for example 9.6 KHz. Regarding the above mentioned real time operation mode, one problem is raised that must be solved.The problem is that the length of the duration in which the processing of each input data is completed, is much shorter than the length of the period at which these input data are supplied, and, accordingly, undesired idling times are intermittently created in the digital signal processing system shown in Figure 4. Therefore, the so-called NOW (NO Operation) instruction must be executed during each idle time. However, the control 430 should further store a great number of meaningless data in order to run the NOP instruction, and accordingly, the storage (ROM) 430 must be designed to be a storage having a large capacity for accomodating the great number of meaningless data therein. However, such a large capacity storage (ROM) 430 is not desirable from an economical viewpoint.

For the purpose of solving the abovementioned problem in the present invention, unique method is further employed. The method is comprised of the following steps: a) holding the program counter 409 to be in a non-incremental accessing state after which a wait instruction is provided from the storage (ROM) 430; b) creating sequential and divisional programs in the storage (ROM) 430, which programs process for the respective input data; c) locating the above mentioned wait instruction at each end of the above mentioned sequential and divisional programs, and; d) executing the divisional program for processing the next new input data by doing the incremental accessing in the program counter 409 after which the wait instruction is executed and also when a corresponding restart pulse RSP is generated.

The above mentioned method will become more apparent from the following description. Figure 11 depicts timing charts used for explaining the above mentioned unique method. In Figure 11, sequential usual programs to be executed are shown in a row b). These usual programs correspond to the usual program 701-2 or 702-2 shown in Figure 7. Each usual program starts running every time the aforesaid start pulse SP is generated (see SP in a row a) ). The input data DT1, DT2, DT3... are intermittently provided, as shown in a row c). As previously mentioned, since the length of each duration in which the processing of each input data is completed, is much shorter than the length of the period at which these input data are supplied, an undesired idling time is created in each period at which the input data is supplied.Figure 12 illustrates a flow of programs loaded in the ROM 430, according to the present invention. The reference numerals 1201-1, 1201-2, 1201-3... represent a first divisional program (put1), a second divisional program (pt2), a third divisional program (pt3) ..., respectively. The divisional programs (put1, pt2, pt3...) process, respectively, the intermittent input data DT1, DT2,DT3.... These processes are indicated by the reference symbols ptl, pt2, pt3... in a row d) of Figure 11. At each end of the divisional programs (tl,t2, t3 ...), wait instructions "WAIT" 1202-1, 1202-2, 1202-3 ... are located at the respective addresses e, m, n ... shown on a left side in Figure 12.

The wait instructions "WAIT" stop the execution of program at each end of the divisional programs (refer to the reference symbol "W" in the row d) of Figure 11). Every time the wait instruction is executed, the digital signal processing system is left in an idle state (see the term "IDLE" in the row d) of Figure 11. The idle state is released every time the aforesaid restart pulse is generated (refer to the reference symbol RSP in a row e) of Figure 11) and at the same time the next divisional program starts running. The reference numerals 1203-1, 1203-2, 1203-3 ... represent reset instructions "RESET", located at addresses (t+1), (m+1), (n+1) ....

The reset instruction "RESET" is available only at the time when the start pulse SP is generated. Accordingly, the addresses (#+1),(m+1),(n+i)... are dummy addresses, as far as the reset pulse RSP is being generated.

Thus, when the start pulse SP is generated, the start address is loaded in the program counter 409, which instruction specifies predetermined one address "08" in the counter 409 in this case. Thereafter, the usual program again starts running from the initial step stored at the specified address "08" (see 08 in Figure 12).

The processes for dealing with wait instruction "WAIT", in connection with the clock signals, the ROM address data (RA), the ROM output data (RO), start pulses SP, the count enabling signal CE, the counter preset signal CP, the processing phase PH1 through PH5 and so on, are identical with the processes which have been already explained with reference to Figure 6.

The above mentioned wait instuction in each divisional program and the start pulse SP are very useful, respectively, for creating the idle state "IDLE" (see the row d) of Figure 11) and for reseting the usual program repeatedly to its initial step. However, the start pulse SP cannot be used as a pulse for sequentially starting the processes of the divisional programs t1,t2,t3... one by one. This is the reason why the restart pulses RSP are introduced into the processor.That is, the restart pulses RSP can be used for sequentially starting the processes of the divisional programs t1,t2,t3.... In Figure 12, the reset instructions "RESET" being located at the addresses (f+1), (m+l ), (n+l) ... are available only when the start pulses SP are generated in order to return back to the initial step of the usual program repeatedly, while program areas 1204-1, 1204-2, 1204-3 ... being located, respectively, at addresses (6+2), (m+2), (not2) ... are available every time the restart pulse RSP is generated so as to continue processing the next divisional program after the lapse of the preceding idle state.The addresses (6+2), (m+2), (n+2)... respectively specify the head addresses of the divisional programs t1, t2, t3....

Figure 13 illustrates a circuit diagram of one example of a hardware for carrying out the above explained unique method employed preferably in the processor. This hardware is mounted in the instruction decoder 404 shown in Figure 4. Figure 14 depicts a timing chart used for explaining the processes of this unique method. In Figure 14, the contents of rows a) through d) are identical with the contents of the rows a) through d) of Figure 6, respectively, and also the contents of rows e) through i) are identical with the contents of the rows i) through m) of Figure 6. In Figure 14, the ROM output data RO-1 (see the row c) ), which is specified by the ROM address data RA-m (see the row b) in Figure 14 and also the address "m" in Figure 12) is the wait instruction.Thereafter, the incremental access to the control storage (ROM) 430, by the program counter 409, is stopped from being executed, as has already been explained with reference to Figure 6. At this time, the ROM output data RO-2 (see the row c) ) specified by the ROM address data RA-(m+1) (see the row b), has been produced from the control storage (ROM) 430. In a case where the restart pulse RSP is generated, since the address (m+1) acts as the dummy address, the next address (m+2) #2)becomes effective. Consequently, the program counter 409 further continues the execution of the incremental access to storage (ROM) 430 again, in synchronous with, for example, the processing phase PH4 (see the row h) ). Then, the address (m+2) specifies the initial step of the divisional program Pt3 (see Figure 12).Although the ROM output data RO-2 is loaded when the start pulse is generated in the program counter 409 by executing the preset operation to this counter 409, this data RO-2 is not loaded when the restart pulse RSP is generated in the program counter 409, because the preset operation is not executed by this restart pulse RSP.

In Figure 13, the reference numerals 1302 through 1304 represent flip-flops, 1305 represents an AND gate, 1306 represents a NAND gate,-1307 represents a NOT gate, and 1308 and 1309 represent NOR gate. The reference symbols "WAIT", "CLK" (clock signal), "SP", "RSP", "PH3", "PH4", and "CE" have already explained. The reference symbol "PE" from the NAND gate 1306 indicates a preset enable signal, which signal "PE" allows the program counter 409 to execute the above mentioned preset operation so as to specify the initial step of the usual program repeatedly in synchronous not with the restart pulse RSP, but with the start pulse SP.

When the ROM output data RO-1 specifies the wait instruction "WAIT", then the flip-flop 1302 is reset by this instruction "WAIT". As a result, the count enable signal CE, applied to the program counter 409, becomes logic "0" (see the row m) of Figure 14). Accordingly, the incremental access to the control storage (ROM) 430 by the counter 409, is stopped from being executed, during the existence of logic "0" of the count enable signal CE. In this case, when the restart pulse RSP is generated (see a row j) of Figure 14), this restart pulse RSP from the NOR gate 1308 is differentiated by a differentiating circuit comprised of the flip-flops 1303, 1304 and the NOR gate 1309 in synchronous with the clock signal produced at the generation processing phase PH3.The differentiated restart pulse RSP' (see a row k) of Figure 14) is produced from the NOR gate 1309 and applied to the AND gate 1305. The AND gate 1305 produces a clock signal to be applied to the flip-flop 1302, in synchronous with both the processing phase PH4 (see the row h) of Figure 14) and the inverted clock signal CLK (see the row a) of Figure 14) by means of the NOT gate 1307. Clock signal to be applied to the flip-flop 1302, is shown in a row{) of Figure 14. As a result, the program counter 409 continues the incremental access to control storage (ROM) 430 again and executes the next divisional program t3 (see Figure 12). The program counter 409 specifies the address (m+1) at the time when the wait instruction "WAIT" (see the reference numeral 1202-2 in Figure 12) has been executed.Therefore, when the program counter 409 continues the incremental access to the control storage (ROM) 430 again, the program counter 409 specifies the address (m+2). This address (m+2) specifies the initial step of the divisional program t3 (see Figure 12). Contrary to the above, when the start pulse SP is generated, the start pulse SP directly activates the NAND gate 1306, which gate 1306 also receives the outputs from the Q output of the flip-flop 1302, a differentiated start SP from the NOR gate 1309 and the signal corresponding to the processing phase PH4. As a result, the preset enable signal PE is produced from the NAND gate 1306. The preset enable signal PE causes the program counter 409 to preset the ROM output data RO-2 (see the row c) of Figure 14) therein.

The count enable signal CE is created when either the restart pulse RSP or the start pulse is generated; however, the preset enable signal PE is created only when the start pulse SP is generated. Thus, the above described unique method is very useful for operating each intermittent input data in a very short time and for creating each idle state for a little time immediately after the completion of each operation of said intermittent input data, as occurs in the MODEM, without increasing the capacity of the ROM 430.

Figure 15 is a block diagram of improved MODEM shown in Figure 1, which improved MODEM is constructed by utilizing the digital signal processing system according to the present invention. In Figure 15, the reference numerals 1510 and 1550 respectively represent the improved MODEM shown in Figure 1. In Figure 15, members which are referenced by the same reference numerals and symbols as those of Figure 1, are identical members. It is important to understand that the MODEM is fabricated by eight chips of LSls which are classified into only three different kinds of LSls.In Figure 15, a first type of LSI (XMT) is indicated by the reference numeral 1501, a second type of LSI (REC) is indicated by the reference numeral 1502 and a third type of LSI (ALU: Arithmetic and Logic Unit) is indicated by the reference numerals 1503-1, 1503-2, 1503-3, 1503-4, 1503-Sand 1503-6, which are also referenced by the reference symbols ALU1, ALU2, ALU3, ALU4, ALU5 and ALU6. Thus, the MODEM is fabricated by eight chips of LSls classified into only three kinds of LSls (1501), (1502) and (1503-1 through 1503-6). The LSls 1503-1 through 1503-6 have the completely same construction.Each of the LSls ALU1 through ALU6 is constructed by members which are identical with the members shown in Figure 4 except for the members 420 and 430. Each of the ROMs and RAMs which cooperate with the respective LSls ALU 1 through ALU6, is identical with the control storage (ROM) 430 and the storage device (RAM) 420 shown in Figure 4. The ALU 1 of Figure 15 is substituted for both the roll-off filters 113,114 and the modulating means (115through 118) of Figure 4. The ALU2 and ALU3 of Figure 15 are substituted for the combination of the roll-off filters 155,156, the demodulating means (158,159) and the timing signal extracting circuit 165 of Figure 1. The ALU4 and ALU5 of Figure 15 are substituted for the automatic equalizer 154 of Figure 1.The ALU6 of Figure 15 is substituted for both the carrier phase tracking circuit 153 and a part of the automatic equalizer 154 of Figure 1. The remaining members of Figure 1 are mounted on the LSI (XMT) 1501 or the LSI (REC) 1502. The reference numerals 1521 and 1522 represent ROMs being cooperated with the LSI (XMT) 1501 and the LSI (REC) 1502, respectively. The reference numeral 440 represents the common bus as shown in Figure 4. The reference numerals 1524 and 1523 respectively represent a comparator and a digital/analogue converter (D/A).

While the invention has been particularly shown and described with reference to a preferred embodiment thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and detail may be made therein without departing from the spirit and scope of the invention.

Claims (8)

1. A digital signal processing system which executes the same arithmetic function repeatedly, comprising: an arithmetic unit for processing each of the arithmetic functions; an instruction decoder which controls the arithmetic unit. an input/output data selector for selecting one of the input and output data to be provided to and from the arithmetic unit; a storage device (RAM) for storing various data to be supplied to the arithmetic unit; a control storage (ROM) for storing data including instruction codes to be supplied to the instruction decoder, and; a program counter for executing incremental access to the control storage (ROM), wherein the digital signal processing system is operated by the steps of, a. forming a data set composed of the instruction code and a fixed number of data to be processed in accordance with the instruction code and storing the data set in the control storage (ROM), b. arranging serially a data input cycle, an arithmetic operation cycle and a data ouput cycle in each time slot, c. allotting parallelythe data input cycle of the (k+1 )th (k=0,1,2,3 ...) time slot, the arithmetic operation cycle of the (k)th time slot and the data output cycle of the (k-1 )th time slot, fixedly into same duration and, d. executing the data input cycle of the (k+l)th time slot, the arithmetic operation cycle of the (k)th time slot and the data output cycle of the (k- 1 )th time slot in accordance with, respectively, the (k- 1 )th data set, the (k)th data set and the (k+i )th data set.

2. A system as set forth in claim 1, wherein a RAM address buffer register is connected to the storage device (RAM) for momentarily storing the data produced from the control storage (ROM), the control storage (ROM) stores the data set including the data to be processed in accordance with the corresponding instruction code, which data is either the input data itself to be supplied to the arithmetic unit or the address information data used for an access to the storage device (RAM), the RAM address buffer register momentarily stores the data produced from the control storage (ROM), irrespective of the input data itself and the address information data, the input data itself is directly applied to the arithmetic unit, while the address information data is applied to the storage device (RAM) and the data specified by the address information is applied, as an input data itself, from the storage device (RAM) to the arithmetic unit.

3. A system as set forth in claim 1 or 2, wherein a means for modifying at least a part the bit pattern of the data to be processed in accordance with the instruction code, this means being located between the output of the control storage (ROM) and the input of the RAM address buffer register and being activated by an external control data (ECD).

4. A system as set forth in claim 1, 2 or 3, wherein the instruction code of the data set can also be used as an instruction code which commands a provision of an external data (EXT) to or from the arithmetic unit, the data of the data set to be processed in accordance with the instruction code is an address information data to be applied to the storage device (RAM) at which address the external data (EXT) is stored by means of an output data selector connected between the arithmetic unit and the storage device (RAM).

5. A system as set forth in claim 1, wherein the digital signal processing system is operated by the steps of, a. controlling the program counter by the instruction code stored in the control storage (ROM) so as to maintain the program counter to be in a state where no incremental access to the control storage (ROM) is executed, b. creating, in the control storage (ROM), a system selection area used for initially specifying an object to which the digital signal processing system is applied, an initial program processing area used for storing initial values of the object and a usual program processing area used for executing the same arithmetic function repeatedly, c. specifying the object of the system selection area by means of a detecting circuit in accordance with an external selection signal (SYS), d. clearing, in the same duration of the above step c, all the contents of the storage device (RAM), e. starting the initial program of the initial program processing area, subject to the last step of the system selection, which last step designates the head address of the inital program, f. starting the usual program of the usual program processing area, subject to the last step of the initial program, which last step designates the head address of the usual program, the last step of the usual program designates the head address thereof so that the usual program is executed repeatedly.

6. A system as set forth in claim 5, wherein the RAM address buffer register is operated either by a register or by a scrambler, the scrambler being used for clearing all the contents of the RAM in the step d.

7. A system as set forth in claim 5, wherein the digital signal processing system is operated by the steps of, a. dividing the usual program processing area into a plurality of divisional program processing areas, the divisional programs being executed with respect to the respective input data being supplied sequentially, b. attaching respective wait instruction areas to each end of the divisional programs, the wait instruction giving the command to stop every time the execution of the divisional program is completed, c. attaching both a first head address specifying area and a second head address specifying area to each end of the wait instruction areas, the first head address designating the initial step of the usual program, the second head address designating the initial step of the next divisional program, d. generating start pulses, the usual program starts being processed in synchronous with each start pulse, further the first head address specifying area being available every time each start pulse is generated and, e. generating restart pulses, the divisional program starting being processed in synchronous with each restart pulse, further the second head address specifying area being available every time each restart pulse is generated.

8. A digital signal processing system substantially as hereinbefore described with reference to the accompanying drawings.