JPS5847054B2 - Data processing equipment for digital signal processing - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a data processing device for digital signal processing, particularly a data processing device for digital signal processing in which a function such as an automatic equalizer in a data transmission/reception system is executed by the data processing device. , arithmetic cycles, and data output cycles are fixedly assigned in advance to the same time width, and instructions including instruction codes are prepared as a data set, and predetermined arithmetic processing is repeated while performing overlap processing. The present invention relates to a data processing device for digital signal processing.

In digital signal processing in the communication field, as typified by digital filters, the basic calculations are multiplication and cumulative calculations, and there is relatively little decision-making and branching processing as in general data processing.

In many cases, such processing can repeatedly execute a single sequence according to a microprogram.

A processor that performs such processing is highly required to perform real-time processing, and one important point is to improve the efficiency of data processing.

Conventionally, in the case of a processor that performs general processing, in performing one arithmetic process, (i) decodes an instruction, then reads appropriate data, then executes the operation, and (1)
1) It also decodes the instructions to be transferred to the outside and then outputs the processing results.

For this reason, all processing is done in series, resulting in poor processing efficiency.

Furthermore, since the number of cycles required for each type of instruction is different, it has the disadvantage that it is extremely time-consuming when microprogramming or modifying a sequence.

The present invention aims to solve the above-mentioned problems, and aims to efficiently perform so-called pie-line processing by taking into consideration the route and data format for supplying RAM data, ROM data, EXT data, etc. In a data processing system that repeatedly executes a predetermined arithmetic process, the data processing device for digital signal processing of the present invention is used. an instruction decoder that controls according to an instruction code; an input/output data selector that interprets input/output data for the arithmetic unit; a storage device that stores input data for the arithmetic unit; and an instruction containing an instruction code for the instruction decoder. an access address buffer corresponding to the storage device, and a bit modification that modifies at least part of the data input to the access address buffer in correspondence with the access address buffer. a data input cycle to the arithmetic unit, an arithmetic cycle in the arithmetic unit, and a data output cycle from the arithmetic unit are fixedly assigned to the same time width, respectively, and the instruction is set as a data set to The commands given in the data set, which are divided into multiple cycles and assigned to classification information corresponding to the divided cycles, include instruction codes for instructing to send and receive data to and from an external device. When inputting data, storage address information in the storage device in which the data should be stored is set in the classification information, and when outputting data to an external device, the data is set in the classification information, In processing the above instruction, the classification information of the instruction given in the data set is read from the control memory in correspondence with the classification cycle, and the read information is modified based on external control by the pit modification means. Then, if the classification information of the instruction is the input data itself to the calculation unit, it is input to the calculation unit via the access address buffer, and the instruction is If the classification information is access address information to the storage device, control is performed so that the read data resulting from accessing the storage device is supplied as input data to the calculation unit, and the data input cycle and the calculation are performed. The output cycle in the (i-1)th process and the above calculation cycle in the (i+1)th process overlap temporally with the calculation cycle period in the first process consisting of the output cycle and the output cycle. It is characterized by being configured so that it is executed in parallel with the input cycle.

This will be explained below with reference to the drawings. FIG. 1 is an explanatory diagram for explaining overlap processing according to the present invention, FIG. 2 is an explanatory diagram for explaining a data set used in the present invention, and FIG. FIG. 4 shows an explanatory diagram for explaining the operation of the configuration shown in FIG.

In the data processing device of the present invention, a data input cycle CYL1, a calculation cycle CYL2, and a data output cycle CYL3 are divided in correspondence to one calculation process, and each cycle is preliminarily set to have the same time width. Fixedly assigned.

As shown in FIG. 1, during the execution period of arithmetic cycle CYL2 in the first process, data output cycles CYL3 and (i+1) in the (i-1)th process are executed.
The data input cycle CYL1 in the second processing is temporally overlapped and processed in parallel.

An important point in configuring a processor that performs overlap processing is how many steps are taken in one cycle in order to complete different processing within the same time.

The parameters that determine this are given by the calculation algorithm and data input/output transfer format.

For example, if an algorithm that requires relatively long steps, such as serial multiplication processing, is employed, there is no advantage in processing data input/output transfers in an overlapping manner as described above.

Conversely, if parallel multiplication processing is used that completes processing in one step, many steps will be required for data input/output transfer, and in order to perform the above overlap processing, the arithmetic processing itself must be multiplexed. It happens.

The type of overlap processing to be performed is selected depending on the scale and processing speed of the hardware that can be employed.

In one embodiment of the present invention, when the arithmetic processing in the arithmetic section is x x y + z, let us consider, for example, the case where the arithmetic cycle is five steps.

At this time, it is necessary to efficiently read instruction codes, supply input data, etc. within the five steps.

FIG. 2 is an explanatory diagram illustrating a data set used in the present invention. In order to correspond to the above five steps, the instruction code 1 byte, the upper 1 byte (word A) such as the 6 multiplicand,
It consists of the following 1 byte (word B) such as a multiplicand, the upper 1 byte (word C) such as a multiplier, and the lower 1 byte (word D) such as a multiplier.

Then, one byte each is read out from the control memory in correspondence with each step.

Of course, the present invention is not limited to the structure of the data set described above.

FIG. 3 shows the configuration of an embodiment of the data processing device of the present invention.

In the figure, 1 is a program counter, 2 is a control memory in which the data set shown in FIG. 2 is stored, 3 is a decoder buffer in which the instruction code shown in FIG. 2 is set, 4 5 is an instruction decoder which decodes the contents of the decoder buffer and performs control as shown by the dotted line in the figure. 5 is a storage device access address buffer which corresponds to words A, B, and C shown in FIG.

6 is a storage device in which operand data is stored; 7 is an input/output data selector that selects input/output data for the arithmetic section; 8 is an arithmetic section; For example, the above operation xX
y+z, 9 is a data selector which corresponds to the bit modification means according to the present invention, and 10 is an output data selector which selects output data.

The operation will be explained below with reference to FIG.

The clock shown in FIG. 4 is generated in response to the steps described above, and the control memory 2 is accessed based on the contents of the program counter in response to the clock "1" shown in the drawing, and the first data The set instruction code (FIG. 2) (instruction-1) is read.

The instruction-1 is decoded by the instruction decoder 4 via the decoder buffer 3 in synchronization with clock "2".

The period of clocks "2" to "6" becomes the valid period of instruction-1 (the process instructed by instruction-1 is calculated).

On the other hand, at the same clock "2", the word A shown in FIG.
The reading from the control memory 2 is performed.

Then, at clock "3", the data is set in the access address buffer 5, and at the same time, word B shown in FIG. 2 is read from the control memory 2.

Thereafter, word CD is similarly read out by clock "6".

The above words A and C are access address buffer 5.
Words B and D are set in access address buffer 5 via selector 9.

Word A corresponding to the multiplicand. B is its own calculation unit 8
When the words A and B are operand data to be operated on in the input/output data selector 7, the words A and B are directly supplied from the access address buffer 5 to the operation unit 8 via the input/output data selector 7.

In addition, when words A and B corresponding to the multiplicand are access address information of the storage device 6, the storage device 6 is accessed based on the words A and B, and the operand data read from the storage device 6 becomes the multiplicand. The data is supplied to the arithmetic unit 8 via the input/output data selector 7.

Word A. Whether B is the operand data itself or access address information, once it is set in the access address buffer 5, the timing at which the operand data is supplied to the arithmetic unit 8 as a multiplicand is determined. The signals are combined and received by the arithmetic unit 8 by the rising edge of the clock "5" as shown in FIG.

Regarding words C and D corresponding to multipliers, the above words A,
This is similar to B, and as shown in FIG. 4, it is received by the arithmetic unit 8 by the rising edge of clock "7".

In the case of the configuration shown in FIG. 3, no latch buffer is provided for data read out from the storage device 6.

For this reason, from the time the access address information is set in the access address buffer 5, the memory device 6
From then on, the read data is supplied to the input/output data selector 7 in the form of a flow as shown RAM data.

On the other hand, needless to say, the contents of the access address buffer 5 are also supplied to the input/output data selector 7 as illustrated ROM data.

Then, both are selected by the selector 7 and supplied to the arithmetic unit 8.

. In this state, that is, at clock "7", the instruction code (instruction-2) in the second data set is decoded by the instruction decoder 4, so that the instruction code (instruction-2) in FIG. The second time slot begins as follows, and based on this, the above word A (A-1)
, B (B-1), C (C-1), and D (D-1).

That is, it takes five steps shown as "second time slot" in FIG.
, D-1) are performed and the data 2 already obtained is added, and the above-mentioned operation x x y + z is performed.

During this time, the next word A (A-2) is processed as shown in FIG.

B (B-2), C (C-2), and D (D-2) are calculation units 8
will be supplied to.

That is, the above-mentioned overlap processing is performed.

Also, the data set read from control memory 2 (second
(Figure) classification information (instruction code, words A, B, C2D)
Regardless of whether it indicates a direct operand or data or indicates access address information for accessing the storage device 6, the access address
By setting it in the buffer 5, the operand data supplied to the arithmetic unit 8 can be provided in synchronization with a predetermined clock.

Note that the "effective period of instruction-1" shown in FIG. 4 can be considered to be the period during which the data corresponding to the data set shown in FIG. The "time slot" may be considered to be a period corresponding to the cycle shown in FIG.

Then, for example, word A (A-1) is supplied to the arithmetic unit 8 at the rising edge of clock "3".

Words B (B-1), C (Cl), D (D-1), etc. are also supplied in a similar manner with a delay of one clock.

As mentioned above, operand data is generally supplied from the control memory 2 or the storage device 6 to the arithmetic unit 8, but the data supplied to the arithmetic unit 8 is determined from the location of the data (
i) data stored in the control memory 2 (ROM data), (ii) data stored in the storage device 6 (
RAM data), 11i) Data from external device (E
(XT data), (iV) calculation unit cover sofa (not shown)
data from (D data), (V) calculation manual buffer (
There is data from (not shown) and (E data).

In the case of the ROM data and 7RAM data, as described above, the EXT data, D data, and E data are input and output via the input/output data selector 1 shown in FIG.

While input/output transfer is performed regarding the EXT data, D data, and E data, there is no need to read operand data from the storage device 6i.

Using this time, the output data selector 10 shown in FIG.
Writing to the storage device 6 is performed via the .

As described above, the data processing apparatus of the present invention performs sequential processing based on a series of data sets stored in the control memory 2.

Therefore, once the data set sequence described above is stored in the control memory 2, only fixed processing can be executed.

This causes inconvenience when it is desired to switch the coefficient data in the storage device 6 using the same data set sequence, for example, to perform digital filter processing in a time-division manner or to change filter characteristics. .

In order to solve this problem, in the case of the present invention, a selector 9 shown in FIG.
The contents of the lower byte set in the buffer 5 can be replaced by an external control signal as necessary.

By doing this, even if the partition information of the data set read from the control memory 2 remains as it was,
It becomes possible to change the operand data supplied to the arithmetic unit 8.

Furthermore, as mentioned above, it is necessary to send and receive EXT data to and from an external device.

For this reason, a code instructing data transmission/reception with an external device is prepared as an instruction code in the data sent shown in FIG.

This causes a transmit word to be sent to the external device to notify this fact.

The external device decodes the word, identifies the predetermined type of data, and sends the data to or takes in the data from the data processing device.

In other words, a transmit word is placed at a predetermined phase within a data set, and when the data processing device receives data, it sends the address of the storage device 6, which is the storage destination, and when it sends the data, it sends the address of the storage device 6. The data will be written into the data set.

As explained above, according to the present invention, arithmetic processing in a data processing device is divided into a data input cycle, an arithmetic cycle, and a data output cycle, and fixedly allocated so that they are completed within the same time, so-called Iterative operations are performed while performing overlap processing.

Even if there is a time loss that may occur due to fixed allocation of processing cycles in this way, it is convenient overall when performing processing in which digital signals are repeatedly operated.

Also, for the calculation unit, ROM data, RAM data, E
Since XT data, E data, etc. can be arbitrarily supplied, and the data set in the access address buffer can be bit-modified, flexibility such as changing calculation data can be provided.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram for explaining overlap processing according to the present invention, FIG. 2 is an explanatory diagram for explaining a data set used in the present invention, and FIG. FIG. 4 shows an explanatory diagram for explaining the operation of the configuration shown in FIG. In the figure, CYL1 to CYL3 are cycles, 1 is a program counter, 2 is a control memory, 4 is an instruction decoder, 5 is a storage device access address buffer, 6 is a storage device, 7 is an input/output data selector, 8 is the calculation part,
9 represents a bit modification means.

Claims (1)

[Claims] 1. In a data processing system that repeatedly executes predetermined arithmetic processing, an arithmetic unit that performs the predetermined arithmetic processing, an instruction decoder that controls the arithmetic unit according to an instruction code from a control memory, and an instruction decoder that controls the arithmetic unit according to an instruction code from a control memory. an input/output data selector for selecting input/output data, a storage device for storing at least input data for the arithmetic unit, a control memory for storing instructions including instruction codes for the instruction decoder, and an access address corresponding to the storage device. - A buffer, and a bit modification means for modifying at least part of the data input to the access address buffer corresponding to the access address buffer, and a data input cycle for the arithmetic unit and a bit modification means for modifying at least part of the data input to the access address buffer. The arithmetic cycle in and the data output cycle from the arithmetic section are fixedly assigned in advance to the same time width, and the above-mentioned instruction is assigned as a data set to segmentation information corresponding to a plurality of segmented cycles into which the cycle is segmented. Therefore, the command given in the above data set includes an instruction code that instructs to send and receive data to/from an external device, and when inputting data from an external device, the data should be stored in the above classification information. The storage address information in the storage device is set, and when outputting data to an external device, the data is set in the classification information, and when processing the instruction, the instruction given in the data set is The classification information is read from the control memory in accordance with the classification cycle, the read information is modified based on external control by the bit modification means, and is once set in the access address buffer. If the instruction classification information is the input data itself to the arithmetic unit, it is input to the arithmetic unit via the access address buffer, and the instruction classification information is access address information to the storage device. In this case, the read data resulting from accessing the storage device is controlled to be supplied as input data to the arithmetic unit, and the above in the first process consisting of the data input cycle, the arithmetic cycle, and the output cycle. The method is characterized in that the output cycle in the (i-1)th process and the input cycle in the (i+1)th process are executed in parallel, overlapping in time with the calculation cycle period. A data processing device for digital signal processing.