US4894708A - LSI package having a multilayer ceramic substrate - Google Patents

LSI package having a multilayer ceramic substrate Download PDF

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Publication number
US4894708A
US4894708A US06/630,266 US63026684A US4894708A US 4894708 A US4894708 A US 4894708A US 63026684 A US63026684 A US 63026684A US 4894708 A US4894708 A US 4894708A
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United States
Prior art keywords
input
substrate
pads
spare
output terminals
Prior art date
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Expired - Lifetime
Application number
US06/630,266
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English (en)
Inventor
Toshihiko Watari
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NEC Corp
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NEC Corp
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Assigned to NEC CORPORATION, 33-1, SHIBA 5-CHOME, MINATO-KU, TOKYO, JAPAN reassignment NEC CORPORATION, 33-1, SHIBA 5-CHOME, MINATO-KU, TOKYO, JAPAN ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: WATARI, TOSHIHIKO
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0286—Programmable, customizable or modifiable circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49004—Electrical device making including measuring or testing of device or component part

Definitions

  • the present invention relates to an LSI (large scale integrated) package having a multilayer ceramic substrate mounted densely with a plurality of integrated circuit (IC) chips.
  • LSI large scale integrated
  • High density LSI packages using alumina ceramic substrates are in use recently in high performance computers.
  • the package includes densely wired layers formed on the upper surface of the ceramic substrate, a number of IC chips mounted densely on the upper surface of the top wiring layer, and a plurality of pin-shaped input/output (I/O) terminals arranged in matrix form on the lower surface of the ceramic substrate. Since the ceramic substrate has a thermal expansion coefficient well matching that of the silicon, which is the main component of each IC chip, these IC chips can be directly adhered to the substrate. As a result, the high density mounting of the IC chips on the substrate can be facilitated.
  • the alumina ceramic substrate is most suitable to sufficiently support such I/O terminals arranged in a matrix fashion.
  • the manufacturing yield of such an LSI package is not very high, because high density and fine formation are required for the wiring formed inside the alumina ceramic substrate. In other words, it is not quite possible to form the wiring completely despite full and meticulous care and control in manufacture.
  • One object of the present invention is, therefore, to provide an improved LSI package free from the above-mentioned disadvantages in the prior art package.
  • an LSI package which comprises a ceramic substrate provided with a plurality of input/output terminals on the lower surface thereof.
  • the substrate at least one power supply layer having a plurality of conductive lines therethrough and a plurality of metallized.
  • the through-holes are formed from the lower surface to the upper surrace of the substrate so as to connect each of the input/output terminals.
  • the substrate has a plurality of signal wiring layers formed on the upper surface of the substrate, each layer having a plurality of conductive lines.
  • a plurality of pads are formed on the upper surface of the top signal wiring layer, for allowing the mounting and connection of circuit elements.
  • a plurality of spare pads are on the surface of the top signal wiring layer for connecting repair wires.
  • a plurality of space terminals are formed on the lower surface of the substrate; and spare wiring means is provided respectively through the substrate and the signal wiring layers to electrically connect each of these spare pads and spare terminals.
  • FIG. 1 is a partially enlarged perspective view of a preferred embodiment of the invention
  • FIG. 2 is another partial cross sectional view of the embodiment.
  • FIG. 3 is another partially enlarged perspective view of the embodiment.
  • one embodiment of the invention comprises a ceramic substrate 9 provided with two power supply layers 5, each of which has a plurality of conductive lines; plural signal wiring layers 6 formed on the upper surface of the ceramic substrate 9 and having a plurality of conductive lines, a plurality of pads 3 for connecting IC terminals (not shown) and a plurality of spare pads 7 formed on the upper surface of the top one 6a of the wiring layers 6; a plurality of IC chips 2 mounted on the upper surface of the layer 6a; a plurality of I/O terminals 1; a plurality of terminals 11 provided for supplying the power from a power source (not shown) to the layers 5; and a plurality of spare terminals 8 provided on the lower surface of the substrate 9.
  • the I/O terminals 1 are mounted onto the lower surface of the substrate 9 in matrix form along with the pin-shaped spare terminals 8. These terminals 1, are usually inserted into connectors (not shown) provided on a printed circuit board (not shown) to be interconnected with other LSI packages.
  • the terminals if the IC chips 2 housed within a known chip carrier are connected to the pads 3 on the upper surface of the top wiring layer 6a. Signal interconnection with the I/O terminals 1 and the IC chips 2 are achieved through the wiring layers 6 and a plurality of metallized through-holes 4.
  • each of the signal wiring layers 6 there are formed a plurality of conductive lines 61 and a plurality of metallized via-holes 62 used for layer-to-layer connection of the lines 61. Therefore, the interconnection between the terminals of the IC chips 2 is achieved by the lines 61 and the via-holes 62 formed in the wiring layers 6. Furthermore, the connection between the pad 3 and the I/O terminal 1 is achieved through the route of the pad 3--the via-hole 62b--the via-hole 62d--the through-hole 4a--the terminal 1, for instance.
  • the conductive lines 11 formed in a net-like fashion inside the power supply layers 5 become a power source circuit having a low impedance by interconnecting the through-holes 4 connected to the same power source.
  • Through-holes 12 connected to the power source via the terminals 11 are connected to the pads 3 via the lines 61, and the via-holes 62 to supply power to the pads 3 to be connected to the power terminals of the IC chips 2.
  • the repair is performed as follows.
  • the pad 3 and the spare pad 7a are connected first via a repair wire 10 on the upper surface side of the top wiring layer 6a.
  • the pad 7a is connected to the spare terminal 8a on the lower surface of the substrate 9 via spare wiring means formed of the via-holes 62a and 62c, the line 61a, and a through-hole 4b.
  • the terminals 8a and 1a are then connected via the repair wire 10' on the lower side of the substrate 9, so that the connection via the route of 3-10-7a-62a-62c-51a-4b-8a-10'-1a is achieved to complete the repair.
  • FIG. 2 shows the spare terminals 8 shaped similarly like a pin as the other I/O terminals 1, but this shape is not necessarily to be limited to the pin. It may be shaped like a pad as well so long as it can be connected to the repair wire 10'.
  • the present invention is advantageous in that the spare pads, the spare terminals, an the spare wiring means provided redundantly on the substrate enable repair of disconnections in the wiring connecting the I/O terminals and the pad by merely adding the repair wires on the upper surface side and lower surface side of the substrate.
US06/630,266 1983-07-19 1984-07-12 LSI package having a multilayer ceramic substrate Expired - Lifetime US4894708A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP58-131422 1983-07-19
JP58131422A JPS6022396A (ja) 1983-07-19 1983-07-19 回路基板

Publications (1)

Publication Number Publication Date
US4894708A true US4894708A (en) 1990-01-16

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US06/630,266 Expired - Lifetime US4894708A (en) 1983-07-19 1984-07-12 LSI package having a multilayer ceramic substrate

Country Status (3)

Country Link
US (1) US4894708A (fr)
JP (1) JPS6022396A (fr)
FR (1) FR2549641B1 (fr)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5095359A (en) * 1988-09-30 1992-03-10 Hitachi, Ltd. Semiconductor package and computer using the package
US5264729A (en) * 1992-07-29 1993-11-23 Lsi Logic Corporation Semiconductor package having programmable interconnect
US5288949A (en) * 1992-02-03 1994-02-22 Ncr Corporation Connection system for integrated circuits which reduces cross-talk
US6038135A (en) * 1995-06-30 2000-03-14 Fujitsu Limited Wiring board and semiconductor device
WO2000057477A1 (fr) * 1999-03-23 2000-09-28 Pyrchenkov Vladislav Nikolaevi Module polycristallin et procede de fabrication d'un module semiconducteur
EP1052696A2 (fr) * 1993-03-01 2000-11-15 The Board Of Trustees Of The University Of Arkansas Medium d'interconnexion electrique
US6323045B1 (en) 1999-12-08 2001-11-27 International Business Machines Corporation Method and structure for top-to-bottom I/O nets repair in a thin film transfer and join process
US20050073034A1 (en) * 1999-12-13 2005-04-07 Seiko Epson Corporation Package for semiconductor chip
US20050149783A1 (en) * 2003-12-11 2005-07-07 International Business Machines Corporation Methods and apparatus for testing an IC

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6253000A (ja) * 1985-08-31 1987-03-07 日本電気株式会社 半導体の実装構造
JPS63245952A (ja) * 1987-04-01 1988-10-13 Hitachi Ltd マルチチップモジュ−ル構造体
US20240088793A1 (en) 2021-01-07 2024-03-14 Panasonic Intellectual Property Management Co., Ltd. Power conversion apparatus capable of controlling power conversion circuits to operate selectively
EP4277080A1 (fr) 2021-01-07 2023-11-15 Panasonic Intellectual Property Management Co., Ltd. Dispositif de conversion d'énergie électrique

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4221047A (en) * 1979-03-23 1980-09-09 International Business Machines Corporation Multilayered glass-ceramic substrate for mounting of semiconductor device
US4407007A (en) * 1981-05-28 1983-09-27 International Business Machines Corporation Process and structure for minimizing delamination in the fabrication of multi-layer ceramic substrate

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5276680A (en) * 1976-10-26 1977-06-28 Fujitsu Ltd Multiilayer printed board
FR2404990A1 (fr) * 1977-10-03 1979-04-27 Cii Honeywell Bull Substrat d'interconnexion de composants electroniques a circuits integres, muni d'un dispositif de reparation
JPS552913A (en) * 1978-06-23 1980-01-10 Hitachi Ltd Device to test composite equivalence of circuit breaker
US4245273A (en) * 1979-06-29 1981-01-13 International Business Machines Corporation Package for mounting and interconnecting a plurality of large scale integrated semiconductor devices
DE2935428A1 (de) * 1979-09-01 1981-03-26 Henkel KGaA, 40589 Düsseldorf Waessrige tensidkonzentrate und verfahren zur verbesserung des fliessverhaltens schwer beweglicher waessriger tensidkonzentrate

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4221047A (en) * 1979-03-23 1980-09-09 International Business Machines Corporation Multilayered glass-ceramic substrate for mounting of semiconductor device
US4407007A (en) * 1981-05-28 1983-09-27 International Business Machines Corporation Process and structure for minimizing delamination in the fabrication of multi-layer ceramic substrate

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Clark et al., "IBM Multichip Multilayer Ceramic Modules for LSI Chips-Design for Performance and Density", IEEE Transaction on Components, Hybrids, and Manufacturing Technology, vol. CHMT-3, No. 1, Mar. 1980, pp. 89-93.
Clark et al., IBM Multichip Multilayer Ceramic Modules for LSI Chips Design for Performance and Density , IEEE Transaction on Components, Hybrids, and Manufacturing Technology, vol. CHMT 3, No. 1, Mar. 1980, pp. 89 93. *

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5095359A (en) * 1988-09-30 1992-03-10 Hitachi, Ltd. Semiconductor package and computer using the package
US5288949A (en) * 1992-02-03 1994-02-22 Ncr Corporation Connection system for integrated circuits which reduces cross-talk
US5264729A (en) * 1992-07-29 1993-11-23 Lsi Logic Corporation Semiconductor package having programmable interconnect
EP1052696A2 (fr) * 1993-03-01 2000-11-15 The Board Of Trustees Of The University Of Arkansas Medium d'interconnexion electrique
EP1052696A3 (fr) * 1993-03-01 2001-05-02 The Board Of Trustees Of The University Of Arkansas Medium d'interconnexion electrique
US6038135A (en) * 1995-06-30 2000-03-14 Fujitsu Limited Wiring board and semiconductor device
WO2000057477A1 (fr) * 1999-03-23 2000-09-28 Pyrchenkov Vladislav Nikolaevi Module polycristallin et procede de fabrication d'un module semiconducteur
US6323045B1 (en) 1999-12-08 2001-11-27 International Business Machines Corporation Method and structure for top-to-bottom I/O nets repair in a thin film transfer and join process
US20050073034A1 (en) * 1999-12-13 2005-04-07 Seiko Epson Corporation Package for semiconductor chip
US20050149783A1 (en) * 2003-12-11 2005-07-07 International Business Machines Corporation Methods and apparatus for testing an IC

Also Published As

Publication number Publication date
FR2549641B1 (fr) 1986-06-20
FR2549641A1 (fr) 1985-01-25
JPH029472B2 (fr) 1990-03-02
JPS6022396A (ja) 1985-02-04

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