US20180315637A1 - Mounting of semiconductor-on-diamond wafers for device processing - Google Patents

Mounting of semiconductor-on-diamond wafers for device processing Download PDF

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US20180315637A1
US20180315637A1 US15/770,209 US201615770209A US2018315637A1 US 20180315637 A1 US20180315637 A1 US 20180315637A1 US 201615770209 A US201615770209 A US 201615770209A US 2018315637 A1 US2018315637 A1 US 2018315637A1
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diamond
wafer
semiconductor
carrier substrate
layer
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Daniel Francis
Frank Yantis Lowe
Michael Ian Pearson
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RFHIC Corp Korea
RFHIC Corp USA
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RFHIC Corp Korea
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Assigned to RFHIC CORPORATION reassignment RFHIC CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ELEMENT SIX TECHNOLOGIES LIMITED
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02376—Carbon, e.g. diamond-like carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02269—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by thermal evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0405—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising semiconducting carbon, e.g. diamond, diamond-like carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3732—Diamonds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1602—Diamond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer

Definitions

  • the present invention relates to a method of mounting a semiconductor-on-diamond wafer on a carrier substrate for subsequent semiconductor device fabrication on the semiconductor-on-diamond wafer.
  • the present invention also relates to a semiconductor-on-diamond-on-carrier substrate wafer fabricated using the methodology described herein and to a method of fabricating one or more semiconductor device structures on a semiconductor side of such a semiconductor-on-diamond-on-carrier substrate wafer.
  • GaN-on-diamond wafers such as GaN-on-diamond wafers are known in the art.
  • U.S. Pat. No. 7,595,507, 8,283,189, and 8,283,672 disclose GaN-on-diamond wafers and methods of manufacture.
  • the GaN-on-diamond wafers need to meet certain mechanical specifications.
  • free standing GaN-on-diamond wafers do not meet many of these specifications.
  • the carrier mounting process is non-trivial because the mounted GaN-on-diamond wafer must meet all mechanical specifications and simultaneously remain unchanged when exposed to acids, bases, solvents and heat treatments, yet be simply dismountable at the end of the device fabrication process.
  • WO2014006562 describes a method of mount a semiconductor-on-diamond wafer on a carrier substrate for subsequent semiconductor device fabrication on the mounted semiconductor-on-diamond wafer.
  • the semiconductor-on-diamond wafer is bonded to a flat carrier plate, which is described as being advantageously a diamond carrier plate, to eliminate bow in the semiconductor-on-diamond wafer.
  • Semiconductor device structures can then be fabricated on the mounted wafer.
  • the carrier plate can then be removed and re-used.
  • One problem with this approach is that the diamond carrier substrate is expensive and the bonding process can be time consuming.
  • US20020115263 discloses a method of bonding a substrate to a carrier using a non-silicate glass bonding layer.
  • the bonding comprises heating the substrate, bonding layer, and carrier to bond the carrier to the substrate.
  • the bonding layer is substantially unsusceptible to outgassing in ultrahigh vacuum environments and is impervious to substantial chemical and structural degradation during thermal processing at temperatures at least up to about 500° C.
  • CTE coefficient of thermal expansion
  • the present specification provides a method of mounting a semiconductor-on-diamond wafer on a carrier substrate for subsequent semiconductor device fabrication on the semiconductor-on-diamond wafer, the method comprising:
  • the carrier substrate comprises at least one layer having a lower coefficient of thermal expansion (CTE) than diamond
  • an adhesive is used for bonding the carrier substrate to the semiconductor-on-diamond wafer and bonding is achieved by curing the adhesive while the semiconductor-on-diamond wafer is pressed against the optical flat
  • a wafer bow of no more than 100 ⁇ m, and more preferably no more than 80 ⁇ m, 60 ⁇ m, 40 ⁇ m or 20 ⁇ m;
  • the method provides a semiconductor-on-diamond-on-carrier substrate wafer comprising:
  • the carrier substrate comprises at least one layer having a lower coefficient of thermal expansion (CTE) than diamond
  • carrier substrate is bonded to the diamond side of the semiconductor-on-diamond wafer with an adhesive
  • a wafer bow of no more than 100 ⁇ m, and more preferably no more than 80 ⁇ m, 60 ⁇ m, 40 ⁇ m or 20 ⁇ m;
  • the carrier substrate may comprise a layer having a higher coefficient of thermal expansion (CTE) than diamond (e.g. silicon) in addition to the layer having a lower coefficient of thermal expansion (CTE) than diamond (e.g. quartz).
  • CTE coefficient of thermal expansion
  • the thermal expansion coefficient of the layers and layer thicknesses of the carrier substrate can be tuned such that internal residual stresses ensure near zero bow of the semiconductor-on-diamond-on-carrier substrate wafer. Such a mounted semiconductor-on-diamond is therefore suitable for device manufacture on a standard fabrication line. After device fabrication, the carrier substrate may be released and reused.
  • a method of fabricating semiconductor device structures comprising:
  • FIG. 1 shows a free-standing GaN-on-Diamond wafer exhibiting wafer bow
  • FIG. 2 shows a GaN-on-Diamond wafer bonded to a carrier wafer but still exhibiting wafer bow
  • FIGS. 3( a ) to 3 ( c ) show the steps involved in mounting a GaN-on-Diamond wafer bonded to a carrier wafer in order to eliminate wafer bow including starting with a free-standing GaN-on-Diamond wafer exhibiting wafer bow ( FIG. 3( a ) ), front-justification of the GaN-on-Diamond wafer against an optical flat ( FIG. 3( b ) ), and bonding of a carrier wafer to the GaN-on-diamond wafer using a UV adhesive and a carrier wafer having a CTE lower than diamond ( FIG. 3( c ) ) according to embodiments of the present invention;
  • FIG. 3( d ) shows an optional step of disposing a thermal tape on the optical flat according to embodiments of the present invention
  • FIG. 4 illustrates a suitable mounting configuration for bonding a carrier wafer to a GaN-on-diamond wafer according to embodiments of the present invention
  • FIG. 5 illustrates another suitable mounting configuration for bonding a carrier substrate to a GaN-on-diamond wafer using a multi-layer carrier substrate according to embodiments of the present invention.
  • FIG. 6 illustrates a flowchart illustrating exemplary steps for mounting a GaN-on-diamond wafer to a carrier wafer according to embodiments of the present invention.
  • GaN-on-diamond wafer and semiconductor-on-diamond wafer are used interchangeably.
  • semiconductor-on-diamond wafer includes a diamond layer and a semiconductor layer, and GaN is one type of semiconductor material.
  • Such a semiconductor-on-diamond wafer mounting solution is required for commercial semiconductor device manufacture on such wafers, particular when the semiconductor-on-diamond wafers are relatively thin (e.g. less than 200 ⁇ m thickness).
  • this methodology is commercially enabling and can be used by semiconductor device manufacturers to successfully process their devices onto a semiconductor-on-diamond substrate wafer without significant modification to their fabrication lines.
  • the basic methodology for mounting a semiconductor-on-diamond wafer e.g. GaN-on-Diamond
  • a semiconductor-on-diamond wafer e.g. GaN-on-Diamond
  • the basic methodology for mounting a semiconductor-on-diamond wafer comprises:
  • the carrier substrate comprises at least one layer having a lower coefficient of thermal expansion (CTE) than diamond
  • an adhesive is used for bonding the carrier substrate to the semiconductor-on-diamond wafer and bonding is achieved by curing the adhesive while the semiconductor-on-diamond wafer is pressed against the optical flat
  • a wafer bow of no more than 100 ⁇ m, and more preferably no more than 80 ⁇ m, 60 ⁇ m, 40 ⁇ m or 20 ⁇ m;
  • one approach uses the combination of a number of interrelated features including front justification, the use of a carrier substrate with a CTE close to, but lower than, diamond, and the use of a low temperature adhesive.
  • a temperature during bonding can be maintained between 10° C. and 40° C. using a low temperature adhesive such as a UV glue which bonds at room temperature when exposed to UV light and the bonding process comprises exposure to UV light to bond the carrier substrate to the diamond side of the semiconductor-on-diamond wafer.
  • the carrier substrate may be formed of a layer of quartz. By bonding the quartz to the diamond without significant heating, the thermally induced bowing due to CTE mismatch between the quartz and diamond can be reduced.
  • the mounted wafer should also be capable of withstanding the processing steps utilized in fabricating semiconductor devices on such a wafer and advantageously the carrier wafer should be subsequently readily removable and recyclable.
  • a thermal release adhesive can be provided between the carrier substrate and the diamond side of the semiconductor-on-diamond wafer to allow release of the carrier substrate after use.
  • the adhesive should be capable of maintaining adhesion of the carrier substrate and semiconductor-on-diamond wafer during exposure to device fabrication temperatures which may be equal to or greater than 200° C., 220° C., 250° C., 280° C., 300° C., or 350° C. depending on the specific device fabrication process. After device fabrication the thermal release adhesive can be exposed to higher temperatures (e.g.
  • the method of device manufacture may comprise: fabricating one or more semiconductor device structures on a semiconductor side of a semiconductor-on-diamond-on-carrier substrate wafer as described herein while maintaining the semiconductor-on-diamond-on-carrier substrate wafer at a temperature less than 220° C. (or 220° C., 250° C., 280° C., 300° C., 350° C., or 400° C.
  • the carrier substrate from the semiconductor-on-diamond wafer after fabrication of the one or more semiconductor device structures by heating the semiconductor-on-diamond-on-carrier substrate wafer to a temperature in excess of 220° C. (or 250° C., 280° C., 300° C., 350° C., or 400° C. depending on the release temperature of the thermal release adhesive).
  • FIG. 1 shows a free-standing GaN-on-diamond wafer comprising a layer of GaN 2 attached to a diamond layer 4 .
  • Such a free-standing GaN-on-diamond wafer 1 is bowed in the manner illustrated with the exposed surface of the GaN in convex form.
  • a carrier substrate 6 is bonded to the diamond side of such a bowed GaN-on-diamond wafer 1 using a bonding material 8 such as an epoxy resin, glass, or a ceramic adhesive
  • the adhesive 8 tends to fill the concave form of the diamond side of the GaN-on-diamond wafer 1 such that the convex bowing of the exposed GaN surface of the wafer 1 remains.
  • FIGS. 3( a ) to 3( c ) show a typical bowed free-standing GaN-on-diamond wafer 1 as previously shown in FIG. 1 comprising a layer of GaN 2 attached to a diamond layer 4 .
  • the diamond layer 4 may be deposited on the GaN layer 2 by a suitable diamond deposition technique.
  • the GaN side of the GaN-on-diamond wafer 1 is pressed flat onto an optical flat 5 .
  • a carrier substrate 6 may then be bonded to the diamond side of the GaN-on-diamond wafer via an adhesive 8 while the GaN-on-diamond wafer 1 is pressed against the optical flat 5 .
  • the stack of layers including GaN layer 2 , diamond layer 4 , adhesive 8 and carrier substrate 6 are pressed against the top surface of the optical flat 5 while the adhesive 8 is cured to secure the diamond layer 4 to the carrier wafer 6 .
  • the GaN-on-diamond-on-carrier substrate wafer 7 can be removed from the optical flat 5 with the GaN surface retaining the flatness characteristics of the optical flat 5 . That is, the optical flat 5 determines the shape of the wafer post bonding to the carrier substrate 6 .
  • FIG. 3( d ) shows an optional step of using a thermal release tape (or, shortly, thermal tape) 9 according to embodiments of the present invention. While FIGS. 3( a ) to 3( c ) illustrate the bottom surface of the GaN layer 2 being pressed directly against the optical flat 5 , it has been found that the provision of a thermal release tape 9 can be applied to the top surface of the optical flat 5 such that the GaN-on-diamond wafer 1 is held in place during the carrier substrate bonding process to ensure that the bonded wafer retains the profile of the optical flat 5 . The bonded wafer can then be removed from the optical flat 5 after bonding is completed by applying heating to trigger release of the thermal release tape 9 .
  • the above described process as illustrated in FIGS. 3( a ) to 3( c ) may produce a mounted GaN-on-diamond wafer with the desired levels of flatness and thickness uniformity.
  • further features may be added to ensure that the mounted semiconductor-on-diamond wafer meets the strict mechanical and geometric requirements for semiconductor device fabrication lines.
  • a low temperature (e.g. room temperature) adhesive may be used in certain configurations. Suitable adhesives include UV glues which set under exposure to UV light.
  • any glue which sets at or near room temperature without outgassing could potentially be utilized.
  • UV glue is preferable because the diamond layer 4 and carrier wafer 6 can be mounted to the desired configuration first with the adhesive 8 in un-set form and then subsequently exposed to UV to set the adhesive in a relatively short time frame.
  • Typical low cost materials for carrier substrate 6 include glass, silicon, and quartz, the most expensive of which is quartz. Quartz has a lower CTE than diamond. Given that the UV glue dismount is done at a high temperature and that many process steps are performed at temperatures higher than room temperature, it is necessary that the diamond be stable and solid at elevated temperatures. Mounting on silicon or glass leaves the diamond in tension at high temperatures, causing it to break above 200° C. Mounting on quartz leaves the diamond under compression at elevated temperatures. Under compression, the diamond causes the quartz to bend and ultimately the UV glue to release without cracking. Since crack-free release is the objective, a substrate with CTE lower than diamond has been found to be necessary.
  • FIG. 4 illustrates a suitable mounting configuration in accordance with embodiments of the present invention.
  • a GaN-on-diamond wafer 40 is pressed and adhered to optical flat quartz 42 using thermal release tape 44 .
  • a protective coating 56 e.g. SiN
  • the protective coating 56 may be applied to the GaN side of the GaN-on-diamond wafer 40 before the GaN-on-diamond wafer 40 is disposed on the optical flat 42 for bonding.
  • the optical flat 42 may be separated (released) from the GaN-on-diamond wafer 40 after the mounting process.
  • a coating layer 46 can also be optionally provided on a diamond side of the GaN-on-diamond wafer 40 to aid adhesion and/or to planarize the diamond surface and/or to allow release of the UV glue (adhesive 48 ) from the GaN-on-diamond wafer 40 after device processing on the GaN layer of the GaN-on-diamond wafer 40 .
  • the coating 46 may be formed of thermoplastic material.
  • adhesive (such as UV glue) 48 may be provided over the GaN-on-diamond wafer 40 and a quartz carrier wafer 50 is positioned on the adhesive layer 48 .
  • a further quartz flat 52 is used to press the quartz carrier wafer 50 to the front-justified GaN-on-diamond wafer 40 .
  • a ring shaped silicon spacer wafer 54 is used to control the thickness of layered structure.
  • FIG. 6 illustrates a flowchart 600 illustrating exemplary steps for mounting a GaN-on-diamond wafer to a carrier wafer according to embodiments of the present invention. The process begins at step 602 .
  • an optional protective coating 56 may be disposed on the layer of GaN (or, equivalently, GaN side or semiconductor side) of the GaN-on-diamond wafer 40 .
  • the GaN-on-diamond wafer 40 includes a diamond layer and a semiconductor (or, equivalently, GaN) layer, where the semiconductor layer is on the bottom side in FIG. 4 .
  • a coating layer (or, shortly coating) 46 may be disposed on the diamond side of the GaN-on-diamond wafer 40 , where the coating 46 may include thermoplastic material. As discussed below, the optional coating 46 may aid adhesion and/or to planarize the diamond surface and/or to allow release of the UV glue (adhesive 48 ) from the GaN-on-diamond wafer 40 after device processing on the GaN layer of the GaN-on-diamond wafer 40 .
  • the GaN-on-diamond wafer 40 may be disposed on the optical flat (such as quartz flat) 42 , where the GaN layer faces the optical flat.
  • a thermal release tape such as 3195N NittoTM tape, 90° C. release
  • a thermoplastic layer may be used in place of the thermal release tape 44 , where the thermoplastic layer, such as brewer bond 305 , may be spin coated on the GaN-on-diamond wafer 40 and baked to remove solvent.
  • an adhesive layer 48 may be disposed on the GaN-on-diamond wafer 40 and a carrier substrate (such as quart substrate) 50 may be disposed on the adhesive layer 48 , to thereby form a stacked wafer structure (or, shortly stacked structure) 53 .
  • the adhesive layer 48 is located between the carrier substrate 50 and the GaN-on-diamond wafer 40 (more specifically the diamond layer of the GaN-on-diamond wafer 40 ).
  • the adhesive layer 48 may be formed of UV glue, where the UV glue may be spun onto the carrier substrate 50 (e.g. NorlandTM 61 UV glue; 1500 RPM; 30 seconds).
  • the carrier substrate 50 and the the GaN-on-diamond wafer are aligned, edges of thermal tape 44 are cleaned, and a ring shaped silicon spacer wafer (or, shortly spacer) 54 may be provided around the stacked wafer structure 53 .
  • the stacked layer structure 53 including the carrier substrate 50 and GaN-on-diamond wafer 40 may be pressed against the optical flat 42 together using another flat (such as quartz flat) 52 in order to flatten the quartz carrier substrate 50 and reach the correct thickness for the stacked structure 53 .
  • the GaN-on-diamond wafer 40 may be front justified to the optical flat 42 so that the bottom surface of the GaN layer of the GaN-on-diamond wafer 40 is flattened by the top surface of the optical flat 42 .
  • the GaN-on-diamond wafer 40 may be bonded to the carrier substrate 50 .
  • the stacked wafer structure 53 may be removed from the press and the adhesive layer 48 is cured so that the carrier substrate 50 is bonded to the GaN-on-diamond wafer 40 .
  • the adhesive 48 is formed of UV glue that may be cured by exposing the glue to UV light for 9 minutes.
  • the stacked wafer structure 53 may remain in the press so that the adhesive layer 48 is cured while the stacked wafer structure 53 is being pressed against the optical flat 42 .
  • the flat 52 may be made of material that is transparent to UV light so that the UV light incident on the top surface of the flat 52 passes through both the flat 52 and the carrier substrate 50 and cures the UV glue to thereby bond the carrier substrate 50 to the GaN-on-diamond wafer 40 .
  • the temperature for curing the UV glue may be between 10° C. and 40° C.
  • the stacked wafer structure 53 is baked at a temperature (such as 120° C.) to heat release the tape 44 so that the GaN-on-diamond-on-carrier wafer 55 is separated from the optical flat 42 .
  • the GaN-on-diamond-on-carrier wafer 55 refers to the stack of GaN-on-diamond wafer 40 , adhesive layer 48 , and carrier substrate 50 , and optically, one or more of the protective coating 56 and the coating 46 .
  • the thermal release tape 44 may be released at a temperature which does not cause softening of the adhesive layer 48 .
  • the tape is peeled off to yield the final GaN-on-diamond-on-carrier substrate wafer 55 (or, equivalently mounted wafer).
  • a mounted wafer of controlled thickness and having a bow and warp of less than 20 ⁇ m is achieved in a processing time of approximately 1 hour.
  • Such a mounted wafer is suitable for semiconductor device processing.
  • the carrier substrate 50 can be released by heating the mounted wafer structure 55 at 250° C. for about 10 minutes. Dismounting the carrier substrate 50 by heating the mounted wafer, more specifically heating the adhesive 48 , is a useful but not necessary condition of mounting.
  • the ability to make a glue that can support temperatures of 200° C. but that dismounts at 250° C. is very useful. 200° C. allows for many fabrication processes, yet 250° C. is not a difficult temperature to achieve. This moderate temperature of dismount makes the process simple and easy to achieve.
  • thermoplastic layer may be disposed between the carrier substrate 50 and the diamond side of the GaN-on-diamond wafer 40 .
  • the thermal tape 44 may be replaced by a thermoplastic layer, where the thermoplastic layer, such as brewer bond 305 , is spin coated and baked up to 220° C. to remove solvents. It has been found that this approach provides a more repeatable approach compared with the use of a thermal release tape 44 . Coating the diamond with a thermo-plastic allows a slide release above 250° C.
  • CTE mismatched wafers are joined.
  • a carrier substrate that is closely matched to diamond of the GaN-on-diamond wafer (or, shortly diamond) in thermal expansion coefficient is selected and adhere it to the diamond side of the GaN-on-diamond wafer at room temperature by a UV sensitive adhesive.
  • the carrier substrate's CTE may be a close match to diamond but less than or equal to diamond in CTE. If the CTE of the carrier substrate is larger that of the diamond, during heating the diamond is under tension and is easily broken. Conversely, if the CTE of the carrier substrate is lower than the CTE of diamond, then when heated, the diamond is under compression and is much more stable.
  • the mounting process is simple and the difference in CTE between the carrier substrate and the diamond does not lead to mechanical bowing of the diamond for the lithography steps.
  • the adhesion may be performed at (or within a few degrees of) the temperature where lithography will occur so that the GaN-on-diamond remains flat.
  • the UV glue which sets by UV exposure may be used to adhere the carrier substrate at the correct temperature.
  • alternatives such as epoxies that set at room temperature may also be acceptable.
  • UV glues are preferable because they can be re-worked for an extended amount of time then set when ready, as opposed to having a fixed amount of time before which the adhesive sets.
  • Thermal setting adhesives may not be acceptable because they set at a temperature higher than lithography temperatures and unless the semiconductor-on-diamond CTE is exactly matched to the carrier then the wafer bows when cooled to lithography temperature.
  • the combination of a quartz carrier substrate and a low temperature UV adhesive for mounting the GaN-on-Diamond wafer is used in order to manage thermal mismatch problems and minimize wafer bow.
  • another modification which can aid in achieving ultra-flat mounted GaN-on-Diamond wafers is to use a carrier substrate which comprises layers having differing coefficients of thermal expansion which are selected such that internal residual stresses ensure near zero bow.
  • the carrier substrate can comprise a layer having a higher coefficient of thermal expansion (CTE) than diamond (e.g. silicon) in addition to the layer having a lower coefficient of thermal expansion (CTE) than diamond (e.g. provided by the previously described quartz carrier wafer).
  • a carrier substrate which comprises more than one layer of different materials such that the differences in CTE of these layers results in a mounted GaN-on-Diamond wafer with the required mechanical specifications in terms of thickness uniformity, bow, and warp. Furthermore, such specifications can be achieved at room temperature even following a high temperature bonding process if the layers are suitably selected.
  • materials that have both higher (e.g. silicon) and lower (e.g. quartz) CTE than diamond and carefully choosing the thickness of each layer and their order within the wafer stack, on cooling to room temperature internal residual stresses ensure near zero bow.
  • the carrier substrate may thus include two or more layers, of which at least two layers must have a different CTE. At least one layer may have a CTE which is higher than that of diamond.
  • the materials, thicknesses, and layer structure may be selected such that:
  • certain embodiments include a carrier substrate comprising a layer having a higher coefficient of thermal expansion (CTE) than diamond (e.g. silicon) in addition to the layer having a lower coefficient of thermal expansion (CTE) than diamond (e.g. quartz).
  • a carrier substrate comprising a layer having a higher coefficient of thermal expansion (CTE) than diamond (e.g. silicon) in addition to the layer having a lower coefficient of thermal expansion (CTE) than diamond (e.g. quartz).
  • CTE coefficient of thermal expansion
  • diamond e.g. silicon
  • CTE coefficient of thermal expansion
  • a thermal release adhesive can be provided that is formed of a material which, after bonding, is releasable when exposed to temperatures in excess of 220° C. (or in excess of 250° C. or more depending on the temperature of device fabrication process) to enable the carrier substrate to be removed and re-used after semiconductor device fabrication on the semiconductor-on-diamond wafer.
  • FIG. 5 shows a configuration for bonding a multi-layer carrier substrate to a GaN-on-Diamond wafer according to embodiments of the present invention.
  • the layer structure of the GaN-on-diamond-on carrier substrate wafer in FIG. 5 is similar to that in FIG. 4 , with the difference that the carrier substrate 70 may include at least two layers: one layer 64 having a higher coefficient of thermal expansion (CTE) than diamond (e.g., silicon) and another layer 66 having a lower CTE than diamond (e.g., quartz).
  • the GaN-on-diamond-on carrier substrate wafer in FIG. 5 may also include: an adhesive layer 68 that is disposed between the two layers 64 and 66 , and a thermal release adhesive 62 .
  • the adhesive layer 67 which bonds the carrier substrate 70 to the GaN-on-diamond wafer 60 , may be similar to the adhesive layer 48 in FIG. 4 .
  • a ring-shaped spacer wafer (not shown in FIG. 5 ), which is similar to the ring-shaped spacer wafer 54 may be disposed around the GaN-on-diamond wafer 60 and the carrier substrate 70 before the flat (such as optical flat) 69 presses the GaN-on-diamond wafer 60 and the carrier substrate 70 against the optical flat 61 .
  • the steps for the mounting of the carrier substrate 70 to the GaN-on-diamond wafer 60 are similar to the steps in flowchart 600 in FIG. 6 .
  • a GaN-on-Diamond wafer 60 (approximately 120 ⁇ m thickness) is pressed against an optical flat 61 .
  • the thermal release adhesive 62 is optionally provided on the diamond side of the GaN-on-Diamond wafer 60 .
  • the carrier substrate 70 may include a wafer of silicon 64 (approximately 295 ⁇ m thickness) and a wafer of quartz 66 (approximately 152 ⁇ m thickness) bonded to the wafer of silicon 64 by a high temperature polymer adhesive 68 .
  • the carrier substrate 70 may be attached to the GaN-on-Diamond wafer 60 using a high temperature polymer adhesive 67 (bonding temperature 350° C.), where the adhesive 67 may be formed of the same material as the adhesive 68 .
  • the high temperature polymer adhesive layers 67 and 68 are spun on, the bonding process occurs at 350° C., and a further optical flat 69 is used to apply a pressure of approximately 1000 N during bonding.
  • the bonding also advantageously takes place under vacuum to aid air pocket removal in the adhesive layers 67 and 68 .
  • a stress model has been developed to help design the carrier substrate.
  • the design outlined in FIG. 5 is deemed advantageous due to:
  • the stress in the diamond for the proposed structure is such that the diamond layer is in compression (-ve stress) through the entire thickness of the layer.
  • the silicon layer 64 is entirely in tension at a level below its tensile strength (>200 MPa).
  • the methodology as described herein is capable of fabricating a semiconductor-on-diamond-on-carrier substrate wafer comprising:
  • the carrier substrate ( 50 , 70 ) may be formed of a single layer of material having a lower coefficient of thermal expansion (CTE) than diamond (e.g. quartz) or alternatively may comprise more than one layer including a layer having a higher coefficient of thermal expansion (CTE) than diamond (e.g. silicon) in addition to the layer having a lower coefficient of thermal expansion (CTE) than diamond.
  • the semiconductor-on-diamond-on-carrier substrate wafer structure may also include a thermal release adhesive 62 between the carrier substrate 70 and the diamond side of the semiconductor-on-diamond wafer 60 to allow release of the carrier substrate 70 after use.
  • the presently described methodology is capable of achieving the requirements for total thickness variation, wafer bow, and wafer warp over a diameter of at least 50 mm, 75 mm, 100 mm, or 150 mm.
  • a flat geometry is achieved even for large area wafers.
  • Typical dimensions for the semiconductor-on-diamond-on-carrier substrate wafer are as follows: a wafer thickness in a range 200 ⁇ m to 1 mm; a diameter in a range 40 mm to 200 mm; a semiconductor-on-diamond wafer thickness in a range 50 ⁇ m to 300 ⁇ m.

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