US20180076262A1 - Semiconductor device having rare earth oxide layer and method of manufacturing the same - Google Patents

Semiconductor device having rare earth oxide layer and method of manufacturing the same Download PDF

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US20180076262A1
US20180076262A1 US15/445,829 US201715445829A US2018076262A1 US 20180076262 A1 US20180076262 A1 US 20180076262A1 US 201715445829 A US201715445829 A US 201715445829A US 2018076262 A1 US2018076262 A1 US 2018076262A1
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layer
crystalline
reo
rare earth
earth oxide
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Youngmin EEH
Toshihiko Nagase
Daisuke Watanabe
Kazuya Sawada
Kenichi Yoshino
Tadaaki Oikawa
Hiroyuki OHTORI
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Kioxia Corp
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Toshiba Memory Corp
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Priority to US15/445,829 priority Critical patent/US20180076262A1/en
Assigned to KABUSHIKI KAISHA TOSHIBA reassignment KABUSHIKI KAISHA TOSHIBA ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: EEH, Youngmin, NAGASE, TOSHIHIKO, OHTORI, HIROYUKI, OIKAWA, TADAAKI, SAWADA, KAZUYA, WATANABE, DAISUKE, YOSHINO, KENICHI
Assigned to TOSHIBA MEMORY CORPORATION reassignment TOSHIBA MEMORY CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KABUSHIKI KAISHA TOSHIBA
Publication of US20180076262A1 publication Critical patent/US20180076262A1/en
Priority to US16/125,759 priority patent/US11201189B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
    • H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/10—Magnetoresistive devices
    • H01L27/228—
    • H01L43/02—
    • H01L43/08—
    • H01L43/10—
    • H01L43/12—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/80—Constructional details
    • H10N50/85—Magnetic active materials

Definitions

  • Embodiments described herein relate generally to a semiconductor device having a rare earth oxide layer and a method of manufacturing the same.
  • the crystalline layer can be obtained by, for example, crystallizing an amorphous layer by heat treatment. In this case, it is important to obtain a good crystalline layer having a preferable orientation.
  • FIG. 1A and FIG. 1B show a first embodiment.
  • FIG. 2 shows a principle on which a crystalline magnetic layer is obtained.
  • FIG. 3 and FIG. 4 show comparative examples.
  • FIG. 5 to FIG. 9 show modifications of the first embodiment.
  • FIG. 10A and FIG. 10B show a second embodiment.
  • FIG. 11 to FIG. 15 show modifications of the second embodiment.
  • FIG. 16 shows a third embodiment.
  • FIG. 17 shows a fourth embodiment.
  • FIG. 18 shows a fifth embodiment.
  • FIG. 19 shows memory cells of an MRAM.
  • FIG. 20 is a sectional view along line XX-XX of FIG. 19 .
  • FIG. 21 is a sectional view along line XXI-XXI of FIG. 19 .
  • FIG. 22 and FIG. 23 show a method of manufacturing the MRAM of FIG. 19 to FIG. 21 .
  • FIG. 24 shows an example of a memory system.
  • a semiconductor device comprises: a first rare earth oxide layer; a first magnetic layer being adjacent to the first rare earth oxide layer; and a nonmagnetic layer, the first magnetic layer being disposed between the first rare earth oxide layer and the nonmagnetic layer and being oriented in a crystal surface which is the same as a crystal surface of the nonmagnetic layer.
  • FIG. 1A and FIG. 1B show a semiconductor device according to a first embodiment.
  • the semiconductor device comprises a rare earth oxide layer (REO layer) 11 and a crystalline magnetic layer 12 above the REO layer 11 .
  • the semiconductor device comprises the crystalline magnetic layer 12 and the REO layer 11 above the crystalline magnetic layer 12 .
  • the crystalline magnetic layer 12 is adjacent to the REO layer 11 . It is preferable that the crystalline magnetic layer 12 contact the REO layer 11 .
  • an interfacial layer may exist between the REO layer 11 and the crystalline magnetic layer 12 . It should be noted that, as will be described later, the interfacial layer may exist under the condition that it does not influence the crystallization of the crystalline magnetic layer 12 .
  • the REO layer 11 includes at least one of Tb, Gd, Nd, Y, Sm, Pm, Tm, Sc, Ce, Eu, Er, Ho, La, Yb, Lu, Pr, and Dy.
  • the crystalline magnetic layer 12 includes at least one of Co, Fe, and Ni.
  • the crystalline magnetic layer 12 is CoFeB
  • the crystalline magnetic layer 12 has a body-centered cubic (BCC) structure in which a film surface is oriented in a (001) surface.
  • the film surface herein means a surface substantially parallel to the interface between the REO layer 11 and the crystalline magnetic layer 12 .
  • the REO layer 11 and the crystalline magnetic layer 12 include the same impurities.
  • the same impurities are, for example, at least one of B, P, C, Al, Mn, Si, Ta, W, Mo, Cr, Hf, and Ti.
  • the crystallization of the crystalline magnetic layer 12 can be promoted.
  • FIG. 2 shows a principle on which a crystalline magnetic layer is obtained.
  • the crystalline magnetic layer 11 can be obtained by, for example, crystallizing an amorphous layer by heat treatment such as annealing. In this case, to promote the crystallization of the crystalline magnetic layer 11 , it is necessary to remove impurities included in the amorphous layer in the heat treatment.
  • the REO layer 11 performs an important role in removing the impurities included in the amorphous layer. That is, the REO layer 11 has a crystal structure in which the space between elements is relatively wide. Accordingly, as shown in the figure, if heat treatment is performed in the semiconductor device having a stacked structure of the REO layer (crystal structure) 11 and an amorphous magnetic layer 12 ′ including impurities, the impurities in the amorphous magnetic layer 12 ′ easily diffuse into the REO layer 11 , or other layers via the REO layer 11 .
  • the impurities in the amorphous magnetic layer 12 ′ can be reduced, and the good crystalline magnetic layer 12 can be obtained.
  • the impurities can be substantially completely removed.
  • the absolute value of the standard free energy of formation of oxide of the REO layer 11 is large, and the REO layer 11 is extremely stable oxide. That is, in heat treatment such as annealing, even if the temperature of the REO layer 11 rises, rare-earth elements and oxygen elements are hardly dissociated. Accordingly, in heat treatment, the rare-earth elements or the oxygen elements in the REO layer 11 do not diffuse into the crystalline magnetic layer 12 or inhibit the crystallization of the crystalline magnetic layer 12 .
  • the film surface of the REO layer 11 (the interface between the REO layer 11 and the crystalline magnetic layer 12 ) has extremely high flatness. This is because the rare-earth elements are large, and thus, when the rare-earth elements and the oxide elements are combined to form the REO 11 , the degree of motion of the rare-earth elements is small. That is, when the rare-earth elements and the oxygen elements are combined, the rare-earth elements hardly cohere, and the film surface of the REO layer 11 can be flattened.
  • the flatness of the film surface of the REO layer 11 is also one of the effective factors in improving various properties, such as perpendicular magnetic anisotropy, of the crystalline magnetic layer 12 .
  • a stacked structure of the REO layer 11 and the amorphous magnetic layer 12 ′ including impurities is formed.
  • the REO layer 11 has a crystal structure
  • the amorphous magnetic layer 12 ′ has an amorphous structure due to the impurities.
  • the impurities in the amorphous magnetic layer 12 ′ are removed, and the amorphous magnetic layer 12 ′ is changed into the crystalline magnetic layer 12 .
  • the impurities in the amorphous magnetic layer 12 ′ diffuse into the REO layer 11 or into other layers via the REO layer 11 .
  • the elements in the REO layer 11 do not diffuse into the crystalline magnetic layer 12 .
  • the crystallization of the crystalline magnetic layer 12 can be promoted.
  • the REO layer 11 does not include impurities in the amorphous magnetic layer 12 ′. However, after the heat treatment, the REO layer 11 includes impurities diffused from the amorphous magnetic layer 12 ′. In addition, although the impurities in the amorphous magnetic layer 12 ′ are reduced by the heat treatment, some of the impurities may be left in the crystalline magnetic layer 12 after the heat treatment. In this case, the REO layer 11 and the crystalline magnetic layer 12 include the same impurities.
  • the crystalline magnetic layer 12 may has a concentration gradient of impurities in the thickness direction (stacked direction). This phenomenon depends on the concentration of impurities in the amorphous magnetic layer 12 ′ before the heat treatment. In this case, a part (an area where the concentration of impurities is high after the heat treatment) of the crystalline magnetic layer 12 may not be crystallized and maintain an amorphous state.
  • FIG. 3 and FIG. 4 show comparative examples.
  • the example of FIG. 3 differs from that of FIG. 2 in that a metal layer 11 ′ is used instead of the REO layer 11 of FIG. 2 .
  • the metal layer 11 ′ includes, for example, Nb, Mo, Ta, Cr, V, Zn, Ru, Hf, or Zr.
  • metal elements in the metal layer 11 ′ diffuse into the crystalline magnetic layer 12 in heat treatment, and thus, the crystallization of the crystalline magnetic layer 12 is thereby inhibited.
  • the example of FIG. 4 differs from that of FIG. 2 in that a metal nitride layer 11 ′′ is used instead of the REO layer 11 of FIG. 2 .
  • the metal nitride layer 11 ′′ includes, for example, MgN, ZrN, NbN, SiN, AlN, HfN, TaN, WN, CrN, MoN, TiN, or VN.
  • the metal nitride layer 11 ′′ may include, for example, an oxygen compound such as MgO.
  • the metal nitride layer 11 ′′ may be a ternary compound such as AlTiN.
  • the metal nitride layer 11 ′′ blocks the diffusion of impurities from the amorphous magnetic layer 12 ′, and thus, it is hard to remove the impurities from the amorphous magnetic layer 12 ′.
  • a large number of impurities are left in the crystalline magnetic layer 12 , and the crystallization of the crystalline magnetic layer 12 cannot be promoted.
  • the crystallization of the crystalline magnetic layer 12 can be promoted by the stacked structure of the REO layer 11 and the crystalline magnetic layer 12 .
  • the present embodiment is applicable to all semiconductor devices which require a crystalline magnetic layer having a good crystal structure.
  • FIG. 5 to FIG. 9 show modifications of the first embodiment.
  • the semiconductor device comprises an REO layer 11 a , the crystalline magnetic layer 12 above the REO layer 11 a , and an REO layer 11 b above the crystalline magnetic layer 12 . That is, the crystalline magnetic layer 12 is interposed between the two REO layers 11 a and 11 b .
  • the REO layers 11 a and 11 b correspond to the REO layer 11 of FIG. 1A and FIG. 1B .
  • an interfacial layer may exist in at least one of the space between the REO layer 11 a and the crystalline magnetic layer 12 and the space between the REO layer 11 b and the crystalline magnetic layer 12 . It should be noted that the interfacial layer may exist under the condition that it does not influence the crystallization of the crystalline magnetic layer 12 .
  • the impurities in the amorphous magnetic layer can diffuse upward and downward, that is, into both of the REO layers 11 a and 11 b , and thus, the crystallization of the crystalline magnetic layer 12 can be further promoted.
  • the semiconductor device comprises a crystalline magnetic layer 12 a , the REO layer 11 above the crystalline magnetic layer 12 a , and a crystalline magnetic layer 12 b above the REO layer 11 . That is, the REO layer 11 is interposed between the two crystalline magnetic layers 12 a and 12 b .
  • the crystalline magnetic layers 12 a and 12 b correspond to the crystalline magnetic layer 12 of FIG. 1A and FIG. 1B .
  • the crystalline magnetic layers 12 a and 12 b contact the REO layer 11 .
  • an interfacial layer may exist in at least one of the space between the REO layer 11 and the crystalline magnetic layer 12 a and the space between the REO layer 11 and the crystalline magnetic layer 12 b . It should be noted that the interfacial layer may exist under the condition that it does not influence the crystallization of the crystalline magnetic layers 12 a and 12 b.
  • the crystalline magnetic layers 12 a and 12 b each having a good crystal structure can be formed at the same time.
  • the semiconductor device comprises the REO layer 11 , the crystalline magnetic layer 12 above the REO layer 11 , and a nonmagnetic layer (seed layer) 13 above the crystalline magnetic layer 12 .
  • the semiconductor device comprises the nonmagnetic layer (seed layer) 13 , the crystalline magnetic layer 12 above the nonmagnetic layer 13 , and the REO layer 11 above the crystalline magnetic layer 12 .
  • the crystalline magnetic layer 12 is interposed between the REO layer 11 and the nonmagnetic layer 13 .
  • the crystalline magnetic layer 12 contact the REO layer 11 and the nonmagnetic layer 13 .
  • an interfacial layer may exist in at least one of the space between the REO layer 11 and the crystalline magnetic layer 12 and the space between the crystalline magnetic layer 12 and the nonmagnetic layer 13 . It should be noted that the interfacial layer may exist under the condition that it does not influence the crystallization of the crystalline magnetic layer 12 .
  • the nonmagnetic layer 13 has a predetermined crystal structure before heat treatment, and performs the function of controlling the orientation of the crystal structure of the crystalline magnetic layer 12 during the heat treatment. That is, in the crystallization process of the magnetic layer, the crystalline magnetic layer 12 grows with the nonmagnetic layer 13 serving as a seed. For example, the crystalline magnetic layer 12 is oriented in the same crystal surface as that of the nonmagnetic layer 13 . In this sense, the nonmagnetic layer 13 is referred to as a seed layer.
  • the nonmagnetic layer 13 may be an insulator or a conductor.
  • the nonmagnetic layer 13 includes, for example, at least one of magnesium oxide, aluminum oxide, zinc oxide, titanium oxide, aluminum nitride, boron nitride, and lanthanum-strontium-manganese oxide (LSMO).
  • LSMO lanthanum-strontium-manganese oxide
  • the nonmagnetic layer 13 is magnesium oxide (MgO)
  • the nonmagnetic layer 13 has an NaCl structure in which the film surface is oriented in a (001) surface.
  • the crystalline magnetic layer 12 is CoFeB
  • the crystalline magnetic layer 12 has a body-centered cubic (BCC) structure in which the film surface is oriented in the (001) surface.
  • the nonmagnetic layer 13 is magnesium oxide (MgO) and the crystalline magnetic layer 12 is FePtB
  • the crystalline magnetic layer 12 has a face centered cubic (FCC) structure in which the film surface is oriented in the (001) surface.
  • FCC face centered cubic
  • boron is substantially completely removed from the crystalline magnetic layer 12 and the crystalline magnetic layer 12 has an L1 O structure (L1 O -FePt).
  • the nonmagnetic layer 13 is zinc oxide (ZnO)
  • the nonmagnetic layer 13 has a hexagonal Wurtzite structure in which the film surface is oriented in a (0001) surface.
  • the crystalline magnetic layer 12 is CoPdB
  • the crystalline magnetic layer 12 has a face centered cubic (FCC) structure in which the film surface is oriented in a (111) surface.
  • FCC face centered cubic
  • boron is substantially completely removed from the crystalline magnetic layer 12 and the crystalline magnetic layer 12 has an L1 1 structure (L1 1 -CoPd).
  • the nonmagnetic layer 13 includes, for example, at least one of Pt, Pd, Rh, Ru, Ir, and Cr.
  • the nonmagnetic layer 13 is one of Pt, Pd, and Ir
  • the nonmagnetic layer 13 has a crystal structure in which the film surface is oriented in a (111) surface.
  • the crystalline magnetic layer 12 also has a crystal structure in which the film surface is oriented in the (111) surface.
  • the nonmagnetic layer 13 is one of Rh and Cr
  • the nonmagnetic layer 13 has a crystal structure in which the film surface is oriented in a (001) surface.
  • the crystalline magnetic layer 12 also has a crystal structure in which the film surface is oriented in the (001) surface.
  • the nonmagnetic layer 13 is Ru
  • the nonmagnetic layer 13 has a crystal structure in which the film surface is oriented in a (0001) surface.
  • the crystalline magnetic layer 12 also has a crystal structure in which the film surface is oriented in the (0001) surface.
  • a material included in the nonmagnetic layer (seed layer) 13 is different from a material included in the REO layer 11 .
  • a rare-earth oxide generally has a large atomic radius and a complex crystal structure. Therefore, in the case where the nonmagnetic layer 13 having a film thickness of several nm includes, for example, the rare-earth oxide, the nonmagnetic layer 13 has a bad crystalline and does not function as a seed layer (a crystalline orientation layer) of the crystalline magnetic layer 12 .
  • the nonmagnetic layer 13 including the rare-earth oxide is not desirable as a tunnel barrier layer for obtaining a large MR ratio.
  • the nonmagnetic layer 13 and the REO layer 11 may include the same element.
  • the crystalline magnetic layer 12 grows with the nonmagnetic layer 13 serving as a seed. Accordingly, the crystallization of the crystalline magnetic layer 12 can be further promoted.
  • the modifications of the FIG. 7 and FIG. 8 are effective in controlling the orientation of the crystalline magnetic layer 12 to an orientation other than that in which the surface energy is the smallest. This is because in the case where the orientation of the crystalline magnetic layer 12 is controlled to the orientation in which the surface energy is the smallest, even if the nonmagnetic layer 13 does not exist, the crystalline magnetic layer 12 naturally has the orientation in which the surface energy is the smallest by heat treatment.
  • the orientation in which the surface energy is the smallest is determined by the material of the crystalline magnetic layer 12 , that is, an element included in the crystalline magnetic layer 12 , or if the crystalline magnetic layer 12 includes elements, the composition ratio thereof, etc.
  • the orientation of the crystalline magnetic layer 12 is controlled to the orientation in which the surface energy is the smallest, the structure of FIG. 1A , FIG. 1B , FIG. 5 , or FIG. 6 is preferable. If the orientation of the crystalline magnetic layer 12 is controlled to an orientation other than that in which the surface energy is the smallest, the structure of FIG. 7 or FIG. 8 is preferable.
  • the semiconductor device comprises the REO layer 11 a , the crystalline magnetic layer 12 a above the REO layer 11 a , the nonmagnetic layer (seed layer) 13 above the crystalline magnetic layer 12 a , the crystalline magnetic layer 12 b above the nonmagnetic layer 13 , and the REO layer 11 b above the crystalline magnetic layer 12 b.
  • the crystalline magnetic layer 12 a is interposed between the REO layer 11 a and the nonmagnetic layer 13
  • the crystalline magnetic layer 12 b is interposed between the nonmagnetic layer 13 and the REO layer 11 b.
  • the crystalline magnetic layer 12 a contact the REO layer 11 a and the nonmagnetic layer 13 . It is preferable that the crystalline magnetic layer 12 b contact the nonmagnetic layer 13 and the REO layer 11 b.
  • an interfacial layer may exist in at least one of the space between the REO layer 11 a and the crystalline magnetic layer 12 a and the space between the crystalline magnetic layer 12 a and the nonmagnetic layer 13 .
  • an interfacial layer may exist in at least one of the space between the REO layer 11 b and the crystalline magnetic layer 12 b and the space between the crystalline magnetic layer 12 b and the nonmagnetic layer 13 . It should be noted that the interfacial layers may exist under the condition that they do not influence the crystallization of the crystalline magnetic layers 12 a and 12 b.
  • FIG. 9 is applicable to a magnetoresistive element.
  • one of the two crystalline magnetic layers 12 a and 12 b is a storage layer (free layer) having a variable direction of magnetization
  • the other is a reference layer (pinned layer) having an invariable direction of magnetization
  • the nonmagnetic layer 13 is an insulating layer (tunnel barrier layer)
  • the invariable magnetization means that the direction of magnetization does not vary before or after writing
  • the variable magnetization means that the direction of magnetization can vary in reverse before or after writing.
  • the writing means spin-transfer-torque writing in which a spin-transfer-torque current (spin-polarized electron) is passed to the magnetoresistive element, thereby imparting a spin torque to the magnetization of a storage layer.
  • a spin-transfer-torque current spin-polarized electron
  • the crystalline magnetic layers 12 a and 12 b have an axis of easy magnetization in a direction perpendicular to the film surface, that is, have the so-called perpendicular magnetic anisotropy.
  • the crystalline magnetic layers 12 a and 12 b may have an axis of easy magnetization in a direction parallel to the film surface, that is, the so-called in-plane magnetic anisotropy.
  • the resistance of the magnetoresistive element varies depending on the relative directions of magnetization of a storage layer and a reference layer because of the magnetoresistive effect.
  • the resistance of the magnetoresistive element is low in a parallel state in which the directions magnetization of the storage layer and the reference layer are the same, and high in an antiparallel state in which the directions of magnetization of the storage layer and the reference layer are opposite to each other.
  • each of the two crystalline magnetic layers 12 a and 12 b includes at least one of Co, Fe, and Ni
  • the nonmagnetic layer 13 includes at least one of magnesium oxide, aluminum oxide, zinc oxide, titanium oxide, aluminum nitride, boron nitride, and LSMO.
  • the two crystalline magnetic layers 12 a and 12 b are oriented by heat treatment in the same crystal surface as that of the nonmagnetic layer 13 .
  • the indices for evaluating the properties of the magnetoresistive element include an improvement in the magnetoresistive (MR) ratio, a reduction in the switching current, and an improvement in the thermal stability. To achieve them at the same time, it is important to improve the crystalline texture or the magnetic anisotropy of the crystalline magnetic layers (storage layer or reference layer) 12 a and 12 b.
  • MR magnetoresistive
  • the state in which the continuity between the crystal structures is secured means that the interface between the crystalline magnetic layer 12 a and the nonmagnetic layer 13 and the interface between the nonmagnetic layer 13 and the crystalline magnetic layer 12 b are each flat and do not have a lattice defect.
  • amorphous magnetic layers between which the nonmagnetic layer (crystal structure) 13 is interposed are formed.
  • the amorphous magnetic layers are formed by mixing impurities into magnetic layers.
  • The, by heat treatment, the impurities in the amorphous magnetic layers are removed, and the crystalline magnetic layers 12 a and 12 b are formed.
  • the impurities in the amorphous layers move from the nonmagnetic layer 13 side to the REO layers 11 a and 11 b side and diffuse into the REO layers 11 a and 11 b .
  • the impurities are easily removed by using the REO layers 11 a and 11 b .
  • any elements do not diffuse from the REO layers 11 a and 11 b into the amorphous magnetic layers.
  • a material included in the nonmagnetic layer (seed layer) 13 is different from a material included in the REO layer 11 a , 11 b .
  • the nonmagnetic layer 13 and the REO layer 11 a , 11 b may include the same element.
  • the crystalline texture or the magnetic anisotropy of the magnetoresistive element can be improved by applying the structure of FIG. 9 to the magnetoresistive element. Accordingly, an improvement in the MR ratio, a reduction in the switching current, and an improvement in the thermal stability of the magnetoresistive element can be achieved.
  • FIG. 10A and FIG. 10B show a semiconductor device according to a second embodiment.
  • the semiconductor device comprises an REO layer 11 and a crystalline layer 12 ′ above the REO layer 11 .
  • the semiconductor device comprises the crystalline layer 12 ′ and the REO layer 11 above the crystalline layer 12 ′.
  • the crystalline layer 12 ′ is adjacent to the REO layer 11 . It is preferable that the crystalline layer 12 ′ contact the REO layer 11 .
  • an interfacial layer may exist between the REO layer 11 and the crystalline layer 12 ′. It should be noted that, as will be described later, the interfacial layer may exist under the condition that it does not influence the crystallization of the crystalline layer 12 ′.
  • the REO layer 11 includes at least one of Tb, Gd, Nd, Y, Sm, Pm, Tm, Sc, Ce, Eu, Er, Ho, La, Yb, Lu, Pr, and Dy.
  • the crystalline layer 12 ′ may be a conductor, an insulator, or a semiconductor.
  • the crystalline layer 12 ′ is a conductor
  • the crystalline layer 12 ′ includes a metal element such as W, Al, or Cu.
  • the crystalline layer 12 ′ may be a magnetic material.
  • the crystalline layer 12 ′ includes at least one of Co, Fe, and Ni.
  • the REO layer 11 and the crystalline layer 12 ′ include the same impurities.
  • the same impurities are, for example, at least one of B, P, C, Al, Mn, Si, Ta, W, Mo, Cr, Hf, and Ti.
  • the crystallization of the crystalline layer 12 ′ can be promoted.
  • a principle on which the crystallization of the crystalline layer 12 ′ is promoted is the same as that of the first embodiment (see FIG. 2 to FIG. 4 ), and a description thereof is herein omitted.
  • the crystallization of the crystalline layer 12 ′ can be promoted by the stacked structure of the REO layer 11 and the crystalline layer 12 ′.
  • the present embodiment is applicable to all semiconductor devices which require a crystalline magnetic layer having a good crystal structure.
  • FIG. 11 to FIG. 15 show modifications of the second embodiment.
  • the semiconductor device comprises an REO layer 11 a , the crystalline layer 12 ′ above the REO layer 11 a , and an REO layer 11 b above the crystalline layer 12 ′. That is, the crystalline layer 12 ′ is interposed between the two REO layers 11 a and 11 b .
  • the REO layers 11 a and 11 b correspond to the REO layer 11 of FIG. 10A and FIG. 10B .
  • an interfacial layer may exist in at least one of the space between the REO layer 11 a and the crystalline layer 12 ′ and the space between the REO layer 11 b and the crystalline layer 12 ′. It should be noted that the interfacial layer may exist under the condition that it does not influence the crystallization of the crystalline layer 12 ′.
  • the impurities in the amorphous magnetic layer can diffuse upward and downward, that is, into both of the REO layers 11 a and 11 b , and thus, the crystallization of the crystalline layer 12 ′ can be further promoted.
  • the semiconductor device comprises a crystalline layer 12 a ′, the REO layer 11 above the crystalline layer 12 a ′, and a crystalline layer 12 b ′ above the REO layer 11 . That is, the REO layer 11 is interposed between the two crystalline layers 12 a ′ and 12 b ′.
  • the crystalline layers 12 a ′ and 12 b ′ correspond to the crystalline layer 12 of FIG. 10A and FIG. 10B .
  • an interfacial layer may exist in at least one of the space between the REO layer 11 and the crystalline layer 12 a ′ and the space between the REO layer 11 and the crystalline layer 12 b ′. It should be noted that the interfacial layer may exist under the condition that it does not influence the crystallization of the crystalline layers 12 a ′ and 12 b′.
  • the crystalline layers 12 a ′ and 12 b ′ each having a good crystal structure can be formed at the same time.
  • the semiconductor device comprises the REO layer 11 , the crystalline layer 12 ′ above the REO layer 11 , and a seed layer (crystalline layer) 13 ′ above the crystalline layer 12 ′.
  • the semiconductor device comprises the seed layer 13 ′, the crystalline layer 12 ′ above the seed layer 13 ′, and the REO layer 11 above the crystalline layer 12 ′.
  • the crystalline layer 12 ′ is interposed between the REO layer 11 and the seed layer 13 ′.
  • an interfacial layer may exist in at least one of the space between the REO layer 11 and the crystalline layer 12 ′ and the space between the crystalline layer 12 ′ and the seed layer 13 ′. It should be noted that the interfacial layer may exist under the condition that it does not influence the crystallization of the crystalline layer 12 ′.
  • the seed layer 13 ′ has a predetermined crystal structure before heat treatment, and performs the function of controlling the orientation of the crystal structure of the crystalline magnetic layer 12 ′ during the heat treatment. That is, in the crystallization process of the crystalline layer 12 ′, the crystalline layer 12 ′ grows with the seed layer 13 ′ serving as a seed. For example, the crystalline layer 12 ′ is oriented in the same crystal surface as that of the seed layer 13 ′.
  • the seed layer 13 ′ may be an insulator or a conductor.
  • the seed layer 13 ′ includes, for example, at least one of magnesium oxide, aluminum oxide, zinc oxide, titanium oxide, aluminum nitride, boron nitride, and lanthanum-strontium-manganese oxide (LSMO).
  • LSMO lanthanum-strontium-manganese oxide
  • the seed layer 13 ′ includes, for example, at least one of Pt, Pd, Rh, Ru, Ir, and Cr.
  • the seed layer 13 ′ is one of Pt, Pd, and Ir
  • the seed layer 13 ′ has a crystal structure in which the film surface is oriented in a (111) surface.
  • the magnetic layer 12 ′ also has a crystal structure in which the film surface is oriented in the (111) surface.
  • the seed layer 13 ′ is one of Rh and Cr
  • the seed layer 13 ′ has a crystal structure in which the film surface is oriented in a (001) surface.
  • the crystalline layer 12 ′ also has a crystal structure in which the film surface is oriented in the (001) surface.
  • the seed layer 13 ′ is Ru
  • the seed layer 13 ′ has a crystal structure in which the film surface is oriented in a (0001) surface.
  • the crystalline layer 12 ′ also has a crystal structure in which the film surface is oriented in the (0001) surface.
  • a material included in the seed layer 13 ′ is different from a material included in the REO layer 11 .
  • the seed layer 13 ′ and the REO layer 11 may include the same element.
  • the crystalline layer 12 ′ grows with the seed layer 13 ′ serving as a seed. Accordingly, the crystallization of the crystalline layer 12 ′ can be further promoted.
  • the modifications of the FIG. 13 and FIG. 14 are effective in controlling the orientation of the crystalline layer 12 ′ to an orientation other than that in which the surface energy is the smallest. This is because in the case where the orientation of the crystalline layer 12 ′ is controlled to the orientation in which the surface energy is the smallest, even if the seed layer 13 ′ does not exist, the crystalline layer 12 ′ naturally has the orientation in which the surface energy is the smallest by heat treatment.
  • the orientation in which the surface energy is the smallest is determined by the material of the crystalline layer 12 ′, that is, an element included in the crystalline layer 12 ′, or if the crystalline layer 12 ′ includes elements, the composition ratio thereof, etc.
  • the orientation of the crystalline layer 12 ′ is controlled to the orientation in which the surface energy is the smallest, the structure of FIG. 10A , FIG. 10B , FIG. 11 , or FIG. 12 is preferable. If the orientation of the crystalline layer 12 ′ is controlled to an orientation other than that in which the surface energy is the smallest, the structure of FIG. 13 or FIG. 14 is preferable.
  • the semiconductor device comprises the REO layer 11 a , the crystalline layer 12 a ′ above the REO layer 11 a , the seed layer 13 ′ above the crystalline layer 12 a ′, the crystalline layer 12 b ′ above the seed layer 13 ′, and the REO layer 11 b above the crystalline layer 12 b′.
  • the crystalline layer 12 a ′ is interposed between the REO layer 11 a and the seed layer 13 ′, and the crystalline layer 12 b ′ is interposed between the seed layer 13 ′ and the REO layer 11 b.
  • the crystalline layer 12 a ′ contact the REO layer 11 a and the seed layer 13 ′. It is preferable that the crystalline layer 12 b ′ contact the seed layer 13 ′ and the REO layer 11 b.
  • an interfacial layer may exist in at least one of the space between the REO layer 11 a and the crystalline layer 12 a ′ and the space between the crystalline layer 12 a ′ and the seed layer 13 ′.
  • an interfacial layer may exist in at least one of the space between the REO layer 11 b and the crystalline layer 12 b ′ and the space between the crystalline layer 12 b ′ and the seed layer 13 ′. It should be noted that the interfacial layers may exist under the condition that they do not influence the crystallization of the crystalline layers 12 a ′ and 12 b′.
  • a material included in the seed layer 13 ′ is different from a material included in the REO layer 11 a , 11 b .
  • the seed layer 13 ′ and the REO layer 11 a , 11 b may include the same element.
  • the crystallization of the crystalline layers 12 a ′ and 12 b ′ progresses successively from the seed layer 13 ′ side with the seed layer 13 ′ serving as a seed. According to the above-described principle, the continuity between the crystal structures is secured.
  • FIG. 16 shows a third embodiment.
  • FIG. 9 which is a modification of the first embodiment, is applied to a magnetoresistive element.
  • a semiconductor device comprises an REO layer 11 a , a crystalline magnetic layer 12 a above the REO layer 11 a , a nonmagnetic layer (seed layer) 13 above the crystalline magnetic layer 12 a , a crystalline magnetic layer 12 b above the nonmagnetic layer 13 , and an REO layer 11 b above the crystalline magnetic layer 12 b.
  • Case A is an example of the magnetoresistive element in which the crystalline magnetic layer 12 a is a storage layer and the crystalline magnetic layer 12 b is a reference layer, that is, a top-pin type magnetoresistive element.
  • Case B is an example of the magnetoresistive element in which the crystalline magnetic layer 12 a is a reference layer and the crystalline magnetic layer 12 b is a storage layer, that is, a bottom-pin type magnetoresistive element.
  • the crystalline magnetic layers 12 a and 12 b include at least one of Co, Fe, and Ni.
  • the crystalline magnetic layers 12 a and 12 b are, for example, CoFeB, FePtB, CoPdB, CoPtB, or NiPtB.
  • the nonmagnetic layer 13 includes at least one of magnesium oxide, aluminum oxide, zinc oxide, titanium oxide, aluminum nitride, boron nitride, and LSMO.
  • the crystalline magnetic layers 12 a and 12 b are oriented by heat treatment in the same crystal surface as that of the nonmagnetic layer 13 .
  • a material included in the nonmagnetic layer (seed layer) 13 is different from a material included in the REO layer 11 a , 11 b .
  • the nonmagnetic layer (seed layer) 13 and the REO layer 11 a , 11 b may include the same element.
  • the crystalline texture or the magnetic anisotropy of the magnetoresistive element can be improved. Accordingly, an improvement in the MR ratio, a reduction in the switching current, and an improvement in the thermal stability of the magnetoresistive element can be achieved.
  • FIG. 17 shows a fourth embodiment.
  • FIG. 13 or FIG. 14 which is a modification of the second embodiment, is applied to one of the elements of a semiconductor device, such as a conductive line or a contact plug.
  • the semiconductor device comprises an underlayer 20 , an REO layer 11 disposed in a depression in the underlayer 20 or above the underlayer 20 , a crystalline layer 12 ′, and a seed layer 13 ′.
  • the underlayer 20 is, for example, a semiconductor substrate or an interlayer insulating layer.
  • the semiconductor device comprises the REO layer 11 and the crystalline layer 12 ′ above the REO layer 11 in the depression in the underlayer 20 .
  • the semiconductor device comprises the seed layer 13 ′ above the crystalline layer 12 ′ and the underlayer 20 .
  • the semiconductor device comprises the seed layer 13 ′ and the crystalline layer 12 ′ above the seed layer 13 ′ in the depression of the underlayer 20 .
  • the semiconductor device comprises the REO layer 11 above the crystalline layer 12 ′ and the underlayer 20 .
  • the crystalline layer 12 ′ includes, for example, a metal element such as W, Al, or Cu.
  • the seed layer 13 ′ includes at least one of Pt, Pd, Rh, Ru, Ir, and Cr.
  • the crystalline layer 12 ′ is oriented by heat treatment in the same crystal surface as that of the seed layer 13 ′.
  • a material included in the seed layer 13 ′ is different from a material included in the REO layer 11 .
  • the seed layer 13 ′ and the REO layer 11 may include the same element.
  • the crystalline texture of one of the elements of the semiconductor device which requires a good crystalline layer, such as a conductive line or a contact plug, can be improved. Accordingly, the properties of the semiconductor device can be improved.
  • a fifth embodiment relates to a memory device comprising a magnetoresistive element.
  • FIG. 18 shows an MRAM as the memory device.
  • a memory cell array 30 comprises memory cells (magnetoresistive elements).
  • a row decoder 31 a and a column decoder 31 b randomly access one of the memory cells of the memory cell array 30 based on an address signal Addr.
  • a column select circuit 32 has the function of electrically connecting the memory cell array 30 and a sense amplifier 33 to each other based on a signal from the column decoder 31 b.
  • a read/write control circuit 34 supplies a read current to one selected memory cell of the memory cell array 30 .
  • the sense amplifier 33 detects the read current, thereby identifying data stored in the one selected memory cell.
  • the read/write control circuit 34 supplies a write current to one selected memory cell of the memory cell array 30 , thereby writing data to the one selected memory cell.
  • a control circuit 35 controls the operation of the row decoder 31 a , the column decoder 31 b , the sense amplifier 33 , and the read/write control circuit 34 .
  • FIG. 19 to FIG. 21 show the memory cells of the MRAM.
  • FIG. 19 is a plan view of the memory cells of the MRAM.
  • FIG. 20 is a sectional view along line XX-XX of FIG. 19 .
  • FIG. 21 is a sectional view along line XXI-XXI of FIG. 19 .
  • the memory cells of the magnetic memory each comprise a select transistor (for example, an FET) ST and a magnetoresistive element MTJ.
  • a select transistor for example, an FET
  • MTJ magnetoresistive element
  • the select transistor ST is disposed in an active area AA in a semiconductor substrate 21 .
  • the active area AA is surrounded by an element isolation insulating layer 22 in the semiconductor substrate 21 .
  • the element isolation insulating layer 22 has a shallow trench isolation (STI) structure.
  • the select transistor ST comprises source/drain diffusion layers 23 a and 23 b in the semiconductor substrate 21 , a gate insulating layer 24 and a gate electrode (word line) 25 formed therebetween in the semiconductor substrate 21 .
  • the select transistor ST of the example has the so-called buried gate structure in which the gate electrode 25 is buried in the semiconductor substrate 21 .
  • the structure of the fourth embodiment ( FIG. 17 ) is applicable to the gate electrode 25 .
  • An interlayer insulating layer (for example, a silicon oxide layer) 26 a covers the select transistor ST.
  • Contact plugs BEC and SC are disposed in the interlayer insulating layer 26 a .
  • the contact plug BEC is connected to the source/drain diffusion layer 23 a
  • the contact plug SC is connected to the source/drain diffusion layer 23 b .
  • the contact plugs BEC and SC include, for example, one of W, Ta, Ru, Ti, TiN, and TaN.
  • the structure of the fourth embodiment ( FIG. 17 ) is applicable to the contact plugs BEC and SC.
  • the magnetoresistive element MTJ is disposed on the contact plug BEC.
  • the magnetoresistive element MTJ have the structure of the third embodiment ( FIG. 16 ).
  • a contact plug TEC is disposed on the magnetoresistive element MTJ.
  • the contact plug TEC includes, for example, one of W, Ta, Ru, Ti, TiN, and TaN.
  • An interlayer insulating layer (for example, a silicon oxide layer) 26 b covers the magnetoresistive element MTJ.
  • a bit line BL 1 is connected to the magnetoresistive element MTJ via the contact plug TEC.
  • a bit line BL 2 is connected to the source/drain diffusion layer 23 b via the contact plug SC.
  • the bit line BL 2 also functions as, for example, a source line SL to which a ground potential is applied at the time of reading.
  • FIG. 22 and FIG. 23 show a method of manufacturing the MRAM of FIG. 19 to FIG. 21 .
  • the select transistor ST having a buried gate structure is formed in the semiconductor substrate 21 .
  • the interlayer insulating layer 26 a is formed, and the contact plug BEC is formed in the interlayer insulating layer 26 a.
  • a stacked structure comprising an REO layer 11 a , an amorphous magnetic layer 12 a - ⁇ , a nonmagnetic layer (seed layer) 13 , an amorphous magnetic layer 12 b - ⁇ , and an REO layer 11 b is formed on the interlayer insulating layer 26 a and the contact plug BEC.
  • the amorphous magnetic layers 12 a - ⁇ and 12 b - ⁇ are crystallized by, for example, lamp annealing.
  • the impurities in the amorphous magnetic layers 12 a - ⁇ and 12 b - ⁇ are substantially completely removed.
  • any elements do not diffuse from the REO layers 11 a and 11 b into the amorphous magnetic layers 12 a - ⁇ and 12 b - ⁇ . Accordingly, the amorphous magnetic layers 12 a - ⁇ and 12 b - ⁇ can be changed well into crystalline magnetic layers 12 a and 12 b.
  • the magnetoresistive element MTJ is patterned by a photoengraving process (PEP) and an RIE process.
  • PEP photoengraving process
  • RIE ion beam etching
  • elements such as the interlayer insulating layer 26 b , the contact plug TEC, and the bit line BL 1 are formed, whereby the MRAM of FIG. 19 to FIG. 21 is complete.
  • a processor used in a personal digital assistant have low power consumption.
  • One of the methods of reducing the power consumption of the processor is a method of replacing a static random access memory (SRAM)-based cache memory having high standby power consumption with a nonvolatile semiconductor memory in which a nonvolatile element is used.
  • SRAM static random access memory
  • the leakage power of an SRAM tends to be greater both during an operating time and a standby (nonoperating) time, as a transistor is miniaturized.
  • power supply can be shut off during the standby time, and the power consumption during the standby time can be reduced.
  • a low power consumption processor can be achieved by, for example, using the above-described magnetic random access memory (MRAM) as a cache memory.
  • MRAM magnetic random access memory
  • FIG. 24 shows an example of a low power consumption processor system.
  • a CPU 41 controls an SRAM 42 , a DRAM 43 , a flash memory 44 , a ROM 45 , and a magnetic random access memory (MRAM) 46 .
  • the MRAM 46 can be used as an alternative to any of the SRAM 42 , the DRAM 43 , the flash memory 44 , and the ROM 45 . With this, at least one of the SRAM 42 , the DRAM 43 , the flash memory 44 , and the ROM 45 may be omitted.
  • the MRAM 46 can be used as a nonvolatile cache memory (for example, an L2 cache).
  • the MRAM 46 also can be used as a storage class memory (SCM).
  • SCM storage class memory
  • the crystallization of the crystalline layer can be promoted. Accordingly, for example, in a magnetoresistive element, the crystalline texture or the magnetic anisotropy of a crystalline magnetic layer can be improved. Accordingly, an improvement in the MR ratio, a reduction in the switching current, and an improvement in the thermal stability of the magnetoresistive element can be achieved.

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