US20130285253A1 - Semiconductor device and method of manufacturing the same - Google Patents
Semiconductor device and method of manufacturing the same Download PDFInfo
- Publication number
- US20130285253A1 US20130285253A1 US13/837,212 US201313837212A US2013285253A1 US 20130285253 A1 US20130285253 A1 US 20130285253A1 US 201313837212 A US201313837212 A US 201313837212A US 2013285253 A1 US2013285253 A1 US 2013285253A1
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- Prior art keywords
- insulating film
- substrate
- film
- semiconductor device
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Definitions
- the present invention relates to a semiconductor device and a method of manufacturing a semiconductor device. More particularly, the present invention relates to a technique effectively applied to a semiconductor device in which a plurality of semiconductor substrates are electrically connected with each other via electrodes.
- silicon substrate semiconductor substrates each made of a single crystal silicon (hereinafter, referred to as silicon substrate) are laminated so that the silicon substrates are electrically connected to each other by using fine electrode wires.
- connection reliability of the bump electrodes which connect the silicon substrates with each other deteriorates due to a stress caused by heat and impacts applied to the silicon substrates.
- a technique for ensuring the connection reliability of the bump electrodes in which the bump electrodes are protected by sealing the periphery of the bump electrodes with an insulator such as a resin is essential.
- One of methods for sealing the periphery of the bump electrodes with the resin is a pre-coating method. This is a method for electrically connecting the bump electrodes with each other by, prior to a step for bonding two silicon substrates (for example, silicon wafers) having bump electrodes formed thereon with each other, coating each silicon substrate with a thermosetting resin represented by an epoxy resin, and then, thermally compression-bonding the two silicon substrates with each other.
- a pre-coating method This is a method for electrically connecting the bump electrodes with each other by, prior to a step for bonding two silicon substrates (for example, silicon wafers) having bump electrodes formed thereon with each other, coating each silicon substrate with a thermosetting resin represented by an epoxy resin, and then, thermally compression-bonding the two silicon substrates with each other.
- the resin adhered onto a surface of the connection of the bump electrodes sometimes enter a space between the bump electrodes upon the thermal compression-bonding. This entering causes a high contact resistance between the bump electrodes, and besides, a non-contact state between the bump electrodes or others, which result in a problem of a reduction of the connection reliability of the bump electrodes.
- Patent Document 1 Specific of U.S. Patent Application Laid-Open Publication No. 2007/0207592 discloses a method of forming a resin portion having an opening portion in a silicon substrate having an LSI formed thereon, and then, burying a bump electrode material into the opening portion of the resin, performing polishing so that there is no step between the resin and an upper surface of the bump electrode to be flattened, similarly forming the bump electrode and the resin in another silicon substrate having an LSI formed thereon, and bonding the resins formed on the two silicon substrates with each other and the electrodes thereon with each other by thermal compression bonding.
- Patent Document 2 Japanese Patent Application Laid-Open Publication No. H07-014982 discloses the following step as a method for bonding two substrates with each other. First, a protective insulating film (12) on a quartz substrate (30) side is opened, metal films (65 and 66) mainly made of Al are buried in the opening portion, and they are flattened on the same level as a surface of the protective insulating film (12). Further, a thick polycrystalline Si film (24) is deposited on a semiconductor integrated circuit device formed on another single crystal Si substrate (11), and polishing a surface of the film to be flattened, and then, forming an adhesive layer (23) made of a fluorine-based resin on the surface thereof.
- an opening portion reaching the semiconductor integrated circuit device is formed in the adhesive layer (23), and then, an insulting treatment is performed onto an opening portion side wall, metal films (67 and 68) mainly made of Al are buried into the opening portion and are flattened. Then, these substrates are bonded with each other (see FIGS. 25 and 26).
- Patent Document 1 includes a problem that gas is desorbed from the resin because heat is applied in the step of the connection between the silicon substrates, and is trapped in the surface of the connection between the resins to cause voids, which results in peeling of the silicon substrate by a subsequent dicing step.
- the technique described in the above-described Patent Document 2 includes a problem of a low heat resistance of the fluorine-based resin serving as the adhesive layer which is not suitable for the thermal compression-bonding between the substrates.
- the present inventors have tried the connection of the silicon substrates with each other by using a resin having a higher heat resistance (which is a heat-resistant resin) than that of the fluorine-based resin. As a result, the peeling has occurred between the substrates in such a step as the dicing step or a back-grinding step.
- a preferred aim of the present invention is to provide a technique capable of improving a property of the semiconductor device. More particularly, a preferred aim of the present invention is to form an electrode and a sealing resin with high productivity as solving the above-described problems included in the conventional techniques, and besides, exerting an effect for suppressing the voids upon the bonding so as to achieve the connection between the substrates with high reliability.
- a semiconductor device described in the typical embodiment of the inventions disclosed in the present application includes: a laminated insulating film having a first insulating film arranged on an upper portion of one surface of a first substrate and made of an inorganic film and a second insulating film arranged on the first insulating film and made of an organic film; and a first electrode arranged inside an opening portion opened by dry-etching the laminated insulating film, and the second insulating film is a heat-resistant insulating film.
- a method of manufacturing a semiconductor device described in the typical embodiment of the inventions disclosed in the present application is a method of manufacturing a semiconductor device for laminating a first substrate having a first electrode formed on one surface thereof and a second substrate having a second electrode formed on one surface thereof, and bonding the one surface of the first electrode and the one surface of the second electrode with each other, so that the first electrode and the second electrode are electrically connected with each other.
- the method includes: (a) a step of forming a first insulating film made of an organic film on the one surface of the first substrate; (b) a step of forming a second insulating film made of an organic film on the first insulating film; (c) a step of forming an opening portion by dry-etching the first insulating film and the second insulating film; (d) a step of forming the first electrode by burying a conductive film inside the opening portion; and (e) a step of bonding the one surface of the first substrate and the one surface of the second substrate with each other, and includes a step of performing a surface treatment on the second insulating film subsequent to the above-described step of (c) but prior to the above-described step of (e).
- a property of the semiconductor device can be improved.
- a semiconductor device having a good property can be manufactured. More particularly, by performing a surface treatment on an organic insulating film on the substrate surface subsequent to the step of forming the opening portion by the dry-etching but prior to the step of connecting the substrates with each other, the connectivity between the substrates can be improved so as to form a semiconductor device having high reliability.
- FIG. 1 is a cross-sectional view illustrating a semiconductor device of a first embodiment
- FIG. 2 is a cross-sectional view illustrating a structural example of a first substrate having an MISFET in a formation layer for a semiconductor element;
- FIG. 3 is a cross-sectional view illustrating a manufacturing step of the semiconductor device of the first embodiment
- FIG. 4 is a cross-sectional view illustrating the manufacturing step of the semiconductor device of the first embodiment, which is a cross-sectional view in the manufacturing step of the semiconductor device continued from FIG. 3 ;
- FIG. 5 is a cross-sectional view illustrating the manufacturing step of the semiconductor device of the first embodiment, which is a cross-sectional view in the manufacturing step of the semiconductor device continued from FIG. 4 ;
- FIG. 6 is a cross-sectional view illustrating the manufacturing step of the semiconductor device of the first embodiment, which is a cross-sectional view in the manufacturing step of the semiconductor device continued from FIG. 5 ;
- FIG. 7 is a cross-sectional view illustrating the manufacturing step of the semiconductor device of the first embodiment, which is a cross-sectional view in the manufacturing step of the semiconductor device continued from FIG. 6 ;
- FIG. 8 is a cross-sectional view illustrating the manufacturing step of the semiconductor device of the first embodiment, which is a cross-sectional view in the manufacturing step of the semiconductor device continued from FIG. 7 ;
- FIG. 9 is a cross-sectional view illustrating the manufacturing step of the semiconductor device of the first embodiment, which is a cross-sectional view in the manufacturing step of the semiconductor device continued from FIG. 8 ;
- FIG. 10 is a cross-sectional view illustrating the manufacturing step of the semiconductor device of the first embodiment, which is a cross-sectional view in the manufacturing step of the semiconductor device continued from FIG. 9 ;
- FIG. 11 is a cross-sectional view illustrating a structural example of a first substrate having a MISFET in a formation layer for a semiconductor element
- FIG. 12 is a cross-sectional view illustrating a manufacturing step of a semiconductor device of a second embodiment
- FIG. 13 is a cross-sectional view illustrating the manufacturing step of the semiconductor device of the second embodiment, which is a cross-sectional view in the manufacturing step of the semiconductor device continued from FIG. 12 ;
- FIG. 14 is a cross-sectional view illustrating the manufacturing step of the semiconductor device of the second embodiment, which is a cross-sectional view in the manufacturing step of the semiconductor device continued from FIG. 13 ;
- FIG. 15 is a cross-sectional view illustrating the manufacturing step of the semiconductor device of the second embodiment, which is a cross-sectional view in the manufacturing step of the semiconductor device continued from FIG. 14 ;
- FIG. 16 is a cross-sectional view illustrating the manufacturing step of the semiconductor device of the second embodiment, which is a cross-sectional view in the manufacturing step of the semiconductor device continued from FIG. 15 ;
- FIG. 17 is a cross-sectional view illustrating the manufacturing step of the semiconductor device of the second embodiment, which is a cross-sectional view in the manufacturing step of the semiconductor device continued from FIG. 16 ;
- FIG. 18 is a cross-sectional view illustrating the manufacturing step of the semiconductor device of the second embodiment, which is a cross-sectional view in the manufacturing step of the semiconductor device continued from FIG. 17 ;
- FIG. 19 is a cross-sectional view illustrating a manufacturing step of a semiconductor device of a third embodiment
- FIG. 20 is a cross-sectional view illustrating the manufacturing step of the semiconductor device of the third embodiment, which is a cross-sectional view in the manufacturing step of the semiconductor device continued from FIG. 19 ;
- FIG. 21 is a cross-sectional view illustrating the manufacturing step of the semiconductor device of the third embodiment, which is a cross-sectional view in the manufacturing step of the semiconductor device continued from FIG. 20 ;
- FIG. 22 is a cross-sectional view illustrating the manufacturing step of the semiconductor device of the third embodiment, which is a cross-sectional view in the manufacturing step of the semiconductor device continued from FIG. 21 ;
- FIG. 23 is a cross-sectional view illustrating the manufacturing step of the semiconductor device of the third embodiment, which is a cross-sectional view in the manufacturing step of the semiconductor device continued from FIG. 22 ;
- FIG. 24 is a cross-sectional view illustrating the manufacturing step of the semiconductor device of the third embodiment, which is a cross-sectional view in the manufacturing step of the semiconductor device continued from FIG. 23 ;
- FIG. 25 is a cross-sectional view illustrating the manufacturing step of the semiconductor device of the third embodiment, which is a cross-sectional view in the manufacturing step of the semiconductor device continued from FIG. 24 ;
- FIG. 26 is a cross-sectional view illustrating the manufacturing step of the semiconductor device of the third embodiment, which is a cross-sectional view in the manufacturing step of the semiconductor device continued from FIG. 25 ;
- FIG. 27 is a cross-sectional view illustrating a manufacturing step of a semiconductor device of a fourth embodiment
- FIG. 28 is a cross-sectional view illustrating the manufacturing step of the semiconductor device of the fourth embodiment, which is a cross-sectional view in the manufacturing step of the semiconductor device continued from FIG. 27 ;
- FIG. 29 is a cross-sectional view illustrating the manufacturing step of the semiconductor device of the fourth embodiment, which is a cross-sectional view in the manufacturing step of the semiconductor device continued from FIG. 28 ;
- FIG. 30 is a cross-sectional view illustrating the manufacturing step of the semiconductor device of the fourth embodiment, which is a cross-sectional view in the manufacturing step of the semiconductor device continued from FIG. 29 ;
- FIG. 31 is a cross-sectional view illustrating the manufacturing step of the semiconductor device of the fourth embodiment, which is a cross-sectional view in the manufacturing step of the semiconductor device continued from FIG. 30 ;
- FIG. 32 is a cross-sectional view illustrating the manufacturing step of the semiconductor device of the fourth embodiment, which is a cross-sectional view in the manufacturing step of the semiconductor device continued from FIG. 31 ;
- FIG. 33 is a cross-sectional view illustrating the manufacturing step of the semiconductor device of the fourth embodiment, which is a cross-sectional view in the manufacturing step of the semiconductor device continued from FIG. 32 ;
- FIG. 34 is a cross-sectional view illustrating a manufacturing step of a semiconductor device of a fifth embodiment
- FIG. 35 is a cross-sectional view illustrating the manufacturing step of the semiconductor device of the fifth embodiment, which is a cross-sectional view in the manufacturing step of the semiconductor device continued from FIG. 34 ;
- FIG. 36 is a cross-sectional view illustrating the manufacturing step of the semiconductor device of the fifth embodiment, which is a cross-sectional view in the manufacturing step of the semiconductor device continued from FIG. 35 ;
- FIG. 37 is another cross-sectional view illustrating the manufacturing step of the semiconductor device of the fifth embodiment.
- FIG. 38 is still another cross-sectional view illustrating the manufacturing step of the semiconductor device of the fifth embodiment.
- FIG. 39 is a cross-sectional view illustrating the manufacturing step of the semiconductor device of the fifth embodiment, which is a cross-sectional view in the manufacturing step of the semiconductor device continued from FIG. 36 ;
- FIG. 40 is a cross-sectional view illustrating the manufacturing step of the semiconductor device of the fifth embodiment, which is a cross-sectional view in the manufacturing step of the semiconductor device continued from FIG. 39 ;
- FIG. 41 is a cross-sectional view illustrating the manufacturing step of the semiconductor device of the fifth embodiment, which is a cross-sectional view in the manufacturing step of the semiconductor device continued from FIG. 40 ;
- FIG. 42 is a cross-sectional view illustrating the manufacturing step of the semiconductor device of the fifth embodiment, which is a cross-sectional view in the manufacturing step of the semiconductor device continued from FIG. 41 ;
- FIG. 43 is a cross-sectional view illustrating the manufacturing step of the semiconductor device of the fifth embodiment, which is a cross-sectional view in the manufacturing step of the semiconductor device continued from FIG. 42 ;
- FIG. 44 is a cross-sectional view illustrating the manufacturing step of the semiconductor device of the fifth embodiment, which is a cross-sectional view in the manufacturing step of the semiconductor device continued from FIG. 43 ;
- FIG. 45 is a cross-sectional view illustrating a manufacturing step of a semiconductor device of a sixth embodiment
- FIG. 46 is a cross-sectional view illustrating the manufacturing step of the semiconductor device of the sixth embodiment, which is a cross-sectional view in the manufacturing step of the semiconductor device continued from FIG. 45 ;
- FIG. 47 is a cross-sectional view illustrating the manufacturing step of the semiconductor device of the sixth embodiment, which is a cross-sectional view in the manufacturing step of the semiconductor device continued from FIG. 46 ;
- FIG. 48 is a cross-sectional view illustrating a manufacturing step of a semiconductor device of a seventh embodiment
- FIG. 49 is a cross-sectional view illustrating the manufacturing step of the semiconductor device of the seventh embodiment, which is a cross-sectional view in the manufacturing step of the semiconductor device continued from FIG. 48 ;
- FIG. 50 is a cross-sectional view illustrating the manufacturing step of the semiconductor device of the seventh embodiment, which is a cross-sectional view in the manufacturing step of the semiconductor device continued from FIG. 49 ;
- FIG. 51 is a graph illustrating a “C” ion amount on a surface portion of a PBO film.
- the invention will be described in a plurality of sections or embodiments when required as a matter of convenience. However, these sections or embodiments are not irrelevant to each other unless otherwise stated, and the one relates to the entire or a part of the other as a modification example, details, or a supplementary explanation thereof. Also, in the embodiments described below, when referring to the number of elements (including number of pieces, numerical values, amount, range, and others), the number of the elements is not limited to a specific number unless otherwise stated or except the case where the number is apparently limited to a specific number in principle. The number larger or smaller than the specified number is also applicable.
- the components are not always indispensable unless otherwise stated or except the case where the components are apparently indispensable in principle.
- the shape of the components, positional relation thereof, and others are described, the substantially approximate and similar shapes and others are included therein unless otherwise stated or except the case where it is conceivable that they are apparently excluded in principle.
- hatching is omitted even in a cross-sectional view so as to make the drawings easy to see.
- a size of each portion does not correspond to that of the actual device, and a specific portion is sometimes illustrated relatively larger so as to easily understand the drawings.
- FIG. 1 is a cross-sectional view illustrating the semiconductor device of the present embodiment.
- the semiconductor device of the present embodiment has a laminated structure of a first substrate “Sa” and a second substrate “Sb”.
- the first substrate Sa is a semiconductor substrate made of silicon in which a semiconductor element (not illustrated) is arranged on a front surface thereof (a first surface, an element surface, a surface on a formation side of a bump electrode, a surface on a formation side of the semiconductor element).
- a formation layer for the semiconductor element (an inner layer of the semiconductor element) is denoted by a symbol 100 a .
- a pad electrode (a pad region, a conductive film) 200 a is arranged on the formation layer 100 a for the semiconductor element.
- This pad electrode 200 a is a part of the uppermost layer wire, and becomes an externally-connecting portion.
- the uppermost layer wire is covered with an inorganic insulating film 300 a , and the pad electrode 200 a is exposed from an opening portion OA 1 of the inorganic insulating film 300 a.
- an inorganic insulating film (inorganic film) 400 a is arranged on the inorganic insulating film 300 a .
- a surface of this inorganic insulating film 400 a is flattened.
- an organic insulating film (organic film) 500 a is arranged on the inorganic insulating film 400 a .
- the organic insulating film 500 a has photosensitivity.
- an opening portion OA 2 is formed, and a bump electrode BPa is arranged inside the opening portion OA 2 .
- the opening portion OA 2 is formed by dry-etching the laminated insulating film TCa of the inorganic insulating film 400 a and the organic insulating film 500 a .
- the bump electrode BPa is formed by burying a conductive film (conductor film) therein. More specifically, it is formed by burying a barrier metal film 600 a , a seed film (not illustrated), and a Cu (copper) film 700 a therein. Also, a surface treatment is performed on the organic insulating film 500 a which is the uppermost layer of the first substrate Sa.
- the second substrate Sb also has the same structure as that of the first substrate Sa.
- the second substrate Sb is a semiconductor substrate made of silicon in which a semiconductor element (not illustrated) is arranged on a front surface thereof (a first surface, an element surface, a surface on a formation side of the bump electrode, a surface on a formation side of the semiconductor element).
- the formation layer for the semiconductor element (which is an inner layer of the semiconductor element) is denoted by 100 b .
- the formation layer 100 b for the semiconductor element is illustrated on the lower side of the second substrate Sa.
- the pad electrode (conductive film) 200 b is arranged on the formation layer 100 b for the semiconductor element (on the lower side in FIG. 1 ).
- This pad electrode 200 b is a part of the uppermost layer wire, and becomes an externally-connecting portion.
- the uppermost layer wire is covered with the inorganic insulating film 300 b , and the pad electrode 200 b is exposed from the opening portion OA 1 of the inorganic insulating film 300 b.
- an inorganic insulating film (inorganic film) 400 b is arranged on the inorganic insulating film 300 b (on the lower side in FIG. 1 .
- a surface of this inorganic insulating film 400 b (on the lower side in FIG. 1 ) is flattened.
- an organic insulating film (organic film) 500 b is arranged on the inorganic insulating film 400 b (on the lower side in FIG. 1 .
- the organic insulating film 500 b has photosensitivity.
- an opening portion OA 2 is arranged, and a bump electrode BPb is arranged inside the opening portion OA 2 .
- the opening portion OA 2 is formed by dry-etching the laminated insulating film TCb of the inorganic insulating film 400 b and the organic insulating film 500 b .
- the bump electrode BPb is formed by burying a conductive film (conductor film) therein. More specifically, it is formed by burying a barrier metal film 600 b , a seed film (not illustrated), and a Cu (copper) film 700 b therein. Also, a surface treatment is performed on the organic insulating film 500 b which is the uppermost layer of the second substrate Sa.
- the semiconductor device of the present embodiment has such a structure that the surface side of the first substrate Sa and the surface side of the second substrate Sb are bonded with each other so that the organic insulating films ( 500 a and 500 b ) and the bump electrodes (BPa and BPb) are in contact with each other.
- the elements to be formed on the formation layers ( 100 a and 100 b ) for the semiconductor elements are not limited, for example, a MISFET can be arranged.
- FIG. 2 is a cross-sectional view illustrating a structural example of the first substrate having the MISFET formed in the formation layer for the semiconductor element.
- a MISFET Metal Insulator Semiconductor Field Effect Transistor: MIS-Type Field Effect Transistor Qn is arranged on the surface of the first substrate Sa.
- This MISFET is an n-channel type MISFET, and is formed on a surface of a p-type well region 3 surrounded by an element isolation region 2 .
- the n-channel type MISFET includes: a gate insulating film 7 arranged on the surface of the p-type well region 3 ; a gate electrode 8 arranged on the gate insulating film 7 ; and a source/drain semiconductor region (n-type impurity diffusion layer) arranged in the first substrate Sa (p-type well region 3 ) on both sides of the gate electrode 8 . Moreover, a sidewall film SW made of an insulator is arranged on a side wall of the gate electrode 8 .
- the source/drain semiconductor region (n-type impurity diffusion layer) has so-called an LDD (Lightly Doped Drain) structure, which is composed of an n ⁇ -type semiconductor region 9 and an n + -type semiconductor region 11 that has an impurity concentration higher than that of the n ⁇ -type semiconductor region 9 .
- the n + -type semiconductor region 11 is arranged on each of the p-type well regions 3 on both sidess of the gate electrode 8 and the sidewall film SW, and the n ⁇ -type semiconductor region 9 is arranged on each of the p-type well regions 3 on both sides of the gate electrode 8 .
- Plugs P 1 to P 3 connect among the respective wires (M 1 to M 3 ) and between the wire M 1 and the MISFET (Qn).
- Symbols C 1 to C 3 denote contact holes.
- an interlayer insulating film IL 1 is arranged on the MISFET (Qn), and the plug P 1 is arranged inside the interlayer insulating film IL 1 .
- the wire M 1 is arranged on the interlayer insulating film IL 1 .
- An interlayer insulating film IL 2 is arranged on the wire M 1 , and the plug P 2 is arranged inside the interlayer insulating film IL 2 .
- the wire M 2 is arranged on the interlayer insulating film IL 3 .
- the wire M 3 is arranged on the interlayer insulating film IL 3 .
- the wire M 3 is the uppermost layer wire, and partially forms the pad electrode 200 a .
- the structure on the pad electrode 200 a is the same as described above.
- These wires (M 1 to M 3 ) are formed by patterning a metal film (for example, aluminum (Al) film) deposited by a sputtering method.
- a metal film for example, aluminum (Al) film
- the three-layered (M 1 to M 3 ) wire is exemplified.
- a multi-layered wire may be arranged.
- MISFET MISFET
- other elements such as a p-channel type MISFET, a transistor having a different structure (bipolar transistor, LDMOS (Laterally Diffused MOS)), a capacitative element, or various types of memories may be formed.
- a circuit formed by the above-described MISFET (Qn) or others a logic circuit, a memory circuit, or others is cited.
- the semiconductor element to be formed on the formation layer 100 a for the semiconductor element in the first substrate Sa and the semiconductor element to be formed on the formation layer 100 b for the semiconductor element in the second substrate S 2 are not necessarily the same as each other, and, for example, the first substrate Sa may be laminated as a logic-use substrate, and the second substrate Sb may be laminated as a memory-use substrate. Moreover, the first substrate Sa and the second substrate Sb may be laminated as system substrates each on which a logic and a memory are embedded.
- a MEMS Micro Electro Mechanical Systems
- the MEMS is a device obtained by integrally forming an element such as a sensor or an actuator and an electronic circuit on a substrate.
- the sensor may be formed on the first substrate Sa
- the electronic circuit may be formed on the second substrate Sb, and these substrates may be laminated.
- FIGS. 3 to 10 are cross-sectional views illustrating the manufacturing steps of the semiconductor device of the present embodiment.
- the first substrate Sa having the formation layer 100 a for the semiconductor element and the pad electrode 200 a formed thereon is prepared.
- the uppermost layer wire including the pad electrode 200 a is formed by patterning a metal film (for example, an aluminum (Al) film) deposited thereon by a sputtering method.
- a silicon nitride film serving as the inorganic insulating film 300 a is deposited on the pad electrode 200 a by a CVD (Chemical Vapor Deposition) method or others.
- CVD Chemical Vapor Deposition
- the opening portion OA 1 from which the surface of the pad electrode 200 a is exposed is formed ( FIG. 4 ).
- a photoresist film (not illustrated) is formed on the inorganic insulating film. 300 a , and the photoresist film on the pad electrode 200 a is removed by exposure and development.
- the opening portion OA 1 is formed by etching the inorganic insulating film 300 a with using this photoresist film as a mask.
- the photoresist film is removed by asking or others. Such steps as the formation of the photoresist film to the removal thereof are referred to as patterning.
- a silicon oxide film serving as the inorganic insulating film 400 a is deposited on an upper portion of the first substrate Sa including an upper portion of the opening portion OA 1 so as to have a thickness of about 500 nm by the CVD method or others.
- a concavo-convex portion corresponding to an overlapped portion between the pad electrode 200 a and the inorganic insulating film 300 a is formed on the surface of the inorganic insulating film 400 a .
- the surface of the inorganic insulating film 400 a is polished by a CMP (Chemical Mechanical Polishing) method. In this manner, the surface of the inorganic insulating film 400 a is flattened. While the silicon oxide film is used as the inorganic insulating film 400 a here, not only this but also a silicon nitride film or others can be used.
- the organic insulating film 500 a is formed on the inorganic insulating film 400 a .
- a photosensitive insulating film is used as the organic insulating film 500 a .
- an insulating film (PBO film) made of polybenzoxazole (PBO) as a main component may be used as such a photosensitive organic insulating film 500 a .
- the PBO film can be formed by heating a polybenzoxazole precursor in a nitrogen atmosphere.
- the polybenzoxazole precursor compound is illustrated by [Chemical Formula 1] below. This compound is soluble in an alkaline solution.
- an alkaline solution of the precursor compound [Chemical Formula 1] is used with further adding a photosensitizing agent (for example, naphthoquinone diazide compound) thereto.
- a photosensitizing agent for example, naphthoquinone diazide compound
- the ring closure of the precursor compound is caused by heating, so that a cured chemical compound illustrated by [Chemical Formula 2] is formed.
- the photosensitive organic insulating film (photosensitive resin film) 500 a made of the PBO film is formed.
- a film thickness of the PBO film is about 1500 nm.
- This PBO film is made of a resin (heat-resistant resin, heat-resistant insulating film) having a higher heat resistance than that of a fluorine-based resin, and is preferably used for the present embodiment including a thermal compression-bonding step which will be described later.
- the organic insulating film 500 a in the formation region of the opening portion OA 2 is exposed to light.
- the exposed organic insulating film 500 a is removed.
- the inorganic insulating film 400 a is etched by using a dry-etching method with using the organic insulating film 500 a as a mask.
- dry-etching gas is changed into plasma and is reacted with the inorganic insulating film 400 a , so that an etching process is performed.
- the dry-etching gas for example, a fluorocarbon-based gas is used.
- the opening portion OA 2 from which the pad electrode 200 a is exposed is formed inside the laminated insulating film TCa formed of the inorganic insulating film 400 a and the organic insulating film 500 a .
- the formation region of the opening portion OA 2 is positioned inside the formation region of the opening portion OA 1 , and has a shape (a planar shape viewed from above) of, for example, a circle shape whose diameter is about 5 ⁇ m.
- a surface treatment is performed on the surface of the organic insulating film 500 a .
- a hydrogen radical treatment is performed.
- a gas containing hydrogen (H) radicals is sprayed onto the surface of the organic insulating film 500 a .
- the modification includes removal (etching) of a surface constituent material of the organic insulating film 500 a and change in a composition of a constituent material.
- a barrier metal film 600 a is formed on the organic insulating film 500 a including the inside of the opening portion OA 2 .
- the barrier metal film 600 a for example, a TiN (titanium nitride) film is deposited so as to have a thickness of about 70 nm by using a sputtering method or others.
- This barrier metal film 600 a is formed in order to prevent diffusion of Cu (copper) into the organic insulating film 500 a , the Cu being buried inside the opening portion OA 2 in a later step.
- a Cu film having a film thickness of about 100 nm is deposited as a seed film (not illustrated) by the sputtering method.
- a Cu film 700 a is deposited so as to have a thickness of about 3 ⁇ m by using an electrolytic plating method. In this manner, the inside of the opening portion OA 2 is filled with the Cu film 700 a.
- the Cu film 700 a , the seed film, and the barrier metal film 600 a on the organic insulating film 500 a are polished by using the CMP method.
- a bump electrode BPa formed of the Cu film 700 a , the seed film, and the barrier metal film 600 a is formed inside the opening portion OA 2 .
- an inorganic insulating film 300 b having the opening portion OA 1 is formed on the second substrate Sa, a laminated insulating film TCb formed of an inorganic insulating film 400 b and an organic insulating film 500 b is subsequently formed, and then, an opening portion OA 2 is formed by a dry-etching process. Then, a surface treatment is performed on a surface of the organic insulating film 500 b , and a bump electrode BPb formed of a Cu film 700 b , a seed film, and a barrier metal film 600 b is formed inside the opening portion OA 2 .
- a front surface of the first substrate Sa (first surface, element surface, surface on the formation side for the bump electrode, surface on the formation side for the semiconductor element) and a front surface of the second substrate Sb (first surface, element surface, surface on the formation side for the bump electrode, surface on the formation side for the semiconductor element) are faced and overlapped to each other, and then, are compressed to be bonded under a high temperature such as 300° C. or higher, so that these substrates are bonded to each other (in the thermal compression-bonding, FIG. 1 ).
- the electrical connection between the bump electrodes (BPa and BPb) formed on the respective first substrate Sa and second substrate Sb and the bonding between the organic insulating films ( 500 a and 500 b ) are simultaneously performed.
- each of a rear surface of the first substrate Sa (second surface, surface opposite to the surface on the formation side for the semiconductor element) and a rear surface of the second substrate Sb (second surface, surface opposite to the surface on the formation side for the semiconductor element) is polished (by the back-grinding process) so as to form a thin film whose substrate thickness is about 25 ⁇ m.
- the first substrate Sa and the second substrate Sb in a wafer state are cut (diced) along scribe lines so as to be individual pieces (chipped).
- the surface treatment for the organic insulating films ( 500 a and 500 b ) is performed subsequent to the formation of the opening portion OA 2 but prior to the formation of the bump electrodes (BPa and BPb).
- the surface treatment for the organic insulating films ( 500 a and 500 b ) may be performed subsequent to the formation of the bump electrodes (BPa and BPb) but prior to the thermal compression-bonding between the substrates.
- the laminated insulating film TCa formed of the inorganic insulating film 400 a and the organic insulating film 500 a is used as the insulating film on the pad electrode 200 a , and therefore, an amount of the organic insulating film 500 a is comparatively reduced so that degassing (the desorbed gas) can be reduced in the heating and compression-bonding processes for the first substrate Sa and the second substrate Sa. Therefore, the occurrence of voids upon the compression-bonding process can be suppressed.
- the insulating film on the pad electrode 200 a is formed of only the organic insulating film, a film thickness thereof increases, and a degree of the degassing due to the heating increases.
- the side wall of the opening portion is adversely formed into a tapered shape.
- the degassing can be reduced, the peeing between the substrates due to the bonding failure between the substrates can be reduced. Moreover, the connection failure between the bump electrodes can be reduced. As described above, the properties of the semiconductor device can be improved.
- the surface treatment on the surface of the organic insulating film 500 a is performed prior to the thermal compression-bonding between the substrates, and therefore, the adhesive property between the organic insulating films ( 500 a and 500 b ) can be improved.
- a thermal compression-bonding process was performed based upon the above-described processes (see FIGS. 3 to 9 ) on the first substrate Sa and the second substrate Sb in a wafer state, so that a laminated substrate A was manufactured. That is, with respect to the substrates (Sa, Sb), a surface treatment was performed on the organic insulating film ( 500 a , 500 b ) subsequent to the formation of the opening portion OA 2 but prior to the formation of the bump electrodes (BPa, BPb), and these substrates (Sa, Sb) were thermally compressed and bonded to each other.
- a thermal compression-bonding process was performed on each of the first substrate Sa and the second substrate Sb in a wafer state with the timing of the surface treatment being changed, so that a laminated substrate B was manufactured. That is, a surface treatment was performed on the organic insulating films ( 500 a , 500 b ) subsequent to the formation of the bump electrodes (BPa, BPb) but prior to the thermal compression-bonding between the substrates, and these substrates (Sa, Sb) were thermally compressed and bonded to each other.
- the first substrate Sa and the second substrate Sb in a wafer state were thermally compressed and bonded to each other without performing the surface treatment thereon so that a laminated substrate C was manufactured.
- each of the first substrate Sa and the second substrate Sb was subjected to a back grinding treatment so as to have a film thickness of about 25 ⁇ m.
- a peeling occurred between the substrates during the back grinding treatment.
- the laminated substrates A and B no peeling was confirmed between the substrates.
- the adhesive force between the substrates can be improved by the surface treatment on the inorganic insulating films ( 500 a , 500 b ).
- the adhesive force between the substrates can be improved even when the timing of the surface treatment is changed as long as the surface treatment was performed prior to the thermal compression-bonding process.
- the PBO film was formed on a substrate, and an Ar (argon) plasma treatment was performed thereon as a damaging treatment, so that a substrate I was manufactured.
- This damaging treatment simulates an Ar plasma state caused by the dry-etching.
- the PBO film was formed on a substrate, and after the Ar (argon) plasma treatment was performed thereon as the damaging treatment, a hydrogen radical treatment was performed thereon as the surface treatment, so that a substrate II was manufactured.
- the PBO film was formed on a substrate, and both of the damaging treatment and the surface treatment are not performed thereon, so that a substrate III was manufactured as a reference.
- FIG. 51 illustrates a graph indicating a C-ion amount on the surface portion of the PBO film.
- a longitudinal axis of the graph indicates a change degree (a. u.) of the C-ion amount.
- a horizontal axis of the graph indicates the depth (nm) from the PBO film surface.
- the C-ion amount on the surface of the PBO film is increased by the Ar plasma treatment.
- the hydrogen radical treatment was performed subsequent to the Ar plasma treatment, the C-ion amount was the same degree (in a range of ⁇ 5%) as that of the reference.
- variation in the C-ion amount in the surface portion (with the depth of 30 nm from the surface) of the PBO film was not as large as that of the Ar plasma treatment, and was the same degree as that of the reference.
- the adhesive property between the substrates can be improved by performing the surface treatment (for example, hydrogen plasma treatment) on the surfaces (of the organic insulating films 500 a and 500 b ) of each of the substrates subsequent to the dry-etching the organic insulating films ( 500 a , 500 b ) but prior to the thermal compression-bonding between the substrates (Sa, Sb).
- the surface treatment for example, hydrogen plasma treatment
- the PBO film is used as the organic insulating film ( 500 a , 500 b ).
- an organic insulating film made of polyimide as a main component an organic insulating film made of benzocyclobutene as a main component, or others may be used.
- These films are also heat-resistant insulating films, and are preferably used for the present embodiment including the thermal compression-bonding process.
- the heat-resistant insulating film is defined as an insulating film whose temperature causing a weight loss of 1% is about 300° C. or higher.
- the PBO film and polyimide there are many types having a positive-type photosensitive property. Therefore, a solvent-free developer can be used by selecting them, and effects on the environment can be reduced. Moreover, when benzocyclobutene is used, side products are difficult to be caused in the cyclization reaction of the host framework, and an organic insulating film having superior characteristics can be formed. Even when the organic insulating film is formed by using the above-described material, gas is easy to be caused due to heating if the film is used as a single layer. Therefore, by forming the insulating film on the pad electrode 200 a as the laminated structure of the inorganic insulating film and the organic insulating film, the degassing degree can be reduced.
- the above-described materials are also carbon-content chemical compounds, and there is a concern about the generation of the damaged layer at the time of the dry-etching process. Therefore, by performing a surface treatment (for example, hydrogen plasma treatment) thereon, the adhesive property between the substrates can be improved.
- a surface treatment for example, hydrogen plasma treatment
- a silicon oxide film formed by the CVD method is used as the inorganic insulating film 400 a , and the surface thereof is polished by the CMP method.
- the flattening may be performed simultaneously with the film formation, and therefore, the polishing process may be eliminated.
- the timing of the surface treatment may be either of (1) subsequent to the formation of the opening portion OA 2 but prior to the formation of the bump electrodes (BPa, BPb) or (2) subsequent to the formation of the bump electrodes (BPa, BPb) but prior to the thermal compression-bonding between the substrates, or may be both of the timings.
- the hydrogen radical treatment is exemplified as the surface treatment.
- a hydrogen plasma treatment, an ammonia radical treatment, an ammonia plasma treatment, an oxygen plasma treatment, or an oxygen radical treatment may be performed. That is, a treatment under atmosphere of gas having such active species or a treatment of spraying the gas is performed.
- the organic insulating films ( 500 a , 500 b ) whose compositions are the same as each other and the bump electrodes (BPa, BPb) whose compositions are the same as each other are bonded.
- the constituent metal of the other hump electrode (for example, BPb) may be a different one.
- the other organic insulating film (for example, 500 b ) may be another insulating film (for example, an inorganic insulating film).
- first substrate Sa and the second substrate Sb in the wafer state thermally compressed and bonded, and then, are cut (diced) so as to be individual pieces (chipped).
- each of the first substrate Sa and the second substrate Sb in the wafer state may be formed so as to be individual pieces, and then, thermally compressed and bonded.
- the inorganic insulating film 300 a is deposited ( FIG. 4 ).
- a wiring trench is formed inside the inorganic insulating film 300 a , and a metal film (for example, Cu (copper) film) is buried inside this wiring trench, so that the pad electrode 200 a is formed.
- FIG. 11 is a cross-sectional view illustrating a structural example of a first substrate having the MISFET in the formation layer for the semiconductor element.
- FIGS. 12 to 18 are cross-sectional views illustrating the manufacturing steps of the semiconductor device of the present embodiment.
- the semiconductor device of the present embodiment has the laminated structure formed of the first substrate Sa and the second substrate Sa.
- a different point from FIG. 1 of the first embodiment is that the pad electrode 200 a is buried inside the wiring trench inside the inorganic insulating film 300 a . Therefore, in the present embodiment, as different from the first embodiment, the convex-concavo portion corresponding to the overlapped portion between the pad electrode 200 a and the inorganic insulating film 300 a is not caused, so that the surface of the pad electrode 200 a and the surface of the inorganic insulating film 300 a are on the same level. In other words, the surface of the pad electrodes 200 a and the surface of the inorganic insulating film 300 a are flattened. Moreover, the same goes for the pad electrode 200 b and the inorganic insulating film 300 b of the second substrate Sa. Note that, since the structures of other parts are the same as those of the first embodiment ( FIG. 1 ), the explanation thereof will be omitted.
- the opening portion OA that is opened by dry-etching the laminated insulating film TCa of the inorganic insulating film 400 a and the organic insulating film 500 a is arranged on the pad electrode 200 a .
- the opening portion OA that is opened by dry-etching the laminated insulating film TCb of the inorganic insulating film 400 b and the organic insulating film 500 b is arranged on the pad electrode 200 b .
- the surface treatment is performed on each of the organic insulating films 500 a and 500 b.
- the bump electrodes BPa and BPb are arranged, respectively.
- the surface side of the first substrate Sa and the surface side of the second substrate Sb are bonded to each other so that the organic insulating films ( 500 a , 500 b ) and the bump electrodes (BPa, BPb) are in contact with each other.
- the elements to be formed in the formation layers ( 100 a , 100 b ) for the semiconductor elements positioned in the lower layers of the pad electrodes ( 200 a , 200 b ) are not limited, and a MISFET or others can be arranged as similar to the first embodiment ( FIG. 2 ).
- the wires (M 1 to M 3 ) are formed by the patterning in FIG. 2 , these may be formed by the burying of a metal film.
- a plug P 1 is arranged inside the interlayer insulating film IL 1 on the MISFET (Qn).
- the structures of the MISFET (Qn), the interlayer insulating film IL 1 and the plug P 1 are the same as those of the first embodiment ( FIG. 2 ).
- IL 2 a is arranged on the interlayer insulating film IL 2 a .
- An interlayer insulating film IL 2 b is arranged on the wire M 1 , and a plug P 2 is arranged in the interlayer insulating film IL 2 b .
- a wire M 2 buried in a wiring-trench insulating film IL 3 a is arranged on the interlayer insulating film IL 3 b .
- An interlayer insulating film IL 3 b is arranged on the wire M 2 , and a plug P 3 is arranged in the interlayer insulating film IL 3 b .
- a wire M 3 buried in the inorganic insulating film 300 a is arranged on the interlayer insulating film IL 3 b .
- the wire M 3 is the uppermost layer wire, and a part thereof becomes the pad electrode 200 a .
- the wires M 1 to M 3 may be provided as buried wires (Damascene wires).
- the first substrate Sa having the formation layer 100 a for the semiconductor element and the pad electrode 200 a formed thereon is prepared.
- the uppermost layer wire including the pad electrode 200 a is formed by burying a metal film (for example, a Cu film) in the wiring trench inside the inorganic insulating film 300 a.
- a silicon oxide film serving as the inorganic insulating film 400 a is deposited on the inorganic insulating film 300 a including the upper portion of the pad electrode 200 a by the CVD method or others so as to have a thickness of about 500 nm.
- the surface of the pad electrode 200 a and the surface of the inorganic insulating film 300 a have almost the same height as each other, and are flattened, the surface of the inorganic insulating film 400 a is also almost flattened. Therefore, the polishing step for the surface of the inorganic insulating film 400 a in the first embodiment can be eliminated.
- an organic insulating film 500 a is formed on the inorganic insulating film 400 a .
- a PBO film is formed as the organic insulating film 500 a as similar to the first embodiment.
- an opening portion OA is formed in the organic insulating film 500 a by exposure and development processes, and the inorganic insulating film 400 a is further dry-etched with using the organic insulating film 500 a as a mask.
- the opening portion OA from which the pad electrode 200 a is exposed is formed inside the laminated insulating film TCa of the inorganic insulating film 400 a and the organic insulating film 500 a.
- a surface treatment is performed on the surface of the organic insulating film 500 a .
- the surface treatment for example, gas containing hydrogen radicals is sprayed onto the surface of the organic insulating film 500 a .
- the surface of the organic insulating film 500 a is modified.
- a barrier metal film 600 a , a seed film (not illustrated) and a Cu film 700 a are formed on the organic insulating film 500 a including the inside of the opening portion OA as similar to the first embodiment.
- the Cu film 700 a , the seed film and the barrier metal film 600 a on the organic insulating film 500 a are polished by using the CMP method.
- a bump electrode BPa formed of the Cu film 700 a , the seed film and the barrier metal film 600 a is formed inside the opening portion OA 2 .
- the opening portion OA is formed by forming the laminated insulating film TCb of the inorganic insulating film 400 b and the organic insulating film. 500 b , and then, performing the dry-etching process thereon. Then, a surface treatment is performed on the surface of the organic insulating film 500 b , and a bump electrode BPb formed of a Cu film 700 b , a seed film and a barrier metal film 600 b is formed inside the opening portion OA.
- a front surface of the first substrate Sa (first surface, element surface, surface on the formation side of the bump electrode, surface on the formation side of the semiconductor element) and a front surface of the second substrate Sb (first surface, element surface, surface on the formation side of the bump electrode, surface on the formation side of the semiconductor element) are faced and overlapped with each other, and then, are compressed and bonded under a high temperature, so that these substrates are bonded to each other (in thermal compression-bonding).
- electrical connections between the bump electrodes (BPa, BPb) formed on the respective first substrate Sa and second substrate Sb and bonding between the organic insulating films ( 500 a , 500 b ) are simultaneously performed.
- each of a rear surface of the first substrate Sa (second surface, surface opposite to the surface on the formation side of the semiconductor element) and a rear surface of the second substrate Sb is subjected to a back grinding process so as to be a thin film whose substrate thickness is about 25 ⁇ m.
- the first substrate Sa and the second substrate Sb in the wafer state are cut along scribe lines so as to be individual pieces.
- the surface treatment on the organic insulating films ( 500 a , 500 b ) is performed subsequent to the formation of the opening portion OA but prior to the formation of the bump electrodes (BPa, BPb).
- the surface treatment on the organic insulating films ( 500 a , 500 b ) may be performed subsequent to the formation of the bump electrodes (BPa, BPb) but prior to the thermal compression-bonding between the substrates.
- the laminated insulating film TCa of the inorganic insulating film 400 a and the organic insulating film 500 a is used as the insulating film on the pad electrode 200 a , and therefore, the degassing from the organic insulating film 500 a can be reduced in the heating and compression-bonding processes for the first substrate Sa and the second substrate Sa. Therefore, the occurrence of voids upon the compression-bonding process can be suppressed, and the peeling between the substrates due to the bonding failure between the substrates can be reduced. Moreover, the connection failure between the bump electrodes can be reduced. Thus, the characteristics of the semiconductor device can be improved.
- the surface treatment is performed on the surface of the organic insulating film 500 a prior to the thermal compression-bonding between the substrates, and therefore, the adhesive property between the organic insulating films ( 500 a , 500 b ) can be improved.
- the bump electrode BPa is formed on the front surface side (first surface, element surface, surface on the formation side of the bump electrode, surface on the formation side of the semiconductor element) of the first substrate Sa.
- the bump electrode BP is formed on the rear surface side (second surface, surface on the side opposite to the formation side of the semiconductor element) of the first substrate Sa.
- FIGS. 19 to 26 are cross-sectional views illustrating the manufacturing steps of the semiconductor device of the present embodiment.
- FIG. 25 that is one of the cross-sectional views illustrating the manufacturing steps of the semiconductor device of the present embodiment
- the rear surface of the first substrate Sa (second surface, surface on the side opposite to the formation side of the semiconductor element) is illustrated as an upper side. Therefore, the formation layer for the semiconductor element (the inner layer of the semiconductor element) 100 formed on the front surface (first surface, element surface, surface on the formation side of the semiconductor element) of the first substrate Sa is positioned on a lower side of the first substrate Sa. Further below the formation layer 100 for the semiconductor element, the pad electrode (conductive film) 200 is arranged.
- a laminated insulating film TC formed of an inorganic insulating film 401 and an organic insulating film 501 is arranged on the rear surface of the first substrate Sa.
- a laminated insulating film TC formed of an inorganic insulating film 401 and an organic insulating film 501 is arranged on the rear surface of the first substrate Sa.
- an opening portion (through hole) TH which penetrates therethrough and reaches the pad electrode 200 is provided.
- a bump electrode BP is arranged inside the opening portion TH.
- the rear surface side of the first substrate Sa and the front surface side of the second substrate Sb explained in the second embodiment are bonded with each other so that the organic insulating films ( 501 and 500 b ) are in contact with each other as well as the bump electrodes (BP and BPb) are in contact with each other.
- an opening portion TH that is opened by dry-etching the laminated insulating film Tc of the inorganic insulating film 401 and the organic insulating film 501 is arranged in the upper portion of the pad electrode 200 ( FIG. 25 ). Moreover, a surface treatment is performed on the organic insulating film 501 .
- the first substrate Sa having the formation layer 100 for the semiconductor element and the pad electrode 200 formed thereon is prepared.
- the uppermost layer wire including the pad electrode 200 is formed by burying a metal film (for example, a Cu film) in the wiring trench inside the inorganic insulating film 300 as similar to the second embodiment.
- the back grinding process is performed so that the thickness of the first substrate Sa is a predetermined thickness (for example, about 25 ⁇ m) when the rear surface of the first substrate Sa (which is the second surface, surface on the side opposite to the formation side of the semiconductor element) is set as the upper side.
- a silicon oxide film is deposited on the first substrate Sa as an inorganic insulating film 401 by using the CVD method or others so as to have a thickness of about 500 nm.
- an organic insulating film 501 is formed on the inorganic insulating film 401 .
- the PBO film is formed as the organic insulating film 501 .
- the organic insulating film 501 in the formation region for the opening portion TH is removed by the exposure and development processes.
- the inorganic insulating film 401 , the first substrate Sa and the formation layer 100 for the semiconductor elements are etched with using the organic insulating film 501 as a mask.
- the opening portion TH is formed so as to penetrate through the inorganic insulating film 401 , the organic insulating film 501 , the first substrate Sa, and the formation layer 100 for the semiconductor element and reach the pad electrode 200 .
- a formation region of the opening portion TH is laid out in association with the pad electrode 200 , and is previously designed so that no semiconductor element is formed in this region.
- a surface treatment is performed on the surface of the organic insulating film 501 (which is the rear surface of the first substrate Sa).
- the surface treatment for example, gas containing hydrogen radicals is sprayed onto the surface of the organic insulating film 501 .
- the surface of the organic insulating film 501 is modified.
- an insulating film 301 is formed on the organic insulating film 501 including the inside of the opening portion TH.
- a silicon oxide film is formed by using the CVD method or others.
- FIG. 24 by anisotropically etching the insulating film 301 , the insulating film 301 is left only on the side wall of the opening portion TH. Thus, the insulating film 301 is removed from the bottom portion of the opening portion TH so that the pad electrode 200 is exposed.
- the insulating film 301 on the bottom portion of the opening portion TH and on the organic insulating film 501 may be removed therefrom so as to form the insulating film 301 covering the side wall of the opening portion TH.
- a barrier metal film 601 is formed on the organic insulating film 501 including the inside of the opening portion TH.
- a TiN film is deposited by using a sputtering method or others so as to have a thickness of about 70 nm.
- a Cu film is deposited as a seed film (not illustrated) by the sputtering method so as to have a film thickness of about 100 nm.
- a Cu film 701 is deposited on the upper portion of the seed film so as to have a thickness of about 3 ⁇ m by using an electrolytic plating method.
- the Cu film 701 , the seed film and the barrier metal film 601 on the organic insulating film 501 are polished by using the CMP method.
- the bump electrode BP formed of the Cu film 701 , the seed film and the barrier metal film 601 is formed inside the opening portion TH.
- the second substrate Sb as explained in the second embodiment is prepared, and as illustrated in FIG. 26 , the front surface of the second substrate Sb (which is the first surface, element surface, surface on the formation side of the bump electrode, surface on the formation side of the semiconductor element) and the rear surface of the first substrate Sa (which is the second surface, surface on the side opposite to the formation side of the semiconductor element) are faced and overlapped with each other, and then, these substrates are thermally compressed and bonded.
- electrical connection between the bump electrodes (BP, BPb) formed on the respective first substrate Sa and second substrate Sb and bonding between the organic insulating films ( 501 , 500 b ) thereon are simultaneously performed.
- the rear surface of the second substrate Sb is subjected to a back grinding process so as to be a thin film whose substrate thickness is as about 25 ⁇ m.
- the first substrate Sa and the second substrate Sb in a wafer state are cut along scribe lines to be individual pieces.
- the surface treatment on the organic insulating film 501 is performed subsequent to the formation of the opening portion TH but prior to the formation of the bump electrodes BP.
- the surface treatment on the organic insulating film 501 may be performed subsequent to the formation of the bump electrode BP but prior to the thermal compression-bonding between the substrates.
- the laminated insulating film TC of the inorganic insulating film 401 and the organic insulating film 501 is formed on the rear surface of the first substrate Sa, and therefore, the degassing from the organic insulating film 501 can be reduced in the heating and compression-bonding processes for the first substrate Sa and the second substrate Sa. Therefore, the occurrence of voids upon the compression-bonding process can be suppressed, and the peeling between the substrates due to bonding failure between the substrates can be reduced. Moreover, the connection failure between the bump electrodes can be reduced. In this manner, the characteristics of the semiconductor device can be improved.
- the surface treatment is performed on the surface of the organic insulating film 501 prior to the thermal compression-bonding between the substrates, and therefore, the adhesive property between the organic insulating films ( 501 , 500 b ) can be improved.
- a bump electrode TBP on the rear surface side of the first substrate Sa (which is the second surface, surface on the side opposite to the formation side of the semiconductor element) is formed as a laminated structure formed of a first bump electrode 1 BP and a second bump electrode 2 BP.
- FIGS. 27 to 33 are cross-sectional views illustrating the manufacturing steps of the semiconductor device of the present embodiment.
- FIG. 32 that is one of the cross-sectional views illustrating the manufacturing steps of the semiconductor device of the present embodiment
- the rear surface of the first substrate Sa (which is the second surface, surface on the side opposite to the formation side of the semiconductor element) is illustrated as the upper side. Therefore, the formation layer 100 for the semiconductor element (which is the inner layer of the semiconductor element) formed in the front surface of the first substrate Sa (which is the first surface, element surface, surface on the formation side of the bump electrode, surface on the formation side of the semiconductor element) is positioned on the lower side of the first substrate Sa. Further below the formation layer 100 for the semiconductor element, the pad electrode (conductive film) 200 is arranged.
- a laminated insulating film TC of an inorganic insulating film 401 and an organic insulating film 501 is arranged on the rear surface of the first substrate Sa.
- this laminated insulating film TC an opening portion (through hole) TH 2 is formed inside the opening portion TH 2 .
- the second bump electrode 2 BP is arranged inside the opening portion TH 2 .
- an opening portion (through hole) TH 1 reaching the pad electrode 200 is formed inside the opening portion TH 1 .
- the first bump electrode 1 BP is arranged inside the opening portion TH 1 .
- the first bump electrode 1 BP and the second bump electrode 2 BP are laminated so that the bump electrode TBP is formed.
- the rear surface side of the first substrate Sa and the front surface side of the second substrate Sb explained in the second embodiment are bonded to each other so that the organic insulating films ( 501 and 500 b ) are in contact with each other as well as the bump electrodes (TBP and BPb) are in contact with each other.
- an opening portion TH 2 that is opened by dry-etching the laminated insulating film TC of the inorganic insulating film 401 and the organic insulating film 501 is arranged in the upper portion of the pad electrode 200 ( FIG. 32 ). Moreover, a surface treatment is performed on the organic insulating film 501 .
- the first substrate Sa having the formation layer 100 for the semiconductor element and the pad electrode 200 formed thereon is prepared.
- the uppermost layer wire including the pad electrode 200 is formed by burying a metal film (for example, a Cu film) in the wiring trench inside the inorganic insulating film 300 as similar to the second embodiment.
- the back grinding process is performed so that the thickness of the first substrate Sa is a predetermined thickness (for example, about 25 ⁇ m) when the rear surface of the first substrate Sa (which is the second surface, surface on the side opposite to the formation side of the semiconductor element) is set as the upper side.
- a predetermined thickness for example, about 25 ⁇ m
- the rear surface of the first substrate Sa which is the second surface, surface on the side opposite to the formation side of the semiconductor element
- an insulating film 301 is formed on the first substrate Sa including the inside of the opening portion TH.
- a silicon oxide film is formed by using the CVD method or others.
- the insulating film 301 is removed.
- a barrier metal film 601 , a seed film (not illustrated) and a Cu film 701 are formed on the insulating film 301 including the inside of the opening portion TH 1 as similar to the third embodiment.
- the Cu film 701 , the seed film and the barrier metal film 601 on the insulating film 301 are polished by using the CMP method.
- a first bump electrode 1 BP formed of the Cu film 701 , the seed film and the barrier metal film 601 is formed inside the opening portion TH 1 .
- the inorganic insulating film 401 for example, a silicon oxide film is deposited on the first bump electrode 1 BP and the insulating film 301 by using the CVD method or others so as to have a thickness of about 500 nm. Then, on the inorganic insulating film 401 , an organic insulating film 501 is formed.
- a PBO film is formed as the inorganic insulating film 501 as similar to the first embodiment.
- the organic insulating film 501 in the formation region of the opening portion TH 2 is removed.
- the inorganic insulating film 401 is dry-etched with using the organic insulating film 501 as a mask.
- the opening portion TH 2 that penetrates through the inorganic insulating film 401 and the organic insulating film 501 and reaches the first bump electrode 1 BP is formed.
- a surface treatment is performed on the surface of the organic insulating film 501 (which is the rear surface of the first substrate Sa).
- the surface treatment for example, gas containing hydrogen radicals is sprayed onto the surface of the organic insulating film 501 .
- the surface of the organic insulating film 501 is modified.
- a barrier metal film 602 for example, a TiN film is deposited on the organic insulating film 501 including the inside of the opening portion TH 2 by using the sputtering method or others. Then, a Cu film is deposited as a seed film (not illustrated) on the barrier metal film 602 by the sputtering method. Next, a Cu film 702 is deposited on the upper portion of the seed film by the electrolytic plating method.
- the Cu film 702 , the seed film and the barrier metal film 602 on the organic insulating film 501 are polished by using the CMP method.
- a second bump electrode 2 BP formed of the Cu film 702 , the seed film and the barrier metal film 602 is formed inside the opening portion TH 2 .
- the bump electrode TBP is formed so as to be connected to the pad electrode 200 , be formed by the laminated structure of the first bump electrode 1 BP and the second bump electrode 2 BP, and be exposed from the rear surface of the first substrate Sa (which is the second surface, surface on the side opposite to the formation side of the semiconductor element).
- the second substrate Sb as explained in the second embodiment is prepared, and the front surface of the second substrate Sb (which is the first surface, element surface, surface on the formation side of the bump electrode, surface on the formation side of the semiconductor element) and the rear surface of the first substrate Sa (which is the second surface, surface on the side opposite to the formation side of the semiconductor element) are faced and overlapped with each other as illustrated in FIG. 33 , and then, these substrates are thermally compressed and bonded.
- electrical connection between the bump electrodes (TBP, BPb) formed on the respective first substrate Sa and second substrate Sb and bonding between the organic insulating films ( 501 , 500 b ) thereon are simultaneously performed.
- the rear surface of the second substrate Sb is subjected to the back grinding process so as to be a thin film whose substrate thickness is about 25 ⁇ m.
- the first substrate Sa and the second substrate Sb in a wafer state are cut along scribe lines to be individual pieces.
- the surface treatment on the organic insulating film 501 is performed subsequent to the formation of the opening portion TH 2 but prior to the formation of the bump electrode TBP.
- the surface treatment on the organic insulating film 501 may be performed subsequent to the formation of the bump electrode TBP but prior to the thermal compression-bonding between the substrates.
- the laminated insulating film TC of the inorganic insulating film 401 and the organic insulating film 501 is formed on the rear surface of the first substrate Sa, and therefore, the degassing from the organic insulating film 501 can be reduced in the heating and compression-bonding processes for the first substrate Sa and the second substrate Sa. Therefore, the occurrence of voids at the time of the compression-bonding process can be suppressed, and the peeling between the substrates due to bonding failure between the substrates can be reduced. Moreover, the connection failure between the bump electrodes can be reduced. In this manner, the characteristics of the semiconductor device can be improved.
- the surface treatment is performed on the surface of the organic insulating film 501 prior to the thermal compression-bonding process between the substrates, and therefore, the adhesive property between the organic insulating films ( 501 , 500 b ) can be improved.
- the first bump electrode 1 BP of the bump electrode TBP having the laminated structure of the first bump electrode 1 BP and the second bump electrode 2 BP is formed prior to the formation of the pad electrode (conductive film) 200 .
- FIGS. 34 to 44 are cross-sectional views illustrating the manufacturing steps of the semiconductor device of the present embodiment.
- FIG. 43 that is one of the cross-sectional views illustrating the manufacturing steps of the semiconductor device of the present embodiment
- the rear surface of the first substrate Sa (which is the second surface, surface on the side opposite to the formation side of semiconductor elements) is illustrated as the upper side. Therefore, the formation layer 100 for the semiconductor element (which is the inner layer of the semiconductor element) formed in the front surface of the first substrate Sa (which is the first surface, element surface, surface on the formation side of the bump electrode, surface on the formation side of the semiconductor element) is positioned on the lower side of the first substrate Sa. Further below the formation layer 100 for the semiconductor element, the pad electrode (conductive film) 200 is arranged.
- a laminated insulating film TC of an inorganic insulating film 401 and an organic insulating film 501 is arranged on the rear surface of the first substrate Sa.
- an opening portion TH 2 is provided in a part of the laminated insulating film IC and the first substrate Sa.
- the side wall of this opening portion TH 2 is covered with an insulating film 302 , and besides, a second bump electrode 2 BP is arranged inside the opening portion TH 2 .
- an opening portion TH 1 is formed in the first substrate Sa and the formation layer 100 for the semiconductor element. Inside this opening portion TH 1 , a first bump electrode 1 BP is arranged inside this opening portion TH 1 .
- a bump electrode TBP is constituted by a laminate of these first bump electrode 1 BP and second bump electrode 2 BP.
- the rear surface side of the first substrate Sa and the front surface side of the second substrate Sb explained in the second embodiment are bonded to each other so that the organic insulating films ( 501 and 500 b ) are in contact with each other as well as the bump electrodes (TBP and BPb) are in contact with each other.
- an opening portion TH 2 that is opened by dry-etching the laminated insulating film TC of the inorganic insulating film 401 and the organic insulating film 501 or others is arranged in the upper portion of the pad electrode 200 ( FIG. 43 ). Moreover, a surface treatment is performed on the organic insulating film 501 .
- the first substrate Sa having the formation layer 100 for the semiconductor element formed thereon is prepared.
- an opening portion (concave portion) TH 1 is formed.
- the bottom portion of the opening portion TH 1 is located at a position having a distance D from the surface of the first substrate Sa.
- the opening portion TH 1 is formed by etching the formation layer 100 for the semiconductor element, and then, further etching the first substrate Sa to the depth of the distance D.
- an insulating film 301 is formed on the first substrate Sa including the inside of the opening portion TH 1 .
- a silicon oxide film is formed by the CVD method or others.
- the insulating film 301 on the first substrate Sa is removed.
- a TiN film is deposited as a barrier metal film 601 by using the sputtering method or others.
- a Cu film is deposited as a seed film (not illustrated) on the barrier metal film 601 by the sputtering method.
- a Cu film 701 is deposited on the upper portion of the seed film by the electrolytic plating method.
- the Cu film 701 , the seed film and the barrier metal film 601 on the formation layer 100 for the semiconductor element are polished by using the CMP method.
- a first bump electrode 1 BP formed of the Cu film 701 , the seed film and the barrier metal film 601 is formed inside the opening portion TH 1 .
- the formation region of the opening portion TH 1 is laid out in association with the formation region where the pad electrode 200 is to be formed, and is previously designed so that no semiconductor element is formed in this region.
- FIG. 37 illustrates one example thereof.
- an MISFET (Qn) is formed on the first substrate Sa.
- an interlayer insulating film IL 1 on the MISFET (Qn) is formed in an interlayer insulating film IL 1 on the MISFET (Qn).
- a plug P 1 is formed on the interlayer insulating film IL 1 .
- a wire M 1 buried in a wire-trench insulating film IL 2 a is formed on the interlayer insulating film IL 2 b is formed on the wire M 1
- a plug P 2 is formed in the interlayer insulating film IL 2 b .
- interlayer insulating film IL 2 b a wire M 2 buried in a wire-trench insulating film IL 3 a is formed.
- An interlayer insulating film IL 3 b is formed on the wire M 2 , and a plug P 3 is formed in the interlayer insulating film IL 3 b.
- a wire M 3 corresponding to the uppermost layer wire is formed on the interlayer insulating film IL 3 b .
- an opening portion TH 1 is formed by etching the formation layer 100 for the semiconductor element and the first substrate Sa ( FIG. 37 ). More specifically, the opening portion TH 1 is formed by etching a part of the interlayer insulating film IL 3 b , the wire-trench insulating film IL 3 a , the interlayer insulating film IL 2 b , the wire-trench insulating film IL 2 a , the interlayer insulating film IL 1 , the element isolation region 2 , and the first substrate Sa.
- an insulating film 301 is formed so as to cover the bottom portion and the side wall of the opening portion TH 1 .
- a first bump 1 BP formed of the Cu film 701 , the seed film and the barrier metal film 601 is formed inside the opening portion TH 1 , and the uppermost layer wire (wire M 3 in FIG. 38 ) is formed so that the pad electrode 200 is positioned on the first bump electrode 1 BP.
- a silicon oxide film is deposited on the upper portion of the first substrate Sa as the inorganic insulating film 300 by the CVD method or others.
- the inorganic insulating film 300 By patterning the inorganic insulating film 300 , a wire trench is formed, and a metal film (for example, Cu film) is buried therein, so that the uppermost layer wire (wire M 3 in FIG. 38 ) is formed. A part of the uppermost layer wire (wire M 3 in FIG. 38 ) becomes the pad electrode 200 .
- a metal film for example, Cu film
- the pad electrode 200 (uppermost layer wire) is formed subsequent to the formation of the opening portion TH 1 and the first bump electrode 1 BP.
- FIG. 39 illustrates the formation layer (inner layer of semiconductor element) as a reference numeral 100 so that the pad electrode 200 is on the first bump electrode 1 BP.
- a back grinding process is performed so that the thickness of the first substrate Sa is a predetermined thickness (for example, about 25 ⁇ m) when the rear surface of the first substrate Sa is set as the upper side.
- the amount of back grinding is adjusted so that the first substrate Sa remains on the first bump electrode 1 BP ( FIG. 40 ).
- a silicon oxide film is deposited on the first substrate Sa as an inorganic insulating film 401 by the CVD method or others so as to have a thickness of about 500 nm.
- an organic insulating film 501 is formed on the inorganic insulating film 401 .
- a PBO film is formed as similar to the first embodiment.
- the organic insulating film 501 in the formation region of the opening portion TH 2 is removed. Then, the inorganic insulating film. 401 , the first substrate Sa and the insulating film 301 are etched with using the organic insulating film 501 as a mask. Thus, the opening portion TH 2 , which reaches the first bump electrode 1 BP, is formed.
- a surface treatment is performed on the surface (rear surface of the first substrate Sa) of the organic insulating film 501 .
- the surface treatment for example, gas containing hydrogen radicals is sprayed onto the surface of the organic insulating film 501 .
- the surface of the organic insulating film 501 is modified.
- an insulating film 302 is formed on the organic insulating film 501 including the inside of the opening portion TH 2 .
- the insulating film 302 for example, a silicon oxide film is formed by using the CVD method or others. Then, by anisotropically etching the insulating film 302 , the insulating film 302 is left only on the side wall of the opening portion TH 2 .
- a barrier metal film 602 for example, a TiN film is deposited by using the sputtering method or others. Then, a Cu film is deposited on the barrier metal film 602 as a seed film (not illustrated) by the sputtering method. Next, a Cu film 702 is deposited on the upper portion of the seed film by the electrolytic plating method.
- the Cu film 702 , the seed film and the barrier metal film 602 on the organic insulating film 501 are polished by using the CMP method.
- a second bump electrode 2 BP formed of the Cu film 702 , the seed film and the barrier metal film 602 is formed inside each opening portion TH 2 .
- the bump electrode TBP is formed so as to be connected to the pad electrode 200 , to be formed of the laminated structure of the first bump electrode 1 BP and the second bump electrode 2 BP, and to be exposed from the rear surface of the first substrate Sa (which is the second surface, surface on the side opposite to the formation side of the semiconductor element).
- the second substrate Sb as explained in the second embodiment is prepared, and as illustrated in FIG. 44 , the front surface of the second substrate Sb (which is the first surface, element surface, surface on the formation side of the bump electrode, surface on the formation side of the semiconductor element) and the rear surface of the first substrate Sa (which is second surface, surface on the side opposite to the formation side of the semiconductor element) are faced and overlapped with each other, and these substrates are thermally compressed and bonded.
- electrical connection between the bump electrodes (TBP, BPb) formed on the respective first substrate Sa and second substrate Sb and bonding between the organic insulating films ( 501 , 500 b ) thereon are simultaneously performed.
- the rear surface of the second substrate Sb is subjected to a back grinding process so as to be a thin film whose substrate thickness is about 25 ⁇ m.
- the first substrate Sa and the second substrate Sb in a wafer state are cut along scribe lines to be individual pieces.
- the surface treatment on the organic insulating film 501 is performed subsequent to the formation of the opening portion TH 2 but prior to the formation of the second bump electrode 2 BP.
- the surface treatment on the organic insulating film 501 may be performed subsequent to the formation of the second bump electrode 2 BP but prior to the thermal compression-bonding between the substrates.
- the laminated insulating film TC of the inorganic insulating film 401 and the organic insulating film 501 is formed on the rear surface of the first substrate Sa, and therefore, the degassing from the organic insulating film 501 can be reduced in the heating and compression-bonding processes for the first substrate Sa and the second substrate Sa. Therefore, the occurrence of voids at the time of the compression-bonding process can be suppressed, the peeling between the substrates due to bonding failure between the substrates can be reduced. Moreover, the connection failure between the bump electrodes can be reduced. In this manner, the characteristics of the semiconductor device can be improved.
- the surface treatment is performed on the surface of the organic insulating film 501 prior to the thermal compression-bonding between the substrates, and therefore, the adhesive property of the organic insulating film 501 can be improved.
- FIGS. 45 to 47 are cross-sectional views illustrating the manufacturing steps of the semiconductor device of a sixth embodiment.
- FIG. 47 that is one of the cross-sectional views illustrating the manufacturing steps of the semiconductor device of the present embodiment
- the rear surface of the first substrate Sa (which is the second surface, surface on the side opposite to the formation side of the semiconductor element) is illustrated as the upper side. Therefore, the formation layer 100 for the semiconductor element (which is the inner layer of the semiconductor element) formed on the front surface of the first substrate Sa (which is the first surface, element surface, surface on the formation side of the bump electrode, surface on the formation side of the semiconductor element) is positioned on the lower side of the first substrate Sa. Further below the formation layer 100 for the semiconductor element, the pad electrode (conductive film) 200 is arranged.
- a laminated insulating film TC of an inorganic insulating film 401 and an organic insulating film 501 is arranged on the rear surface of the first substrate Sa.
- An opening portion TH 2 is formed in the laminated insulating film IC, and a second bump electrode 2 BP is arranged inside the opening portion TH 2 .
- an opening portion TH 1 that reaches the pad electrode 200 is formed inside the opening portion TH 1 .
- a bump electrode TBP is formed by a laminate of the first bump electrode 1 BP and second bump electrode 2 BP.
- the opening portion TH 2 which is opened by dry-etching the laminated insulating film TC of the inorganic insulating film 401 and the organic insulating film 501 or others, is formed on the upper portion of the pad electrode 200 ( FIG. 47 ). Moreover, a surface treatment is performed on the organic insulating film 501 .
- the opening portion (concave portion) TH 1 , the insulating film 301 and the first bump electrode 1 BP are formed, and an uppermost layer wire (pad electrode 200 ) is further formed thereon (see FIG. 39 ).
- the thickness of the first substrate Sa is a predetermined thickness (for example, about 25 ⁇ m) when the rear surface of the first substrate Sa is set as the upper side.
- the first substrate Sa is subjected to the back grinding process until the insulating film 301 on the first bump electrode 1 BP is exposed ( FIG. 45 ).
- a silicon oxide film is deposited on the first substrate Sa and the first bump electrode 1 BP (insulating film 301 ) as an inorganic insulating film 401 by the CVD method or others.
- an organic insulating film 501 is formed on the inorganic insulating film 401 .
- a PBO film is formed as similar to the first embodiment. Note that the insulating film 301 may be removed by the back grinding process so that the first bump electrode 1 BP is exposed.
- the organic insulating film 501 in the formation region of the opening portion TH 2 is removed. Then, the inorganic insulating film 401 and the insulating film 301 are etched with using the organic insulating film 501 as a mask. Thus, the opening portion TH 2 , which reaches the first bump electrode 1 BP, is formed.
- a surface treatment is performed on the surface (rear surface of the first substrate Sa) of the organic insulating film 501 .
- the surface treatment for example, gas containing hydrogen radicals is sprayed onto the surface of the organic insulating film 501 .
- the surface of the organic insulating film 501 is modified.
- a barrier metal film 602 for example, a TiN film is deposited on the organic insulating film 501 including the inside of the opening portion TH 2 by using the sputtering method or others. Then, a Cu film is deposited on the barrier metal film 602 as a seed film (not illustrated) by the sputtering method. Next, a Cu film 702 is deposited on the upper portion of the seed film by the electrolytic plating method.
- the Cu film 702 , the seed film and the barrier metal film 602 on the organic insulating film 501 are polished by using the CMP method.
- a second bump electrode 2 BP formed of the Cu film 702 , the seed film and the barrier metal film 602 is formed inside each opening portion TH 2 .
- the bump electrode TBP is formed so as to be connected to the pad electrode 200 , to be formed by a laminated structure of the first bump electrode 1 BP and the second bump electrode 2 BP, and to be exposed from the rear surface of the first substrate Sa (which is the second surface, surface on the side opposite to the formation side of the semiconductor element).
- the second substrate Sb as explained in the second embodiment is prepared, and the front surface of the second substrate Sb (first surface, element surface, surface on the formation side of the bump electrode, surface on the formation side of the semiconductor element) and the rear surface of the first substrate Sa (second surface, surface on the side opposite to the formation side of the semiconductor element) are faced and overlapped with each other, and after having been overlapped with each other as similar to the fifth embodiment, and these substrates are thermally compressed and bonded (see FIG. 44 ).
- electrical connection between the bump electrodes (TBP, BPb) formed on the respective first substrate Sa and second substrate Sb and bonding between the organic insulating films ( 501 , 500 b ) are simultaneously performed.
- the rear surface of the second substrate Sb is subjected to a back grinding process so as to be a thin film whose substrate thickness is about 25 ⁇ m.
- the first substrate Sa and the second substrate Sb in a wafer state are cut along scribe lines to be individual pieces.
- the surface treatment on the organic insulating film 501 is performed subsequent to the formation of the opening portion TH 2 but prior to the formation of the second bump electrode 2 BP.
- the surface treatment on the organic insulating film 501 may be performed subsequent to the formation of the second bump electrode 2 BP but prior to the thermal compression-bonding between the substrates.
- the laminated insulating film TC of the inorganic insulating film 401 and the organic insulating film 501 is formed on the rear surface of the first substrate Sa, and therefore, the degassing from the organic insulating film 501 can be reduced in the heating and compression-bonding processes for the first substrate Sa and the second substrate Sa. Therefore, the occurrence of voids at the time of the compression-bonding process can be suppressed, and the peeling between the substrates due to bonding failure between the substrates can be reduced. Moreover, the connection failure between the bump electrodes can be reduced. In this manner, the characteristics of the semiconductor device can be improved.
- the surface treatment is performed on the surface of the organic insulating film 501 prior to the thermal compression-bonding between the substrates, and therefore, the adhesive property of the organic insulating film 501 can be improved.
- FIGS. 48 to 50 are cross-sectional views illustrating the manufacturing steps of the semiconductor device of the seventh embodiment.
- FIG. 50 that is one of the cross-sectional views illustrating the manufacturing steps of the semiconductor device of the present embodiment
- the rear surface of the first substrate Sa (second surface, surface on the side opposite to the formation side of the semiconductor element) is illustrated as the upper side. Therefore, the formation layer 100 for the semiconductor element (which is the inner layer of the semiconductor element) formed on the front surface of the first substrate Sa (which is the first surface, element surface, surface on the formation side of the bump electrode, surface on the formation side of the semiconductor element) is positioned on the lower side of the first substrate Sa. Further below the formation layer 100 for the semiconductor element, the pad electrode (conductive film) 200 is arranged.
- a laminated insulating film TC of an inorganic insulating film 401 and an organic insulating film. 501 is arranged on the rear surface of the first substrate Sa.
- An opening portion TH 2 is formed in the laminated insulating film TC, and a second bump electrode 2 BP is arranged inside the opening portion TH 2 .
- an opening portion TH 1 that reaches the pad electrode 200 is formed inside the opening portion TH 1 .
- a first bump electrode 1 BP is arranged inside the opening portion TH 1 .
- the surface of the first bump electrode 1 BP protrudes from the rear surface of the first substrate Sa (which is an upper surface in FIG. 50 ).
- a bump electrode TBP is formed by a laminate of the first bump electrode 1 BP and second bump electrode 2 BP.
- the opening portion TH 2 which is opened by dry-etching the laminated insulating film TC of the inorganic insulating film 401 and the organic insulating film 501 or others, is arranged on the upper portion of the pad electrode 200 ( FIG. 50 ). Moreover, a surface treatment is performed on the organic insulating film 501 .
- the opening portion (concave portion) TH 1 , the insulating film 301 and the first bump electrode 1 BP are formed, and the uppermost layer wire (pad electrode 200 ) is further formed thereon (see FIG. 39 ).
- a back grinding process is performed so that the thickness of the first substrate Sa is a predetermined thickness (for example, about 25 ⁇ m) when the rear surface of the first substrate Sa is set as the upper side.
- the first substrate Sa is subjected to the back grinding process until the insulating film 301 on the first bump electrode 1 BP is exposed, and is further subjected to the over grinding process.
- the grinding (polishing) step by performing the grinding process under such a condition that a chemically-polished component is superior, the first substrate Sa can be recessed relative to the first bump electrode 1 BP (insulating film 301 ). Note that the insulating film 301 may be removed by the back grinding process so that the first bump electrode 1 BP is exposed.
- a silicon oxide film is deposited on the first substrate Sa as an inorganic insulating film 401 by the CVD method or others.
- an organic insulating film. 501 is formed on the inorganic insulating film. 401 .
- a PBO film is formed as similar to the first embodiment.
- the organic insulating film 501 in the formation region of the opening portion TH 2 is removed. Then, the inorganic insulating film 401 and the insulating film 301 are etched with using the organic insulating film 501 as a mask. Thus, the opening portion TH 2 , which reaches the first bump electrode 1 BP, is formed.
- a surface treatment is performed on the surface of the organic insulating film. 501 (which is the rear surface of the first substrate Sa).
- the surface treatment for example, gas containing hydrogen radicals is sprayed onto the surface of the organic insulating film 501 .
- the surface of the organic insulating film 501 is modified.
- a barrier metal film 602 for example, a TiN film is deposited on the organic insulating film 501 including the inside of the opening portion TH 2 by using the sputtering method or others. Then, a Cu film is deposited on the barrier metal film 602 as a seed film (not illustrated) by the sputtering method. Next, a Cu film 702 is deposited on the upper portion of the seed film by the electrolytic plating method.
- the Cu film 702 , the seed film and the barrier metal film 602 on the organic insulating film 501 are polished by using the CMP method.
- a second bump electrode 2 BP formed of the Cu film 702 , the seed film and the barrier metal film 602 is formed inside the opening portion TH 2 .
- the bump electrode TBP is formed so as to be connected to the pad electrode 200 , to be formed of a laminated structure of the first bump electrode 1 BP and the second bump electrode 2 BP, and to be exposed from the rear surface of the first substrate Sa (second surface, surface on the side opposite to the formation side of the semiconductor element).
- the second substrate Sb as explained in a second embodiment is prepared, and the front surface of the second substrate Sb (which is the first surface, element surface, surface on the formation side of the bump electrode, surface on the formation side of the semiconductor element) and the rear surface of the first substrate Sa (which is the second surface, surface on the side opposite to the formation side of the semiconductor element) are faced and overlapped with each other as similar to the fifth embodiment, and then, these substrates are thermally compressed and bonded (see FIG. 44 ).
- electrical connection between the bump electrodes (TBP, BPb) formed on the respective first substrate Sa and second substrate Sb and bonding between the organic insulating films ( 501 , 500 b ) are simultaneously performed.
- the rear surface of the second substrate Sb is subjected to a back grinding process so as to be a thin film whose substrate thickness is about 25 ⁇ m.
- the first substrate Sa and the second substrate Sb in a wafer state are cut along scribe lines to be individual pieces.
- the surface treatment on the organic insulating film 501 is performed subsequent to the formation of the opening portion TH 2 but prior to the formation of the second bump electrode 2 BP.
- the surface treatment on the organic insulating film 501 may be performed subsequent to the formation of the second bump electrode 2 BP prior to the thermal compression-bonding between the substrates.
- the laminated insulating film TC of the inorganic insulating film 401 and the organic insulating film 501 is formed on the rear surface of the first substrate Sa, and therefore, the degassing from the organic insulating film 501 can be reduced in the heating and compression-bonding processes for the first substrate Sa and the second substrate Sa. Therefore, the occurrence of voids at the time of the compression-bonding process can be suppressed, and the peeling between the substrates due to bonding failure between the substrates can be reduced. Moreover, the connection failure between the bump electrodes can be reduced. In this manner, the characteristics of the semiconductor device can be improved.
- the surface treatment is performed on the surface of the organic insulating film. 501 prior to the thermal compression-bonding between the substrates, and therefore, the adhesive property of the organic insulating film. 501 can be improved.
- the thermal compression-bonding process has been performed so as to bond the bump electrodes (BP, BPb) on the front surface of the second substrate Sb and the rear surface of the first substrate Sa to each other.
- substrates each having the same structure as that of the first substrate Sa may be prepared, and the rear surfaces of these substrates may be thermally compressed and bonded to each other.
- the second substrate Sa the second substrate Sb of the second embodiment has been exemplified.
- the second substrate Sb of the first embodiment may be used.
- the substrates (Sa, Sb) described in the first to seventh embodiments may be combined with each other, and the thermal compression-bonding process may be performed so as to bond the bump electrodes to each other.
- the constituent metal of the other bump electrode may be made different, and besides, the other organic insulating film may be prepared as another insulating film (for example, inorganic insulating film).
- the thermal compression-bonding may be performed after the first substrate Sa and the second substrate Sb in a wafer state are formed into individual pieces.
- the present invention relates to a semiconductor device and a method of manufacturing the semiconductor. More particularly, the present invention is effectively applied to a semiconductor device (three-dimensional IC) in which a plurality of semiconductor substrates are electrically connected to each other via an electrode.
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US9153495B2 (en) | 2015-10-06 |
JP2013229415A (ja) | 2013-11-07 |
TW201403775A (zh) | 2014-01-16 |
US20150187651A1 (en) | 2015-07-02 |
JP6014354B2 (ja) | 2016-10-25 |
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