US20100258878A1 - Cmos semiconductor device and method for manufacturing the same - Google Patents

Cmos semiconductor device and method for manufacturing the same Download PDF

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US20100258878A1
US20100258878A1 US12/745,638 US74563808A US2010258878A1 US 20100258878 A1 US20100258878 A1 US 20100258878A1 US 74563808 A US74563808 A US 74563808A US 2010258878 A1 US2010258878 A1 US 2010258878A1
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layer
type mosfet
metal
formation region
insulation layer
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Nobuyuki Mise
Takahisa Eimori
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Renesas Electronics Corp
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Renesas Electronics Corp
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H01L29/4975—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 being a silicide layer, e.g. TiSi2
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present invention relates to a CMOS semiconductor device and a method for producing the same, and more particularly to a CMOS semiconductor device using a high-k material for a gate electrode and a method for producing the same.
  • CMOS semiconductor device As a CMOS semiconductor device is miniaturized, what is troubling is that a gate insulation layer composed of SiON or SiO 2 becomes thin and a leak current goes through the gate insulation layer due to a tunneling phenomenon.
  • a high-k material such as hafnium is used for the gate insulation layer and a thickness of the gate insulation layer is set to a constant value to prevent the leak current from being generated.
  • high-k material such as hafnium
  • a thickness of the gate insulation layer is set to a constant value to prevent the leak current from being generated.
  • a metal such as nickel silicide is used instead of polycrystalline silicon.
  • NiSi is used for a metal gate electrode of a p-channel MOSFET
  • Ni 2 Si is used for a metal gate electrode of an n-channel MOSFET.
  • Patent document 1 Japanese Unexamined Patent Publication No. 2002-359295
  • CMOS semiconductor device it is necessary to control a gate length Lg with a high degree of accuracy to control threshold voltages of the p-channel MOSFET and the n-channel MOSFET.
  • the gate length Lg is 20 nm, for example, allowable LWR (Line Width Roughness) of the gate length is about 5%, which means about 1 nm.
  • the gate electrodes composed of different materials such as NiSi and Ni 2 Si cannot be processed with a high degree of accuracy in the same etching step, that is, in one etching step using one kind of etching gas, so that a side wall of the electrode is tapered in general.
  • CMOS semiconductor device capable of controlling a gate length with a high degree of accuracy in the CMOS semiconductor device using a high-k material, and a production method for producing the same.
  • the present invention is a CMOS semiconductor device having an n-type MOSFET and a p-type MOSFET, comprising: a gate electrode of the n-type MOSFET having a first insulation layer composed of a high-k material, and a first metal layer provided on the first insulation layer and composed of a metal material; and a gate electrode of the p-type MOSFET having a second insulation layer composed of a high-k material, and a second metal layer provided on the second insulation layer and composed of a metal material, wherein the first insulation layer and the second insulation layer are composed of the different high-k materials, and the first metal layer and the second metal layer are composed of the same metal material.
  • the present invention is a method for producing a CMOS semiconductor device having an n-type MOSFET and a p-type MOSFET, comprising the steps of: preparing a semiconductor substrate defined by an n-type MOSFET formation region and a p-type MOSFET formation region; forming a high-k material layer, a first cap layer, and a first metal layer, sequentially on the semiconductor substrate; removing the first cap layer and the first metal layer except for those in the p-type MOSFET formation region; forming a second cap layer and a second metal layer, sequentially on the semiconductor substrate; removing the second metal layer except for that in the n-type MOSFET formation region; removing the second cap layer provided between the n-type MOSFET formation region and the p-type MOSFET formation region, using the first metal layer and the second metal layer as masks; removing the first metal layer and the second metal layer; forming a gate metal material layer on the semiconductor substrate; and forming a gate metal layer of a gate electrode
  • the CMOS semiconductor device can control a threshold voltage with a high degree of accuracy.
  • the gate metal layer of the gate electrode each of the n-type MOSFET and the p-type MOSFET can be formed in the same etching step, the gate electrode can be processed with a high degree of accuracy.
  • FIG. 1 is a cross-sectional view of a CMOS semiconductor device according to a first embodiment.
  • FIG. 1A is a cross-sectional view of a production step of the CMOS semiconductor device according to the first embodiment.
  • FIG. 1B is a cross-sectional view of a production step of the CMOS semiconductor device according to the first embodiment.
  • FIG. 1C is a cross-sectional view of a production step of the CMOS semiconductor device according to the first embodiment.
  • FIG. 1D is a cross-sectional view of a production step of the CMOS semiconductor device according to the first embodiment.
  • FIG. 1E is a cross-sectional view of a production step of the CMOS semiconductor device according to the first embodiment.
  • FIG. 1F is a cross-sectional view of a production step of the CMOS semiconductor device according to the first embodiment.
  • FIG. 1G is a cross-sectional view of a production step of the CMOS semiconductor device according to the first embodiment.
  • FIG. 1H is a cross-sectional view of a production step of the CMOS semiconductor device according to the first embodiment.
  • FIG. 1I is a cross-sectional view of a production step of the CMOS semiconductor device according to the first embodiment.
  • FIG. 1J is a cross-sectional view of a production step of the CMOS semiconductor device according to the first embodiment.
  • FIG. 1K is a cross-sectional view of a production step of the CMOS semiconductor device according to the first embodiment.
  • FIG. 2A is a cross-sectional view of a production step of a CMOS semiconductor device according to a second embodiment.
  • FIG. 2B is a cross-sectional view of a production step of the CMOS semiconductor device according to the second embodiment.
  • FIG. 2C is a cross-sectional view of a production step of the CMOS semiconductor device according to the second embodiment.
  • FIG. 3A is a cross-sectional view of a production step of a CMOS semiconductor device according to a third embodiment.
  • FIG. 3B is a cross-sectional view of a production step of the CMOS semiconductor device according to the third embodiment.
  • FIG. 3C is a cross-sectional view of a production step of the CMOS semiconductor device according to the third embodiment.
  • FIG. 3D is a cross-sectional view of a production step of the CMOS semiconductor device according to the third embodiment.
  • FIG. 3E is a cross-sectional view of a production step of the CMOS semiconductor device according to the third embodiment.
  • FIG. 3F is a cross-sectional view of a production step of the CMOS semiconductor device according to the third embodiment.
  • FIG. 3G is a cross-sectional view of a production step of the CMOS semiconductor device according to the third embodiment.
  • FIG. 3H is a cross-sectional view of a production step of the CMOS semiconductor device according to the third embodiment.
  • FIG. 4A is a cross-sectional view of a production step of a CMOS semiconductor device according to a fourth embodiment.
  • FIG. 4B is a cross-sectional view of a production step of the CMOS semiconductor device according to the fourth embodiment.
  • FIG. 4C is a cross-sectional view of a production step of the CMOS semiconductor device according to the fourth embodiment.
  • FIG. 4D is a cross-sectional view of a production step of the CMOS semiconductor device according to the fourth embodiment.
  • FIG. 4E is a cross-sectional view of a production step of the CMOS semiconductor device according to the fourth embodiment.
  • FIG. 4F is a cross-sectional view of a production step of the CMOS semiconductor device according to the fourth embodiment.
  • FIG. 4G is a cross-sectional view of a production step of the CMOS semiconductor device according to the fourth embodiment.
  • FIG. 4H is a cross-sectional view of a production step of the CMOS semiconductor device according to the fourth embodiment.
  • FIG. 5A is a cross-sectional view of a production step of another CMOS semiconductor device according to the fourth embodiment.
  • FIG. 5B is a cross-sectional view of a production step of another CMOS semiconductor device according to the fourth embodiment.
  • FIG. 5C is a cross-sectional view of a production step another CMOS semiconductor device according to the fourth embodiment.
  • FIG. 6A is a cross-sectional view of a production step of a CMOS semiconductor device according to a fifth embodiment.
  • FIG. 6B is a cross-sectional view of a production step of the CMOS semiconductor device according to the fifth embodiment.
  • FIG. 6C is a cross-sectional view of a production step of the CMOS semiconductor device according to the fifth embodiment.
  • FIG. 6D is a cross-sectional view of a production step of the CMOS semiconductor device according to the fifth embodiment.
  • FIG. 6E is a cross-sectional view of a production step of the CMOS semiconductor device according to the fifth embodiment.
  • FIG. 6F is a cross-sectional view of a production step of the CMOS semiconductor device according to the fifth embodiment.
  • FIG. 6G is a cross-sectional view of a production step of the CMOS semiconductor device according to the fifth embodiment.
  • FIG. 6H is a cross-sectional view of a production step of the CMOS semiconductor device according to the fifth embodiment.
  • FIG. 7A is a cross-sectional view of a production step of a CMOS semiconductor device according to a sixth embodiment.
  • FIG. 7B is a cross-sectional view of a production step of the CMOS semiconductor device according to the sixth embodiment.
  • FIG. 7C is a cross-sectional view of a production step of the CMOS semiconductor device according to the sixth embodiment.
  • FIG. 7D is a cross-sectional view of a production step of the CMOS semiconductor device according to the sixth embodiment.
  • FIG. 7E is a cross-sectional view of a production step of the CMOS semiconductor device according to the sixth embodiment.
  • FIG. 7F is a cross-sectional view of a production step of the CMOS semiconductor device according to the sixth embodiment.
  • FIG. 8 is a structural drawing of gate electrodes of a CMOS semiconductor device according to a seventh embodiment.
  • FIG. 9 is a structural drawing of gate electrodes of the CMOS semiconductor device described in the first to sixth embodiments.
  • FIG. 10A is a schematic view of a production step of a CMOS semiconductor device according to an eighth embodiment.
  • FIG. 10B is a schematic view of a production step of the CMOS semiconductor device according to the eighth embodiment.
  • FIG. 11 is a structural drawing of gate electrodes of a CMOS semiconductor device according to a ninth embodiment.
  • FIG. 1 is a cross-sectional view of a CMOS semiconductor device (complementary metal oxide semiconductor device) represented by 100 as a whole according to a first embodiment.
  • CMOS semiconductor device complementary metal oxide semiconductor device
  • the CMOS semiconductor device 100 includes an n-type MOSFET 101 and a p-type MOSFET 102 .
  • the CMOS semiconductor device 100 includes a semiconductor substrate 105 composed of silicon, for example.
  • An n-type well region 110 and a p-type well region 120 are provided in the semiconductor substrate 100 .
  • the n-type well region 110 and the p-type well region 120 are insulated by an interlayer insulation layer 130 composed of silicon oxide, for example.
  • Source/drain regions 111 are provided in the n-type well region 110 .
  • a gate electrode 10 is provided on a channel region sandwiched between the source/drain regions 111 .
  • the gate electrode 10 includes a gate insulation layer 11 , a cap layer 12 , and gate metal layers 13 and 14 provided thereon.
  • the gate insulation layer 11 is composed of a high-k material such as HfLaO or HfMgO
  • the cap layer 12 is composed of MgO or LaO, for example.
  • the gate metal layer 13 is composed of a mid-gap material having high heat resistance such as TiN, TaN, TaSiN, NiSi, PtSi, or CoSi 2
  • the gate metal layer 14 is made of a low resistance material such as W.
  • source/drain regions 121 are provided in the p-type well region 120 .
  • a gate electrode 20 is provided on a channel region sandwiched between the source/drain regions 121 .
  • the gate electrode 20 includes a gate insulation layer 21 , a cap layer 22 , and gate metal layers 23 and 24 provided thereon.
  • the gate insulation layer 21 is composed of a high-k material such as HfAlO
  • the cap layer 22 is composed of AlO, for example.
  • the gate metal layers 23 and 24 are composed of the same materials as those of the gate metal layers 13 and 14 of the n-type MOSFET 101 , respectively.
  • the gate electrode can be processed with a high degree of accuracy, and a threshold voltage can be easily and correctly controlled in the CMOS semiconductor device 100 .
  • the LWR of a gate length Lg can be 5% or less.
  • CMOS semiconductor device 100 Specific structures of the gates of the CMOS semiconductor device 100 are as follows, for example.
  • n-type MOSFET W/TiN/MgO (or LaO)/HfSiON/Si substrate
  • FIGS. 1A to 1K A method for producing the CMOS semiconductor device 100 according to the first embodiment will be described with reference to FIGS. 1A to 1K .
  • the same reference as that in FIG. 1 represents the same or corresponding part in the drawings.
  • the production method includes the following step 1 to step 9.
  • Step 1 As shown in FIG. 1A , the semiconductor substrate 105 composed of silicon is prepared. As described in FIG. 1A , the n-type MOSFET 101 is formed on the left side, and the p-type MOSFET 102 is formed on the right side. In addition, the semiconductor substrate 105 is omitted after FIG. 1B .
  • a silicon oxide film (not shown) having a film thickness of 1 nm or less is formed on the semiconductor substrate 105 , and then an insulation layer 1 is formed thereon.
  • the insulation layer 1 is composed of a high-k (high-dielectric) material such as HfSiON.
  • the insulation layer 1 is formed by an ALD method, a MOCVD method, a sputtering method, or the like. According to need, a nitriding treatment or a heat treatment may be performed in the middle of or after this process.
  • the cap layer 22 composed of Al 2 O 3 is formed on the insulation layer 1 .
  • the cap layer 22 is about 1 nm in thickness, and made by the ALD method, the MOCVD method, the sputtering method, or the like. According to need, a heat treatment may be performed.
  • a first TiN layer 31 is formed to be about 10 nm in thickness on the cap layer 22 , and then a SiN layer 33 is formed to be about 10 nm in thickness. These are formed by the sputtering method, a CVD method, or the like.
  • Step 2 As shown in FIG. 1B , the SiN layer 33 in an n-MOSFET formation region is removed by dry etching using a photoresist (not shown) as an etching mask, for example. Then, the photoresist mask is removed, and the first TiN layer 31 and the cap layer 22 are removed by wet etching with H 2 O 2 , using the SiN layer 33 as an etching mask. The insulation layer 1 is hardly damaged through the above steps.
  • the cap layer 12 composed of MgO or LaO is formed by the ALD method, the MOCVD method or the sputtering method, for example.
  • the film thickness of the cap layer 12 is about 1 nm, but this is not necessarily the same as that of the cap layer 22 in a p-MOSFET formation region.
  • a Hf layer may be further formed on the cap layers 12 and 22 .
  • the gate insulation layer has a structure of HfO/MgO/HfSiON in the n-type MOSFET, and the gate insulation layer has a structure of HfO/AlO/HfSiON in the p-type MOSFET.
  • Step 3 As shown in FIG. 1C , a second TiN layer 32 is formed to be about 10 nm in thickness by the sputtering method or the CVD method, for example.
  • first and second TiN layers 31 and 32 are needed in the production steps, they do not remain in a final product. Therefore, they are preferably formed of the material which can be easily formed, high in selectivity, and easily removed.
  • polycrystalline Si may be used instead of TiN.
  • Step 4 As shown in FIG. 1D , a SiN layer 34 is formed to be about 10 nm in thickness by the sputtering method or the CVD method, for example. Then, a resist mask 36 is formed in the n-MOSFET formation region.
  • Step 5 As shown in FIG. 1E , the SiN layer 34 is selectively etched using the resist mask 36 as an etching mask. The etching stops on the second TiN layer 32 .
  • Step 6 As shown in FIG. 1F , the resist mask 36 is selectively removed by plasma ashing or the like.
  • Step 7 As shown in FIG. 1G , the second TiN layer 32 is selectively removed using the SiN layer 34 as an etching mask.
  • Step 8 As shown in FIG. 1H , the SiN layers 33 and 34 and the exposed cap layer 12 are removed by wet etching.
  • Step 9 As shown in FIG. 1I , the first and second TiN layers 31 and 32 are selectively removed by wet etching with H 2 O 2 , for example.
  • Step 10 As shown in FIG. 1J , a TaN layer 3 composed of a mid-gap material having high heat resistance is formed to be 30 nm or less in thickness by a sputtering method, for example.
  • a sputtering method for example.
  • TiN may be used instead of TaN.
  • a low-resistance tungsten layer 4 is formed on the TaN layer 3 by a sputtering method, for example. Its film thickness is 50 nm, for example.
  • Step 11 Finally, as shown in FIG. 1K , the tungsten layer 4 , the TiN layer 3 , the cap layers 12 and 22 , and the insulation layer 1 are etched using a hard mask (not shown) composed of SiN as an etching mask, whereby the gate electrode 10 of the n-type MOSFET and the gate electrode 20 of the p-type MOSFET are formed.
  • a hard mask (not shown) composed of SiN as an etching mask
  • the CMOS semiconductor device 100 is formed as shown in FIG. 1K .
  • the well region, the interlayer insulation layer, and the source/drain regions are formed by the same production steps as those of the conventional CMOS semiconductor device.
  • the metal layers (the tungsten layer 4 and the TaN layer in this case) of the gate electrodes of the n-MOSFET and the p-MOSFET are made of the same material, in the steps of producing the CMOS semiconductor device 100 according to this embodiment, they can be etched in the same etching step (step 11 in this case). Therefore, a fine gate electrode having a gate length which is as small as 20 nm, for example, can be etched with a high degree of accuracy.
  • the gate metal layers for the n-type MOSFET and the p-type MOSFET are made of the same material, the controllability can be improved as compared with the case where different materials are etched at the same time.
  • the material of the gate metal layer is different from each other, its etched shape differs from each other, and the selectivity with the lower insulation layer (high-k material) becomes low.
  • the etched shape is different, a gate length and a channel length are different between the n-type MOSFET and the p-type MOSFET.
  • the semiconductor substrate 1 is also etched.
  • the metal used to form the gate electrode finally is directly formed on the high-k material (insulation layer) such as HfSiON, a part of an element isolation region made of STI or the like is not etched by the etching step. Thus, preferable element isolation characteristic can be obtained.
  • FIGS. 2A to 2C A method for producing a CMOS semiconductor device according to a second embodiment is shown in FIGS. 2A to 2C .
  • FIG. 2A a structure shown in FIG. 2A is provided through the same steps as those shown in FIGS. 1A to 1F .
  • the second TiN layer 32 and the cap layer 12 are etched by selective etching using the SiN layer 34 as an etching mask.
  • the tungsten layer 4 is formed on the whole surface by the CVD method or the sputtering method, for example.
  • the tungsten layer 4 , and the TiN layers 31 and 33 are etched using a hard mask (not shown) composed of SiN, for example, as an etching mask, whereby gate electrodes of the n-type MOSFET and the p-type MOSFET are formed.
  • a hard mask (not shown) composed of SiN, for example, as an etching mask
  • CMOS semiconductor device 150 is formed as shown in FIG. 2C .
  • FIGS. 3A to 3H show a method for producing a CMOS semiconductor device according to a third embodiment.
  • the production method includes the following steps 1 to 8. According to this production method, the SiN layers 33 and 34 formed in the production method shown in FIGS. 1A to 1K in the first embodiment are not formed.
  • the same references as those in FIGS. 1A to 1K show the same or corresponding parts.
  • Step 1 As shown in FIG. 3A , the insulation layer 1 composed of HfSiON, for example, and the cap layers 12 and 22 , and TiN layers 31 and 32 are formed on the semiconductor substrate 105 (omitted after FIG. 3B ). These layers are made by roughly the same steps as those in FIGS. 1A to 1C except for the step of forming the SiN layer 33 .
  • Step 2 As shown in FIG. 3B , the photoresist mask 36 is formed in the n-MOSFET formation region.
  • Step 3 As shown in FIG. 3C , the TiN layer 32 is selectively removed by wet etching with H 2 O 2 , for example, using the resist mask 36 as an etching mask.
  • Step 4 As shown in FIG. 3D , the resist mask 36 is removed by an ashing method. In this step, a surface of the cap layer 12 is exposed to an ashing environment.
  • Step 5 As shown in FIG. 3E , the cap layer 12 on the insulation layer 1 is removed by wet etching using the TiN layers 31 and 32 as etching masks.
  • Step 6 As shown in FIG. 3F , the TiN layers 31 and 32 are selectively removed.
  • Step 7 As shown in FIG. 3G , the TaN layer 3 is formed to be 30 nm or less in thickness by a sputtering method, for example.
  • TiN may be used instead of TaN.
  • the low-resistance tungsten layer 4 is formed on the TaN layer 3 by a sputtering method, for example. Its film thickness is 50 nm, for example.
  • Step 8 Finally, as shown in FIG. 3H , the tungsten layer 4 , the TaN layer 3 , and the cap layers 12 and 22 are etched using a hard mask (not shown) composed of SiN, for example, as an etching mask, whereby the gate electrode 10 of the n-type MOSFET and the gate electrode 20 of the p-type MOSFET are formed.
  • a hard mask (not shown) composed of SiN, for example, as an etching mask
  • the production steps can be simplified. Meanwhile, the surface of the cap layer 12 is exposed to the ashing environment in step 4 ( FIG. 3D ). Therefore, the production method is preferably used in a case where the ashing step does not affect the device characteristics.
  • FIGS. 4A to 4H show a method for producing a CMOS semiconductor device according to a fourth embodiment.
  • the production method includes the following steps 1 to 8.
  • the same references as those in FIGS. 1A to 1 K show the same or corresponding parts.
  • Step 1 As shown in FIG. 4A , the insulation layer 1 composed of HfSiON is formed on a semiconductor substrate (not shown) and then an amorphous silicon layer 40 is formed by the CVD method or the like thereon.
  • Step 2 As shown in FIG. 4B , a photoresist layer 51 is formed in the n-type MOSFET formation region. Then, Al ions 41 are implanted into the amorphous silicon layer 40 in the p-type MOSFET formation region using the photoresist layer 51 as an implantation mask.
  • Step 3 As shown in FIG. 4C , the photoresist layer 51 is removed and then a photoresist layer 52 is formed in the p-type MOSFET formation region. Then, Mg ions 42 are implanted into the amorphous silicon layer 40 in the n-type MOSFET formation region, using the photoresist layer 52 as an implantation mask.
  • Step 4 As shown in FIG. 4D , the photoresist layer 52 is removed. Thus, the Mg ions are implanted in the n-type MOSFET formation region of the amorphous silicon layer 40 and the Al ions are implanted in the p-type MOSFET formation region thereof.
  • Step 5 As shown in FIG. 4E , a heat treatment is performed to segregate Mg and Al at an upper part and a lower part of the amorphous silicon layer 40 .
  • the heat treatment is performed at a processing temperature of 600° C. for a processing time of 30 seconds by a RTA method, for example.
  • Mg segregated layers 45 and 46 are formed on the lower and upper parts of the amorphous silicon layer 40 in the n-type MOSFET formation region
  • Al segregated layers 43 and 44 are formed on the lower and upper parts of the amorphous silicon layer 40 in the p-type MOSFET formation region.
  • Step 6 As shown in FIG. 4F , the Mg segregated layer 46 , the Al segregated layer 44 , and the amorphous silicon layer 40 are removed by wet etching with a KOH aqueous solution, for example.
  • Step 7 As shown in FIG. 4G , the Mg segregated layer 45 and the Al segregated layer 43 are oxidized by plasma oxidization with oxygen plasma, whereby the cap layer 12 composed of MgO and the cap layer 22 composed of AlO are formed.
  • Step 8 As shown in FIG. 4H , the TiN layer 3 and the tungsten layer 4 are sequentially formed.
  • step 11 in the first embodiment, the TiN layer 3 and the tungsten layer 4 are etched at the same time, and the cap layers 12 and 22 , and the insulation layer 1 are etched, whereby the gate electrodes are formed.
  • FIGS. 5A to 5C show a method for producing another CMOS semiconductor device according to the fourth embodiment.
  • step 5 after step 5 ( FIG. 4E ), only the Mg segregated layer 46 and the Al segregated layer 44 formed on the upper part of the amorphous silicon layer 40 are etched, and the amorphous silicon layer 40 remains.
  • the amorphous silicon layers 40 in the n-type MOSFET formation region and the p-type MOSFET formation region are etched at the same time using a resist mask (not shown), for example.
  • the Mg segregated layer 44 , the Al segregated layer 43 , and the insulation layer 1 are etched, whereby gate electrodes are formed.
  • a gate metal 48 composed of NiSi is formed by a reaction between amorphous silicon and nickel, using a step of producing a FUSI gate.
  • the process can be performed with a high degree of accuracy.
  • FIGS. 6A to 6H show a method for producing a CMOS semiconductor device according to a fifth embodiment.
  • the production method includes the following steps 1 to 8.
  • the same references as those in FIGS. 1A to 1K show the same or corresponding parts.
  • Step 1 As shown in FIG. 6A , the insulation layer 1 composed of HfSiON is formed on a semiconductor substrate (not shown) and then an amorphous silicon layer 60 is formed by the CVD method or the like.
  • Step 2 As shown in FIG. 6B , a TEOS (or SiN) layer 55 is formed in the n-type MOSFET formation region. Then, an Al layer 43 and an amorphous silicon layer 61 are formed by the sputtering method or the CVD method.
  • a TEOS (or SiN) layer 55 is formed in the n-type MOSFET formation region. Then, an Al layer 43 and an amorphous silicon layer 61 are formed by the sputtering method or the CVD method.
  • Step 3 As shown in FIG. 6C , a heat treatment is performed to diffuse Al, and the Al layer 43 is formed on a surface of a polycrystalline silicon layer 63 and on the insulation layer 1 . In addition, in the heat treatment step, the amorphous silicon layer 61 becomes the polycrystalline silicon layer 63 .
  • Step 4 As shown in FIG. 6D , the polycrystalline silicon layer 63 and the Al layer 43 are removed, so that the Al layer 43 remains only on the insulation layer 1 in the p-type MOSFET formation region.
  • Step 5 As shown in FIG. 6E , the TEOS layer 55 is removed. Then, a TEOS layer 56 is formed in the p-type MOSFET formation region. Then, an Mg layer 44 and an amorphous silicon layer 64 are formed by the sputtering method or the CVD method.
  • Step 6 As shown in FIG. 6F , a heat treatment is performed to diffuse Mg, and the Mg layer 44 is formed on a surface of a polycrystalline silicon layer 65 and on the insulation layer 1 .
  • the amorphous silicon layer 64 becomes the polycrystalline silicon layer 65 .
  • Step 7 As shown in FIG. 6G , the layers formed above the polycrystalline silicon layer 62 are all removed. Thus, there remain the insulation layer 1 , the Mg layer 44 formed on the insulation layer 1 in the n-type MOSFET formation region, and the Al layer 43 formed on the insulation layer in the p-type MOSFET formation region. In addition, plasma oxidation is performed with oxygen plasma, so that the cap layer 12 composed of MgO and the cap layer 22 composed of AlO are formed.
  • Step 8 As shown in FIG. 6H , the TiN layer 3 and the tungsten layer 4 are sequentially formed.
  • step 11 in the first embodiment, the TiN layer 3 and the tungsten layer 4 are etched at the same time, and then the cap layers 12 and 22 , and the insulation layer 1 are etched, whereby gate electrodes are formed.
  • the processing can be implemented with a high degree of accuracy.
  • FIGS. 7A to 7F show a method for producing a CMOS semiconductor device according to a sixth embodiment.
  • the production method includes the following steps 1 to 6.
  • the same references as those in FIGS. 1A to 1K show the same or corresponding parts.
  • Step 1 As shown in FIG. 7A , a dielectric body composed of HfSiON or the like, and a polycrystalline silicon layer are laminated on the semiconductor substrate (not shown) composed of silicon, for example. Then, these are etched at the same time to form a gate electrode composed of the insulation layer 1 and a polycrystalline silicon layer 70 in each of the n-type MOSFET formation region and the p-type MOSFET formation region.
  • a gate metal of each gate electrode is composed of the polycrystalline silicon layer 70 , the high-accuracy processing can be implemented by one etching step.
  • a gate length of the gate electrode is about 20 ⁇ m.
  • Step 2 As shown in FIG. 7B , a silicon oxide layer is formed on the whole surface by the CVD method, for example. Then, an upper surface is flattened by a CMP method, and an interlayer insulation layer 71 is formed.
  • Step 3 As shown in FIG. 7C , a mask 72 (not shown in FIG. 7C ) is formed in the p-type MOSFET formation region, and the polycrystalline silicon 70 in the n-type MOSFET formation region is selectively removed.
  • Step 4 As shown in FIG. 7D , a cap layer 73 composed of MgO, for example, a TaSiN layer 74 , and a tungsten layer 75 are sequentially formed on the mask 72 . These layers are formed by the ALD method, or the MOCVD method, for example.
  • Step 5 As shown in FIG. 7E , the cap layer 73 , the TaSiN layer 74 , and the tungsten layer 75 are etched from the above. Then, a mask (not shown) is formed on the n-type MOSFET, and the polycrystalline silicon 70 of the p-type MOSFET is selectively etched. Then, a cap layer 76 composed of AlO, a Pt layer 77 , and the tungsten layer 75 are formed.
  • Step 6 As shown in FIG. 7F , after flattening the surface by the CMP method, the interlayer insulation layer 71 is removed, and a gate electrode (replacement gate) is formed in each of the n-type MOSFET formation region and the p-type MOSFET formation region.
  • a gate electrode replacement gate
  • the metal material having low heat resistance can be selected as the gate metal material, so that a range of options to choose materials can be expanded.
  • the threshold voltage can be adjusted by appropriately selecting a material of the gate metal.
  • the gate electrode of the n-type MOSFET and the gate electrode of the p-type MOSFET each have the insulation layer made of the common high-k material such as HfSiON, and the cap layer made of the different material such as nCap composed of LaO or MgO, for example, or pCap composed of AlO, for example.
  • the threshold voltage is correctly controlled.
  • the metal layer (metal) formed on the cap layer is made of the same material in each gate electrode.
  • the gate electrodes of the n-type MOSFET and the p-type MOSFET may only have the same metal layer (metal) and have different insulation layers (n-high-k and p-high-k).
  • the gate electrodes have the following stacked structures.
  • n-type MOSFET W/TiN/HfMgO/Si substrate
  • the gate electrodes may have the following structures.
  • n-type MOSFET W/TiN/MgO/AlO/HfSiON/Si substrate
  • the cap layer may have a two-layer structure.
  • AlO and MgO may be exchanged in a vertical direction.
  • an additional cap layer may be inserted to only one of the n-type MOSFET and the p-type MOSFET.
  • the gate electrodes have the following stacked structures.
  • n-type MOSFET W/TiN/MgO/HfSiON/Si substrate
  • SiO 2 or SiON is provided on the Si substrate, the cap layer is provided thereon, and the insulation layer composed of the high-k material such as HfSiON is provided thereon as follows.
  • n-type MOSFET W/TiN/HfSiON/MgO/SiO 2 (SiON)/Si substrate
  • the cap layer composed of MgO or AlO can be arranged at a position close to the Si substrate. As a result, the threshold voltage can be controlled more easily.
  • a final structure may become as shown in FIG. 10B due to a reaction between polycrystalline silicon and Ni or Pt.
  • the present invention is characterized in that since the gate electrodes of the n-type MOSFET and the p-type MOSFET are composed of the same gate metal, these gate electrodes can be formed at the same time in one etching step, so that the etching process can be performed with a very high degree of accuracy.
  • the materials of the gate metals may be different between the n-type MOSFET and the p-type MOSFET.
  • the stacks at the time of etching of the gate electrode is as follows.
  • n-type MOSFET Poly-Si/MgO/HfSiO/Si substrate
  • n-type MOSFET FUSI/NiSi/MgO/HfSiO/Si substrate
  • a HALO layer or an extension layer may be formed according to need.
  • FIG. 11 is a schematic view of a CMOS semiconductor device according to a ninth embodiment.
  • the CMOSFET has three kinds of structures as gate electrodes of n-type CMOSFETs as follows.
  • n-type MOSFET1 Poly-SI/TiN/LaO/HfSiO/Si substrate
  • n-type MOSFET2 Poly-SI/TiN/HfSiO/Si substrate
  • n-type MOSFET3 Poly-SI/TiN/AlO/HfSiO/Si substrate
  • SiO 2 film is provided on the surface of the Si substrate in FIG. 11 , it may be omitted.
  • threshold voltages (Vth) are shifted to +0.2V (MOSFET1), +0.5V (MOSFET2), and +0.8V (MOSFET3) as compared with the structure in which the gate insulation layer is only composed of SiO 2 .
  • p-type MOSFET1 Poly-SI/TiN/LaO/HfSiO/Si substrate
  • p-type MOSFET2 Poly-SI/TiN/HfSiO/Si substrate
  • p-type MOSFET3 Poly-SI/TiN/AlO/HfSiO/Si substrate
  • threshold voltages (Vth) are shifted to ⁇ 0.2V (MOSFET1), ⁇ 0.5V (MOSFET2), and ⁇ 0.8V (MOSFET3) as compared with the structure in which the gate insulation layer is only composed of SiO 2 .
  • these gate electrodes are each formed of the same gate metal material, they can be made through only one etching step, so that the gate electrode can be high in processing accuracy.
  • CMOS semiconductor device containing a plurality of MOSFETs having different threshold voltages can be produced by combining the six kinds of gate electrodes.

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Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100038729A1 (en) * 2008-08-13 2010-02-18 Renesas Technology Corp. Method of manufacturing semiconductor device and semiconductor device
US20110115027A1 (en) * 2009-11-17 2011-05-19 International Business Machines Corporation Structure and method to obtain eot scaled dielectric stacks
US20110180879A1 (en) * 2010-01-25 2011-07-28 Samsung Electronics Co., Ltd. Cmos transistor, semiconductor device including the transistor, and semiconductor module including the device
US20120107966A1 (en) * 2009-03-02 2012-05-03 Qualcomm Incorporated Magnetic tunnel junction device and fabrication
US20120244712A1 (en) * 2011-03-25 2012-09-27 Tsubata Shuichi Manufacturing method of semiconductor device
US8395219B2 (en) 2008-07-01 2013-03-12 Panasonic Corporation Semiconductor device and fabrication method for the same
US8440520B2 (en) 2011-08-23 2013-05-14 Tokyo Electron Limited Diffused cap layers for modifying high-k gate dielectrics and interface layers
US8633118B2 (en) 2012-02-01 2014-01-21 Tokyo Electron Limited Method of forming thin metal and semi-metal layers by thermal remote oxygen scavenging
US8865581B2 (en) 2012-10-19 2014-10-21 Tokyo Electron Limited Hybrid gate last integration scheme for multi-layer high-k gate stacks
US8865538B2 (en) 2012-03-30 2014-10-21 Tokyo Electron Limited Method of integrating buried threshold voltage adjustment layers for CMOS processing
US9099336B2 (en) 2013-02-25 2015-08-04 Samsung Electronics Co., Ltd. Semiconductor device and fabricating method thereof
US10586854B2 (en) * 2017-01-04 2020-03-10 International Business Machines Corporation Gate-all-around field effect transistor having multiple threshold voltages

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5329294B2 (ja) * 2009-04-30 2013-10-30 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP2011003664A (ja) * 2009-06-17 2011-01-06 Renesas Electronics Corp 半導体装置およびその製造方法
JP5375362B2 (ja) * 2009-06-24 2013-12-25 富士通セミコンダクター株式会社 半導体装置の製造方法
JP2011009313A (ja) * 2009-06-24 2011-01-13 Panasonic Corp 半導体装置及びその製造方法
JP5372617B2 (ja) * 2009-06-24 2013-12-18 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
CN101930979B (zh) 2009-06-26 2014-07-02 中国科学院微电子研究所 控制器件阈值电压的CMOSFETs结构及其制造方法
DE102009031155B4 (de) * 2009-06-30 2012-02-23 GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG Einstellen einer Schwellwertspannung für komplexe Transistoren durch Diffundieren einer Metallsorte in das Gatedielektrikum vor der Gatestrukturierung
JP2011029483A (ja) * 2009-07-28 2011-02-10 Renesas Electronics Corp 半導体装置およびその製造方法
JP5407645B2 (ja) * 2009-08-04 2014-02-05 富士通セミコンダクター株式会社 半導体装置及びその製造方法
TWI488240B (zh) * 2009-09-28 2015-06-11 United Microelectronics Corp 半導體元件的製造方法
US8114739B2 (en) 2009-09-28 2012-02-14 Freescale Semiconductor, Inc. Semiconductor device with oxygen-diffusion barrier layer and method for fabricating same
JP5401244B2 (ja) * 2009-10-01 2014-01-29 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
WO2011101931A1 (ja) * 2010-02-17 2011-08-25 パナソニック株式会社 半導体装置及びその製造方法
KR101131891B1 (ko) * 2010-07-30 2012-04-03 주식회사 하이닉스반도체 매립게이트를 구비한 반도체 장치 제조방법
US10431583B2 (en) 2016-02-11 2019-10-01 Samsung Electronics Co., Ltd. Semiconductor device including transistors with adjusted threshold voltages
KR102495258B1 (ko) 2018-04-24 2023-02-03 삼성전자주식회사 반도체 장치
US10692734B2 (en) * 2018-10-25 2020-06-23 Applied Materials, Inc. Methods of patterning nickel silicide layers on a semiconductor device

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020135030A1 (en) * 2001-03-22 2002-09-26 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and manufacturing method thereof
US20020151125A1 (en) * 2001-04-11 2002-10-17 Samsung Electronics Co., Ltd. Method of forming a CMOS type semiconductor device having dual gates
US6897095B1 (en) * 2004-05-12 2005-05-24 Freescale Semiconductor, Inc. Semiconductor process and integrated circuit having dual metal oxide gate dielectric with single metal gate electrode
US20050282329A1 (en) * 2004-06-17 2005-12-22 Hong-Jyh Li CMOS transistors with dual high-k gate dielectric and methods of manufacture thereof
US20060001106A1 (en) * 2004-06-30 2006-01-05 Metz Matthew V Using different gate dielectrics with NMOS and PMOS transistors of a complementary metal oxide semiconductor integrated circuit
US20060022271A1 (en) * 2004-07-28 2006-02-02 Metz Matthew V Using different gate dielectrics with NMOS and PMOS transistors of a complementary metal oxide semiconductor integrated circuit
US20060180870A1 (en) * 2005-02-14 2006-08-17 Kabushiki Kaisha Toshiba Semiconductor device
US20070210354A1 (en) * 2006-03-10 2007-09-13 Renesas Technology Corp. Semiconductor device and semiconductor device manufacturing method
US20080160736A1 (en) * 2006-12-28 2008-07-03 Texas Instruments Inc. Lanthanide series metal implant to control work function of metal gate electrodes
US20080237655A1 (en) * 2007-03-29 2008-10-02 Kabushiki Kaisha Toshiba Semiconductor apparatus and method for manufacturing same
US20080303099A1 (en) * 2007-06-08 2008-12-11 Rohm Co., Ltd. Semiconductor Device and Fabrication Method Thereof

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4792716B2 (ja) * 2004-07-06 2011-10-12 日本電気株式会社 半導体装置およびその製造方法
KR100653721B1 (ko) * 2005-06-30 2006-12-05 삼성전자주식회사 질소주입활성영역을 갖는 반도체소자 및 그 제조방법
JP4850458B2 (ja) * 2005-09-12 2012-01-11 富士通セミコンダクター株式会社 半導体装置およびその製造方法

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020135030A1 (en) * 2001-03-22 2002-09-26 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and manufacturing method thereof
US20020151125A1 (en) * 2001-04-11 2002-10-17 Samsung Electronics Co., Ltd. Method of forming a CMOS type semiconductor device having dual gates
US6897095B1 (en) * 2004-05-12 2005-05-24 Freescale Semiconductor, Inc. Semiconductor process and integrated circuit having dual metal oxide gate dielectric with single metal gate electrode
US20050282329A1 (en) * 2004-06-17 2005-12-22 Hong-Jyh Li CMOS transistors with dual high-k gate dielectric and methods of manufacture thereof
US20060001106A1 (en) * 2004-06-30 2006-01-05 Metz Matthew V Using different gate dielectrics with NMOS and PMOS transistors of a complementary metal oxide semiconductor integrated circuit
US20060022271A1 (en) * 2004-07-28 2006-02-02 Metz Matthew V Using different gate dielectrics with NMOS and PMOS transistors of a complementary metal oxide semiconductor integrated circuit
US20060180870A1 (en) * 2005-02-14 2006-08-17 Kabushiki Kaisha Toshiba Semiconductor device
US20070210354A1 (en) * 2006-03-10 2007-09-13 Renesas Technology Corp. Semiconductor device and semiconductor device manufacturing method
US20080160736A1 (en) * 2006-12-28 2008-07-03 Texas Instruments Inc. Lanthanide series metal implant to control work function of metal gate electrodes
US20080237655A1 (en) * 2007-03-29 2008-10-02 Kabushiki Kaisha Toshiba Semiconductor apparatus and method for manufacturing same
US20080303099A1 (en) * 2007-06-08 2008-12-11 Rohm Co., Ltd. Semiconductor Device and Fabrication Method Thereof

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US9543300B2 (en) 2010-01-25 2017-01-10 Samsung Electronics Co., Ltd. CMOS transistor, semiconductor device including the transistor, and semiconductor module including the device
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US20110180879A1 (en) * 2010-01-25 2011-07-28 Samsung Electronics Co., Ltd. Cmos transistor, semiconductor device including the transistor, and semiconductor module including the device
US20120244712A1 (en) * 2011-03-25 2012-09-27 Tsubata Shuichi Manufacturing method of semiconductor device
US8956982B2 (en) * 2011-03-25 2015-02-17 Kabushiki Kaisha Toshiba Manufacturing method of semiconductor device
US8440520B2 (en) 2011-08-23 2013-05-14 Tokyo Electron Limited Diffused cap layers for modifying high-k gate dielectrics and interface layers
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US8865581B2 (en) 2012-10-19 2014-10-21 Tokyo Electron Limited Hybrid gate last integration scheme for multi-layer high-k gate stacks
US9099336B2 (en) 2013-02-25 2015-08-04 Samsung Electronics Co., Ltd. Semiconductor device and fabricating method thereof
US10586854B2 (en) * 2017-01-04 2020-03-10 International Business Machines Corporation Gate-all-around field effect transistor having multiple threshold voltages

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US20130034953A1 (en) 2013-02-07
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JP5284276B2 (ja) 2013-09-11

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