US20100219158A1 - Method for dry etching interlayer insulating film - Google Patents

Method for dry etching interlayer insulating film Download PDF

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US20100219158A1
US20100219158A1 US12/301,786 US30178607A US2010219158A1 US 20100219158 A1 US20100219158 A1 US 20100219158A1 US 30178607 A US30178607 A US 30178607A US 2010219158 A1 US2010219158 A1 US 2010219158A1
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gas
etching
interlayer insulating
resist
insulating film
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Yasuhiro Morikawa
Koukou Suu
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Ulvac Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics

Definitions

  • the present invention relates to a method for dry etching an interlayer insulating film.
  • interlayer insulating films were commonly made of SiO 2 . Since the 90 nm node, however, low dielectric constant materials (or low-k materials) have been increasingly substituted for SiO 2 as the material for interlayer insulating films in order to solve the problem of wiring delay. It has been proposed that, in order to etch fine grooves or holes in such low dielectric constant films, ArF resist material may be used, instead of conventionally used KrF resist material, since the former is used with a shorter wavelength of light than the latter and hence is suitable for high precision processing (see, e.g., Patent Document 1).
  • ArF resist materials generally have poor plasma resistance. Therefore, a fine exposure pattern of an ArF resist material is likely to be distorted due to damage by the plasma etching process. This distortion is directly transferred to the low dielectric constant film under the resist during the etching process, which tends to cause irregularities, such as striations, in the edge surfaces of fine grooves or holes formed in the low dielectric constant film.
  • an object of the present invention to provide a method for dry etching an interlayer insulating film in such a manner as to prevent damage to the resist.
  • the present invention provides a method for dry etching an interlayer insulating film with an ArF resist or KrF resist thereon, the method comprising dry etching fine features into the interlayer insulating film with an etching gas in such a manner as to form a polymer film on the ArF or KrF resist from the etching gas, wherein the etching gas is introduced under a pressure of 0.5 Pa or less, and wherein a Fourier transform infrared spectrum of the polymer film includes a C—F bond peak at about 1200 cm ⁇ 1 , a C—N bond peak at about 1600 cm ⁇ 1 , and a C—H bond peak at about 3300 cm ⁇ 1 .
  • the introduction of the etching gas under a pressure of 0.5 Pa or less prevents the formation of reactive species of the etching gas, thereby reducing damage to the resist. Further, since the interlayer insulating film is etched in such a manner as to form a polymer film on the resist from the etching gas, damage to the resist is further reduced, resulting in a high etch selectivity ratio (i.e., a high ratio of the etch rate of the interlayer insulating film to that of the resist).
  • the etching gas is preferably a mixture of a CF-based gas, a N-containing gas, and a low molecular weight hydrocarbon gas.
  • the use of these gases allows for the formation of a polymer film on the resist which film exhibits C—F, C—N, and C—H bond peaks in its absorption spectrum. This reduces damage to the resist and allows the low dielectric constant film (or interlayer insulating film) to be etched without premature etch stop.
  • the etching gas is preferably a mixture of a C x F y H z gas and a N-containing gas.
  • the use of these gases also allows for the formation of a polymer film on the resist which film exhibits C—F, C—N, and C—H bond peaks in its absorption spectrum. This reduces damage to the resist and allows the low dielectric constant film (or interlayer insulating film) to be etched without premature etch stop.
  • the CF-based gas preferably includes at least one gas selected from the group consisting of CF 4 , C 3 F 8 , C 2 F 6 , C 4 F 8 , C 5 F 8 and C x F y I.
  • the low molecular weight hydrocarbon is preferably selected from the group consisting of CH 4 , C 2 H 6 , C 3 H 8 , C 4 H 10 , and C 2 H 2 .
  • the C x F y H z gas is preferably CHF 3 gas.
  • the N-containing gas preferably includes at least one gas selected from the group consisting of nitrogen gas, NO x , NH 3 , methylamine, and dimethylamine.
  • the C x F y I gas is preferably C 3 F 7 I gas or CF 3 I gas
  • the interlayer insulating film is preferably an SiOCH-based material.
  • An advantage of the present invention is that it etches an interlayer insulating film in a low pressure to reduce damage to the resist and hence reduce striations.
  • Another advantage of the invention is that it etches an interlayer insulating film in such a manner as to form a polymer film on the resist from the etching gas to reduce damage to the resist, thereby achieving a high etch selectivity ratio.
  • FIG. 1 shows an etching system 1 for implementing a method for dry etching an interlayer insulating film according to the present invention.
  • the etching system 1 includes a vacuum chamber 11 that allows for etching in low-temperature, high-density plasma.
  • the vacuum chamber 11 includes vacuuming means 12 such as a turbo molecular pump.
  • the vacuum chamber 11 is made up of a substrate treatment section 13 and a plasma generating section 14 which lies on the substrate treatment section 13 .
  • a substrate mounting unit 2 is provided at the bottom center of the substrate treatment section 13 .
  • the substrate mounting unit 2 includes a substrate electrode 21 on which a processing substrate S is placed, an insulator 22 , and a support base 23 .
  • the insulator 22 is interposed between the substrate electrode 21 and the support base 23 .
  • the substrate electrode 21 is connected to a first high frequency power supply 25 through a blocking capacitor 24 and acts as a floating potential electrode. This electrode 21 is negatively biased.
  • a top panel 31 is provided at the top of the plasma generating section 14 and faces the substrate mounting unit 2 . It is fixed to the sidewall of the plasma generating section 14 and is connected to a second high frequency power supply 33 through a variable capacitor 32 . This top panel 31 is at a floating potential and acts as the opposite electrode.
  • a gas feed path 41 of gas feeding means 4 is coupled to the top panel 31 to introduce an etching gas into the vacuum chamber 11 .
  • This gas feed path 41 is connected to a gas source 43 through gas flow rate control means 42 .
  • gas flow rate control means 42 It should be noted that although only one gas source 43 is shown in FIG. 1 , there may be a number of gas sources 43 corresponding to the number of types of gas used in the etching process. In such a case, the gas feed path 41 may be branched into a number of branches corresponding to the number of gas sources 43 .
  • the plasma generating section 14 has a cylindrical dielectric sidewall.
  • a magnetic field coil 51 may be provided around the outside of this sidewall as magnetic field generating means. In such a case, the magnetic field coil 51 produces a circular magnetic neutral line (not shown) within the plasma generating section 14 .
  • a high frequency antenna coil 52 is disposed between the magnetic field coil 51 and the outside of the sidewall of the plasma generating section 14 to generate plasma.
  • the high frequency antenna coil 52 has a parallel antenna structure, and is connected to the junction (or branch point) 34 between the variable capacitor 32 and the second high frequency power supply 33 to receive a voltage from the second high frequency power supply 33 .
  • the high frequency antenna coil 52 generates an alternating electric field along the magnetic neutral line produced by the magnetic field coil 51 to produce a plasma along the line.
  • the antenna coil 52 for generating plasma receives a voltage from the second high frequency power supply 33 , it is to be understood that in other embodiments a third high frequency power supply may be provided which is connected to the antenna coil 52 . Further, means may be provided to adjust the voltage applied to the antenna coil to a predetermined value.
  • the present invention is applied to interlayer insulating films composed of a low dielectric constant material (or low-k material) and formed on a substrate S.
  • low dielectric constant materials include SiOCH-based materials, such as HSQ and MSQ, which are applied by spin coating, etc. It will be noted that they may be porous.
  • SiOCH-based materials examples are those available under the trade names: “LKD5109r5” from JSR Co., Ltd.; “HSG-7000” from Hitachi Chemical Co., Ltd.; “HOSP” and “Nanoglass” from Honeywell Electric Materials Inc.; “OCD T-12” and “OCD T-32” from Tokyo Ohka Kogyo Co., Ltd.; “IPS 2.4” and “IPS 2.2” from Catalysts & Chemicals Industries Co., Ltd.; “ALCAP-S 5100” from Asahi Kasei Corporation; and “ISM” from ULVAC, Inc.
  • the method begins by applying a resist material to such an interlayer insulating film and then forming a predetermined (resist) pattern by photolithography.
  • suitable resist materials include known KrF resist materials (e.g., KrFM78Y from JSR Co., Ltd.) and known ArF resist materials (e.g., UV-II, etc.).
  • KrF resist materials e.g., KrFM78Y from JSR Co., Ltd.
  • ArF resist materials e.g., UV-II, etc.
  • the substrate S with the interlayer insulating film thereon is placed on the substrate electrode 21 within the vacuum chamber 11 .
  • the interlayer insulating film on the substrate S is then etched with a high etch selectivity ratio and without striations by introducing an etching gas from the etching gas feeding means 4 and applying RF power from the second high frequency power supply 33 such that a plasma is generated within the plasma generating section 14 .
  • the etching gas is introduced under an operating pressure of 0.5 Pa or less, preferably 0.1-0.5 Pa, into the vacuum chamber 11 in order to prevent radical reactions.
  • the etching gas used for the etching method of present invention is of the type that allows the interlayer insulating film to be etched without premature etch stop and in such a manner that a desired polymer film is formed on the resist.
  • This etching gas may be a mixture of a CF-based gas, a N-containing gas, and a low molecular weight hydrocarbon gas.
  • the CF-based gas serves to etch SiO in the interlayer insulating film
  • the N-containing gas and the low molecular weight hydrocarbon gas serve to etch CH in the interlayer insulating film. These gases also contribute to reducing damage to the resist.
  • the CF-based gas may be composed of at least one gas selected from the group consisting of CF 4 , C 3 F 8 , C 2 F 6 , C 4 F 8 , and C 5 F 8 .
  • it may be a C x F y I gas (which contains iodine) such as C 3 F 7 I or CF 3 I, for example.
  • the iodine (I) serves to remove excess fluorine atoms in the gas phase .
  • the low molecular weight hydrocarbon is preferably linear and may be selected from, e.g., CH 4 , C 2 H 6 , C 3 H 8 , C 4 H 10 , and C 2 H 2 .
  • suitable N-containing gases include nitrogen gas, NO x , NH 3 , methylamine, and dimethylamine.
  • the etching gas may be a mixture of a C x F y H z gas and a N-containing gas. Each gas in this gas mixture acts in the same manner as the corresponding gas in the above gas mixture including three gases.
  • the C x F y H z gas may be, e.g., CHF 3 .
  • suitable N-containing gases include nitrogen gas, NO x , NH 3 , methylamine, and dimethylamine.
  • the etching gas is not mixed with a dilution gas of any of the following noble gases: helium, neon, argon, krypton, and xenon.
  • etching gas such as described above allows the low dielectric constant interlayer insulating film to be etched in such a manner that a desired polymer film is formed on the resist from the etching gas, thereby preventing damage to the resist.
  • This polymer film exhibits a C—F bond peak at about 1200 cm ⁇ 1 , a C—N bond peak at about 1600 cm ⁇ 1 , and a C—H bond peak at about 3300 cm ⁇ 1 in its absorption spectrum (measured by a Fourier transform infrared spectrophotometer), although this may vary slightly depending on the measurement method used.
  • the polymer film is a nitrogen-containing CF-based polymer formed as a result of the combining of C from the etching gas with F, N, and H also from the etching gas.
  • the etching gas is an iodine-containing CF-based gas
  • a CF-based polymer film containing iodine is further formed during the etching process.
  • the interlayer insulating film is etched without premature etch stop by introducing an etching gas such as described above into the vacuum chamber 11 in such a manner that a polymer film such as described above is formed on the resist from the etching gas.
  • the flow rate of the CF-based gas introduced into the vacuum chamber 11 is preferably approximately 20-40%, more preferably approximately 20-30%, of the total etching gas flow.
  • the flow rate of the C x F y H z gas introduced into the vacuum chamber 11 is preferably approximately 20-40%, more preferably approximately 30-40%, of the total etching gas flow.
  • a polymer film was formed from the etching gas used for the dry etching method of the present invention, and the infrared absorption spectrum of the formed polymer film was measured by FT-IR.
  • CF 4 gas at a flow rate of 60 sccm
  • N 2 gas at a flow rate of 90 sccm
  • CH 4 gas at a flow rate of 70 sccm
  • the spectrum of the polymer film deposited from the etching gas of the present invention (i.e., the CF 4 /N 2 /CH 4 gas mixture) had a C—N bond beak (at about 1600 cm ⁇ 1 ) and a C—H bond peak (at about 3300 cm ⁇ 1 ) as did the spectrum of the polymer film deposited from N 2 /CH 4 gas mixture, and also had a C—F bond peak (at about 1200 cm ⁇ 1 ) as did the spectrum of the polymer film deposited from the C 3 F 8 /Ar gas mixture.
  • an SiOCH film serving as an interlayer insulating film was formed on a silicon substrate S by plasma CVD, and an organic film serving as a BARC was formed on the SiOCH film by spin coating.
  • UV-II an ArF resist material
  • the substrate with these films formed thereon was then placed on the substrate electrode 21 of the etching system 1 shown in FIG. 1 .
  • the BARC was etched by introducing a BARC etching gas mixture of CF 4 gas (at a flow rate of 25 sccm) and CHF 3 gas (at a flow rate of 25 sccm) and generating a plasma therefrom.
  • FIG. 3( a ) shows an SEM micrograph of the top surface of the etched substrate
  • FIG. 3( b ) shows a cross-sectional SEM micrograph of the hole enclosed by dotted line A in FIG. 3( a ).
  • FIG. 3( a ) indicates that the top surface of the substrate, i.e., the surface of the resist, had no irregularities. Further, the cross-sectional SEM micrograph of FIG. 3( b ) indicates that no premature etch stop occurred and a polymer film was formed on the top surface of the substrate and on the interior surface of the inlet end of the hole, indicating that the interlayer insulating film was etched without striations. [The formed polymer film is shown shaded and is indicated by B in FIG. 3( b ).] That is, the etching method of the present invention allows an interlayer insulating film to be etched without damage to the resist and hence without striations on the surfaces in the holes formed in the interlayer insulating film.
  • This example examined the relationship between the flow rate ratio of the gases in the etching gas mixture and the selectivity ratio (i.e., the ratio of the etch rate of the interlayer insulating film to that of the resist).
  • an interlayer insulating film was etched in the etching system 1 in the following manner.
  • the parameters of the system were set to the same values as in Practical Example 2 except that the antenna side high frequency power supply was 2000 W and the flow rate ratio of the gases in the etching gas mixture was varied. More specifically, the flow rate of the CH 4 gas was fixed at 70 sccm and the flow rates of the CF 4 gas and N 2 gas were varied as follows:
  • FIG. 4 Observation of FIG. 4 reveals the following facts. Under the flow rate conditions (1), i.e., when the flow rates of the CF 4 gas and the N 2 gas were 20 sccm and 30 sccm (i.e., 16% and 25% of the total etching gas flow), respectively, the etch rates of the interlayer insulating film and the resist were 160 nm/min and 12 nm/min, respectively, and hence the selectivity ratio was approximately 13.
  • the etch rates of the interlayer insulating film and the resist were 195 nm/min and 3 nm/min, respectively, and hence the selectivity ratio was 65, which is higher than that obtained under the flow rate conditions (1).
  • the etch rates of the interlayer insulating film and the resist were 200 nm/min and 18 nm/min, respectively, and hence the selectivity ratio was approximately 11.
  • the selectivity ratio (of the interlayer insulating film to the resist) can be optimized by adjusting the ratio of the gases in the etching gas mixture. More specifically, when the flow rate of the CF-based gas was 21-28% of the total etching gas flow, the etch rate of the resist was low resulting in a high selectivity ratio.
  • FIGS. 5( a ) to 5 ( d ) Observation of FIGS. 5( a ) to 5 ( d ) reveals that the etching under the flow rate conditions (1), (2), and (5) above resulted in the formation of irregularities on the surface of the resist and hence the formation of striations.
  • the etching under the flow rate conditions (3) did not cause striations, resulting from reduced irregularities on the resist surface. This means that when the flow rate of the CF-based gas was 25-27% of the total etching gas flow, the etching process not only exhibited a high selectivity ratio, but also did not create irregularities on the resist surface and hence did not create striations.
  • interlayer insulating films on substrates were etched in the etching system 1 . These interlayer insulating films were similar to those used in Practical Example 2.
  • the etching gas mixture used in this example additionally included Ar gas.
  • the flow rates (sccm) of the C 3 F 8 , Ar, N 2 , and CH 4 gases of the etching mixture were varied as follows:
  • FIGS. 6( a ) to 6 ( e ) Observation of FIGS. 6( a ) to 6 ( e ) reveals that the etching under these flow rate conditions (a) to (e) caused the resist surface to be uneven and roughened, thereby creating striations on the sides of the holes. Further, the occurrence of premature etch stop is also observed, meaning that the above conditions (a) to (e) are not practical. Thus the etching under these conditions (a) to (e) resulted in damage to the resist surface. This is the reason why the selectivity ratios obtained were impractically low, as shown in FIG. 7 .
  • the present invention allows an interlayer insulating film to be etched in such a manner as to reduce damage to the resist even if the resist is made of a material having low plasma resistance. Therefore, the invention is particularly advantageously applied to the dry etching of interlayer insulating films of a Low-k material through a resist of an ArF resist material. Thus, the present invention is useful in the semiconductor manufacturing field.
  • FIG. 1 is a schematic diagram showing a configuration of an etching system for implementing a dry etching method according to the present invention.
  • FIG. 2 is a graph showing measured FT-IR spectra of films that have been etched by the dry etching method of the present invention.
  • FIG. 3 shows SEM micrographs of a substrate that has been etched by the etching method of the present invention, wherein FIG. 3( a ) is atop view and FIG. 3( b ) is a cross-sectional view.
  • FIG. 4 is a graph showing the etch rates (nm/min) of an interlayer insulating film and the resist thereon and the etch selectivity ratio of the interlayer insulating film to the resist, as a function of the ratio of the gases in the etching gas mixture.
  • FIGS. 5( a ) to 5 ( d ) are cross-sectional SEM micrographs of substrates that have been etched with etching gas mixtures containing different ratios of constituents.
  • FIGS. 6( a ) to 6 ( e ) are cross-sectional SEM micrographs of substrates that have been etched by a conventional etching method.
  • FIG. 7 is a graph showing the etch rate (nm/min) of the interlayer insulating film on each substrate etched by the conventional etching method, the etch rate (nm/min) of the resist on the interlayer insulating film, and the etch selectivity ratio of the interlayer insulating film to the resist.
US12/301,786 2006-05-24 2007-05-16 Method for dry etching interlayer insulating film Abandoned US20100219158A1 (en)

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CN113544823A (zh) * 2020-02-10 2021-10-22 株式会社日立高新技术 等离子处理方法
WO2021262841A1 (en) * 2020-06-26 2021-12-30 L'air Liquide, Societe Anonyme Pourl'etude Et L'exploitation Des Procedes Georges Claude Iodine-containing fluorocarbon and hydrofluorocarbon compounds for etching semiconductor structures

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US7637269B1 (en) * 2009-07-29 2009-12-29 Tokyo Electron Limited Low damage method for ashing a substrate using CO2/CO-based process
JP2012096823A (ja) * 2010-11-01 2012-05-24 Takagi Seiko Corp 液体貯蔵容器
KR101102495B1 (ko) * 2011-08-11 2012-01-05 주식회사 미로 가로등
WO2020195559A1 (ja) 2019-03-22 2020-10-01 セントラル硝子株式会社 ドライエッチング方法及び半導体デバイスの製造方法

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KR20090012329A (ko) 2009-02-03
JPWO2007135906A1 (ja) 2009-10-01
DE112007001243T5 (de) 2009-05-28
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CN101454878A (zh) 2009-06-10
TW200809961A (en) 2008-02-16

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