US20080272437A1 - Threshold Adjustment for High-K Gate Dielectric CMOS - Google Patents

Threshold Adjustment for High-K Gate Dielectric CMOS Download PDF

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US20080272437A1
US20080272437A1 US11/743,101 US74310107A US2008272437A1 US 20080272437 A1 US20080272437 A1 US 20080272437A1 US 74310107 A US74310107 A US 74310107A US 2008272437 A1 US2008272437 A1 US 2008272437A1
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Prior art keywords
type fet
liner
fet device
gate
dielectric
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Bruce B. Doris
Eduard Albert Cartier
Vijay Narayanan
Vamsi Paruchuri
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GlobalFoundries Inc
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Priority to US11/743,101 priority Critical patent/US20080272437A1/en
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION reassignment INTERNATIONAL BUSINESS MACHINES CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: PARUCHURI, VAMSI, CARTIER, EDUARD ALBERT, NARAYANAN, VIJAY, DORIS, BRUCE B.
Priority to KR1020097014372A priority patent/KR20090130845A/ko
Priority to JP2010504608A priority patent/JP4917171B2/ja
Priority to CN200880014505.6A priority patent/CN101675513B/zh
Priority to PCT/EP2008/054218 priority patent/WO2008132026A1/en
Priority to EP08735946A priority patent/EP2165359B1/en
Priority to TW097116080A priority patent/TW200845384A/zh
Publication of US20080272437A1 publication Critical patent/US20080272437A1/en
Priority to US12/535,554 priority patent/US8187961B2/en
Assigned to GLOBALFOUNDRIES U.S. 2 LLC reassignment GLOBALFOUNDRIES U.S. 2 LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: INTERNATIONAL BUSINESS MACHINES CORPORATION
Assigned to GLOBALFOUNDRIES INC. reassignment GLOBALFOUNDRIES INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GLOBALFOUNDRIES U.S. 2 LLC, GLOBALFOUNDRIES U.S. INC.
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28176—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the definitive gate conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/981—Utilizing varying dielectric thickness

Definitions

  • the present invention relates to electronic devices.
  • it relates to CMOS structures having high-k containing gate dielectrics, and to ways to adjust the threshold voltage for the two type of devices independently from one another.
  • the mainstay material of microelectronics is silicon (Si), or more broadly. Si based materials.
  • Si based materials One such Si based material of importance for microelectronics is the silicon-germanium (SiGe) alloy.
  • the devices in the embodiments of the present disclosure are typically part of the art of single crystal Si based material device technology.
  • EOT equivalent oxide thickness
  • Metal gates are also enhanced by the use of metal gates.
  • the depletion region in the poly-Si next to the gate insulator can become an obstacle in increasing gate-to-channel capacitance, or equivalently to decrease the EOT.
  • the solution is to use a metal gate.
  • Metal gates also assure good conductivity along the width direction of the gates, reducing the danger of possible RC delays of the gate.
  • High performance small FET devices are also in need of precise threshold voltage control. As operating voltage decreases, to 2V and below, threshold voltages also have to decrease, and threshold variation becomes less tolerable. Every new element, such as a different gate dielectric, or a different gate material, influences the threshold voltage. Sometimes such influences are detrimental for achieving the desired threshold voltage values. Any technique which can affect the threshold voltage, without other effects on the devices is a useful one.
  • CMOS structure which contains at least one first type FET device and at least one second type FET device.
  • the first type FET contains a first gate insulator which has a first high-k dielectric.
  • the first type FET also has a first liner composed of oxide and having thickness between about 0.2 nm and 1.2 nm.
  • the second type FET contains a second gate insulator which has a second high-k dielectric.
  • the second type FET also has a second liner composed of oxide and with a thickness at least three times larger than the thickness of the first liner.
  • the invention further discloses a method for producing a CMOS structure.
  • the method includes the fabrication of a first type FET device with a first gate insulator containing a first high-k dielectric, and fabricating a temporary liner composed of oxide. Fabricating a second type FET device having a second gate insulator containing a second high-k dielectric, and fabricating a second liner also composed of oxide.
  • the method further includes removing completely the temporary liner by etching. In the place of the removed temporary liner a chemical oxide liner is formed with thickness of between about 0.2 nm and 1.2 nm, which is so selected to be at least three times smaller than the thickness of the second liner.
  • the method further includes exposing the first type FET device and the second type FET device to oxygen.
  • Oxygen penetrates through the second liner reaching the second high-k dielectric of the second gate insulator, and causes a predetermined shift in the threshold voltage of the second type EFT device, while, due to the extremely small thickness of the first liner, oxygen is not penetrating to the first high-k dielectric of the first gate insulator, and the threshold voltage of the first type FET device remains unchanged.
  • FIG. 1 shows a schematic cross section of a CMOS structure with one type device having a chemically deposited oxide liner, according to an embodiment of the present invention
  • FIG. 2 shows a schematic cross section of an initial stage in the processing of the CMOS structure in accordance to an embodiment of the present invention
  • FIG. 3 shows a schematic cross section of a following stage in the processing of a CMOS structure according to an embodiment of the present invention
  • FIG. 4 shows a schematic cross section of a stage in the processing of a CMOS structure according to an embodiment of the present invention where the chemical oxide liner has been formed;
  • FIG. 5 shows a schematic cross section of a stage in the processing of a CMOS structure according to an embodiment of the present invention where oxygen exposure shifts the threshold of one type of device
  • FIG. 6 shows a symbolic view of a processor containing at least one CMOS circuit according to an embodiment of the present invention.
  • FET Field Effect Transistor-s
  • Standard components of a FET are the source, the drain, the body in-between the source and the drain, and the gate.
  • the gate is overlaying the body and is capable to induce a conducting channel in the body between the source and the drain. In the usual nomenclature, the channel is hosted by the body.
  • the gate is typically separated from the body by the gate insulator.
  • a CMOS circuit contains at least one PFET and at least one NFET device.
  • NFET and PFET devices are fabricated together on the same chip, one is dealing with CMOS processing and the fabrication of CMOS structures.
  • an electrical attribute is the threshold voltage.
  • the threshold voltage When the voltage between the gate and the source exceeds the threshold voltage, the devices are capable to carry current between the source and the drain.
  • NFET threshold voltages are positive, and PFET threshold voltages are negative.
  • exposing a gate dielectric which comprises a high-k material to oxygen can result in shifting device thresholds in a direction which is the same as if one moved the gate workfunction toward a p + silicon workfunction. This results in lowering the PFET threshold, namely, making it a smaller negative voltage, and raising the NFET threshold, namely making it a larger positive voltage. It is preferable to carry out such an oxygen exposure at relatively low temperatures, and it is also preferable that, no high temperature processing should occur afterwards. Accordingly, such a threshold shifting operation should occur late in the device fabrication, typically after the source and the drain have been activated.
  • the thresholds of the different types of devices could be adjusted individually, meaning one would desire to use threshold tuning techniques, such as the oxygen exposure, in a manner that, the threshold of one type device becomes adjusted, without affecting the threshold of the other type of device.
  • Embodiments of the present invention teach such a selective adjusting of a device threshold by having a liner allowing oxygen diffusion for one type of FET, while modifying the liner of the other type of FET in such a manner that it becomes substantially impenetrable to oxygen.
  • FIG. 1 shows a schematic cross section of a CMOS structure with one type device having a chemically deposited oxide liner, according to an embodiment of the present invention.
  • the CMOS structure is adapted for being exposed to a low temperature oxidation, which may result in a threshold shift for one of the FETs.
  • the threshold shift is such that depending on which type of device allows oxygen diffusion to the gate insulator, the threshold of the PFET would be lowered, while the threshold of the NFET would be raised.
  • FIG. 1 depicts two devices, an NFET and a PFET, of the at least one NFET and PFET device that make up a CMOS structure.
  • the two devices is an NFET and which one is a PFET.
  • Embodiments of the invention cover both cases, as to which type of device, NFET or PFET, is the one whose threshold is adjusted by exposure to oxygen. Accordingly, a first type and a second type FET device will be discussed, with the understanding that if the first type is an NFET than the second type is a PFET, and the other way around, if the first type is a PFET than the second type is an NFET
  • the device bodies 50 are typically of a single crystal Si based material. In a representative embodiment of the invention the Si based material bodies 50 are essentially single crystal Si. In exemplary embodiments of the invention the device bodies 50 are part of a substrate.
  • the substrate may be any type known in the electronic art, such as bulk, or semiconductor on insulator (SOI), fully depleted, or partially depleted, FIN type, or any other kind. Also, substrates may have various wells of various conductivity types, in various nested positioning enclosing device bodies.
  • the figure shows what typically may be only a small fraction of an electronic chip, for instance a processor, as indicated by the wavy dashed line boundaries.
  • the devices may be isolated from one another by any method known in the art.
  • the figure shows a shallow trench 99 isolation scheme, as this is a typical advanced isolation technique available in the art.
  • the devices have source/drain extensions 40 , and silicided sources and drains 41 , as well as have silicide 42 on the gates 55 , 56 .
  • these elements all have their individual characteristics. Accordingly, when common indicators numbers are used in the figures of the present disclosure, it is because from the point of view of embodiments of the present invention the individual characteristics of such elements are not important.
  • CMOS processing typically the highest temperature-budgets, meaning temperature and time exposure combinations, are reached during source/drain fabrication.
  • CMOS structure of FIG. 1 since the sources and drains have already been fabricated, such high temperature, fabrication steps have already been performed, and the structure will not have to be exposed to further high temperature treatment.
  • exposure to a high temperature-budget means a comparable heat treatment as one used in source/drain fabrication.
  • the devices have standard side wall spacers 30 , 60 .
  • the spacer material is significant only to the extent that it is preferably impenetrable to oxygen.
  • the typical material used in the art for such spacers is nitride (SiN), which is an exemplary oxygen blocking material.
  • SiN nitride
  • the spacer of the first type FET device 30 and the spacer of the second type FET device 60 are fabricated during the same processing steps, and are the same material.
  • the gate stacks 55 , 56 may be different from one another, and the liners 22 , 21 differ from one another on purpose, the spacers 30 , 60 of the two type of devices are likely to be of different In their detailed shape.
  • the gate 55 of the first type FET device and of the gate 56 of the second type FET device usually have their own internal structures, typically in layers.
  • the gates, also referred to as gate stacks, 55 , 56 of the two types of devices may be processed independently of one another, and they typically have differing structures.
  • the first type FET device has a first gate insulator 10 and the second type FET device has a second gate insulator 11 .
  • Both gate insulators comprise a high-k dielectrics.
  • Such high-k dielectrics may be ZrO 2 , HfO 2 , Al 2 O 3 , HfSiO, HfSiON, and/or their admixtures.
  • the gate insulator of the first type FET device 10 and the gate insulator of the second type FET device 11 may comprise the same high-k material, or they may have differing high-k materials.
  • the common high-k material present in both gate insulators 10 , 11 is HfO 2 .
  • Bach gate insulator 10 , 11 apart of the high-k dielectric may have other components as well.
  • a very thin, less than about 1 nm, chemically deposited oxide may be present between the high-k dielectric layer and the device body 50 .
  • any and all inner structure, or the lack of any structure beyond simply containing a high-k dielectric, for either the first or second gate insulators 10 , 11 is within the scope of the embodiments of the present invention.
  • HfO 2 covering a thin chemical SiO 2 would be used as gate insulator, with an equivalent oxide thickness of about between 0.6 mil and 1.2 nm.
  • the second type FET device has a second liner 21 .
  • Liners are known in the art, and regularly used in standard CMOS processing.
  • the material of such liners is an oxide, typically silicon-dioxide (SiO 2 ).
  • the traditional role for the liners is in the protection of the gate during various processing steps, particularly during etching steps.
  • Such liners typically have selective etching properties relative to nitride and silicon.
  • the material of the second liner 21 typically SiO 2 , allows oxygen to diffuse through it, and allows oxygen to reach the gate dielectric.
  • the spacer 60 which spacer blocks oxygen, at the edges of the liner 21 , underneath the spacers, and next to the top of the gate, oxygen may enter the liner 21 , reach the gate insulator 11 , and shift the threshold voltage of the second type FET by a desired, predetermined amount.
  • FIG. 1 is only a schematic representation. As known in the art, there may be many more elements in the structures than present in the figures, but these would not effect the scope of the embodiments of the present invention. Such an element, as an example, may be any further layers between a liner and a gate. One type of such often used layer is called offset, or source/drain, spacer, which serve in source/drain fabrication.
  • the first type FET device has a first liner 22 .
  • the first liner 22 may by much thinner than the second liner 21 .
  • the thickness range of the first liner 22 is in the range of about between 0.2 nm and 1.2 nm, typically being between about 0.4 nm and 0.8 nm.
  • the first liner is also composed of oxide (SiO 2 ). Since the first liner is composed of oxide, oxygen may be capable to penetrate into it. However, the first liner 22 has a thickness significantly smaller than that of the second liner 21 , which second liner is typically over 3 nm thick. Accordingly, although given enough time oxygen may pass through the first liner 22 , it would do so in smaller quantities than are passing through the thicker second liner 21 .
  • the times involved in the technique of threshold shifting by oxygen exposure may usually be not more than a few hours.
  • the time while sufficient amount of oxygen crosses the second liner 21 and reaches the second gate insulator 11 to affect the desired threshold shift for the second type FET essentially no oxygen is crossing the first liner 22 , and threshold of the first type FET stays unchanged. Such an outcome is the desired effect sought by embodiments of the present invention.
  • the first liner 22 typically is a, so called, chemical oxide, referring to the manner in which it was produced. Such chemical oxide depositions are known in the art. It is possible, that at its smallest thickness ranges the first liner 22 to some degree is discontinuous. In general, for the embodiments of the present invention the thickness of the first liner is selected in such a range as to be thick enough to fill its role of protecting the gate during etching steps, which etching steps mainly occur during spacer fabrication; meanwhile, the first liner 22 has to be thin compared to the second liner 21 , such that it is capable to substantially prevent oxygen penetration.
  • the technique of chemically depositing the first liner 22 is selected because this technique is able to produce in a controlled manner very thin uniform layers of oxide.
  • FIG. 1 Manufacturing of NFET, PFET, and CMOS is very well established in the art. It is understood that, there are a large number of steps involved in such processing, and each step might have practically endless variations known to those skilled in the art. It is further understood that the whole range of known processing techniques are available for fabricating the disclosed device structures, and only those process steps will be detailed that are related to embodiments of the present invention.
  • FIG. 2 shows a schematic cross section of an initial stage in the processing of a CMOS structure according to an embodiment of the present invention.
  • a first gate insulator 10 has been implemented in a manner that this first gate insulator includes a first high-k dielectric.
  • the first gate insulator 10 may essentially be of a high-k dielectric in itself or may be implemented in combination with further dielectrics, such as, for instance, silicon dioxide, or others.
  • a temporary liner 20 has been deposited conformally essentially over all of the first type FET, in particular over the gate 55 and over the source/drain 40 regions.
  • the name of this liner “temporary” reflects the fact that in later processing steps it will be removed, to be replaces by the first liner 22 .
  • the temporary liner 20 consists essentially of an oxide material, typically SiO 2 .
  • This temporary liner 20 is similar to the second liner 21 of the second type FET and it is protecting the gate during various processing steps usually involved with source/drain fabrications.
  • the temporary liner 20 is of comparable thickness as the second liner 21 , consequently it is not adapted to prevent oxygen penetration to the first gate insulator 10 .
  • FIG. 2 also shows that in a second type FET device a second gate insulator 11 has been implemented in a manner that this second gate insulator includes a second high-k dielectric.
  • the second gate insulator 11 may essentially be of a high-k dielectric in itself, or may be implemented in combination with further dielectrics, such as, for instance silicon dioxide, or others.
  • the second liner 21 has been deposited conformally essentially over all of the second type FET device, in particular over the gate 56 and over the source/drain 40 regions.
  • the second liner 21 consists essentially of an oxide material, typically SiO 2 .
  • the temporary liner 20 and second liner 21 are being deposited during a single processing event, and thus have essentially identical properties. These liners 20 , 21 could also be deposited during differing steps in the fabrication, and they may not have identical characteristics, such as, for instance, thickness, or exact composition. Similar considerations hold for the high-k materials in the first and second gate insulators 10 , 11 . In representative embodiments of the invention they may be deposited during differing processing steps, and may, or may not, be of the same material.
  • the gate insulators as well may be deposited in the same processing steps.
  • the high-k materials in the first and second gate insulators 10 , 11 are of a same material, such as, for instance of HfO 2 .
  • the gate 55 of the first type FET device and the gate 56 of the second type FET device may be composite structures themselves. Since the threshold of the first type FET device is selected not to be adjusted during an oxygen exposure, the composition of the gate 55 of the first type FET device has to be properly selected in order for the threshold voltage of the first type FET device to end up with the desired value. For this reason the first type FET device gate 55 , may include a carefully selected, so called cap layer 55 ′′. Such cap layers are known in art, presented for instance by V. Narayanan et al, IEEE VLSI Symposium p. 224, (2006). The cap layer 55 ′′ may contain lanthanum (La), which under proper treatment may yield the desired threshold value.
  • La lanthanum
  • the first type FET device gate 55 my also contain a metal 55 ′, such as, for instance, W, Ta, or others known in the art.
  • the gate 56 of the second type FET device also may have internal structure, for instance a metal layer 56 ′. This metal layer 56 ′ may be in direct contact with the second gate insulator 11 .
  • a metal for the second type FET device gate 56 ′ may also be selected to be W, Ta, or other metals known to be suitable for gate fabrication.
  • metals deemed suitable for being parts of the gates may include Mo, Mn, TaN, TiN, WN, Ru, Cr, Ta, Nb, V, W, Mn, Re, and their combinations.
  • the metal layers 55 ′, 56 ′ of the first and second type FET device gates 55 , 56 may be fabricated of the same material. There may be further layers present in the as fabricated gate stacks, such as amorphous silicon ( ⁇ -Si) and poly silicon layers. In subsequent figures the possible internal structures of the gates will not be indicated, but it is understood that if such structure was present at the stage of processing shown on FIG. 2 , then that internal structure of the gates does not change, and it will he present all through further fabrication, and in the completed devices, as well. The figure also shows that by this stage usually the source/drain extensions 40 have also been processed.
  • FIG. 3 shows a schematic cross section of a following stage in the processing of a CMOS structure according to an embodiment of the present invention.
  • the process is shown at a stage where the temporary liner 20 has been completely removed by etching in the first type FET.
  • Etching steps that usually involve masking and etching with diluted HF, which can remove an liner, such as the temporary liner 20 , in a selective manner and leave other structures, such as the gate 55 , intact, are known to those skilled in the art.
  • a blocking mask 150 know to those skilled in the art, protects the regions of the second type FET.
  • FIG. 4 shows a schematic cross section of a stage in the processing of a CMOS structure according to an embodiment of the present invention, where the chemical oxide liner has been deposited.
  • the first type FET including the gate 55 and the first gate insulator 10 , have been covered by a conformally deposited oxide liner, the first liner 22 .
  • Forming oxide by chemical means is known in the art. Such a chemical forming is able to produce very thin uniform layers of oxide in a controlled manner.
  • the thickness of the first liner 22 in representative embodiments of the present invention is selected to be between about 0.2 nm and 1.2 nm, with a preferred range being between about 0.4 nm and 0.8 nm.
  • This oxide for the first liner 22 may he formed by using a conventional SC 1 SC 2 process, which is also known in the art as RCA clean.
  • Such steps may include fabricating and activating the sources and drains; forming silicide over sources/drains 41 and gates 42 ; processing the spacers 30 , 60 for both devices.
  • the property of interest for the spacers 30 , 60 is that they should not be penetrable by oxygen, since the spacers are to block oxygen entrance where they interface with the liners 21 , 22 .
  • the usual material used for the spacers 30 , 60 is nitride (SiN), which efficiently blocks oxygen.
  • FIG. 5 shows a schematic cross section of a stage in the processing of a CMOS structure according to an embodiment of the present invention, where oxygen exposure shifts the threshold of one type of device.
  • the oxygen exposure 101 may occur at low temperature at about 200° C. to 350° C. by furnace or rapid thermal anneal.
  • the duration of the oxygen exposure 101 may vary broadly from approximately 2 minutes to about 150 minutes.
  • For the duration of the exposure oxygen is substantially blocked by the extreme thinness of the first liner 22 from penetrating to the first gate insulator 10 , but oxygen is capable of penetrating to the second gate insulator 11 .
  • the amount of threshold shift depends on the oxygen exposure parameters, primarily on die temperature and duration of the procedure. Threshold shifts up to the range of 250 mV to 300 mV may be achieved in embodiments of the present invention.
  • the oxygen exposure does not have to affect all second type FET devices for a given chip, or processor.
  • the one does not necessarily have to implement the chemical oxide liner 22 as liners of all of the first type of FET devices on a given chip, or processor.
  • the threshold values may differ up to about 250 mV-300 mV, but often threshold differences of about 50 mV-100 mV are already of great value for some circuits. Examples of circuits that may find multiple threshold devices useful include circuits in signal processing and communication processors, and others.
  • CMOS structure After the oxygen exposure step, the CMOS structure, and its wiring into circuits may be completed with standard steps known to one skilled in the art.
  • FIG. 7 shows a symbolic view of a processor containing at least one CMOS structure incorporating an embodiment of the present invention.
  • a processor 900 has at least one chip 901 , which contains at least one CMOS structure 100 , with a FET having high-k gate dielectric, a gate comprising a metal, and a liner composed of oxide having a thickness between about 0.2 nm and 1.2 nm.
  • the processor 900 may be any processor which can benefit from embodiments of the present invention.
  • Representative embodiments of processors manufactured with embodiments of the disclosed structure are digital processors, typically found in the central processing complex of computers; mixed digital/analog processors, typically found in signal processing and communication equipment, and others.

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US11/743,101 US20080272437A1 (en) 2007-05-01 2007-05-01 Threshold Adjustment for High-K Gate Dielectric CMOS
EP08735946A EP2165359B1 (en) 2007-05-01 2008-04-08 Selective threshold voltage adjustment for high-k gate dielectric cmos
PCT/EP2008/054218 WO2008132026A1 (en) 2007-05-01 2008-04-08 Threshold adjustment for high-k gate dielectric cmos
JP2010504608A JP4917171B2 (ja) 2007-05-01 2008-04-08 高ｋゲート誘電体ｃｍｏｓのための閾値調整
CN200880014505.6A CN101675513B (zh) 2007-05-01 2008-04-08 高k栅极介电质互补金属氧化物半导体结构的阈值调整
KR1020097014372A KR20090130845A (ko) 2007-05-01 2008-04-08 하이 ｋ 게이트 유전체 ｃｍｏｓ를 위한 임계 조정
TW097116080A TW200845384A (en) 2007-05-01 2008-05-01 Threshold adjustment for high-k gate dielectric CMOS
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