US20080230823A1 - Semiconductor device and manufacturing method therefor - Google Patents

Semiconductor device and manufacturing method therefor Download PDF

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US20080230823A1
US20080230823A1 US12/045,482 US4548208A US2008230823A1 US 20080230823 A1 US20080230823 A1 US 20080230823A1 US 4548208 A US4548208 A US 4548208A US 2008230823 A1 US2008230823 A1 US 2008230823A1
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electrode
semiconductor device
forming
manufacturing
layer
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Hisao Kawasaki
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Toshiba Corp
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Toshiba Corp
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Assigned to KABUSHIKI KAISHA TOSHIBA reassignment KABUSHIKI KAISHA TOSHIBA ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KAWASAKI, HISAO
Publication of US20080230823A1 publication Critical patent/US20080230823A1/en
Priority to US13/115,251 priority Critical patent/US8587094B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0605—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8252—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes

Definitions

  • the present invention relates to a microwave monolithic integrated circuit (hereinafter, abbreviated as MMIC) using a compound semiconductor substrate and more particular to a semiconductor device having an active element and a metal-insulator-metal (hereinafter, abbreviated as MIM) capacitor and to a manufacturing method therefor.
  • MMIC microwave monolithic integrated circuit
  • MIM metal-insulator-metal
  • an active element such as a field effect transistor (hereinafter, abbreviated as an FET) and an MIM capacitor as a passive element are formed.
  • an active element such as a field effect transistor (hereinafter, abbreviated as an FET) and an MIM capacitor as a passive element are formed.
  • the active element and passive element are manufactured by different manufacturing processes.
  • a source electrode and a drain electrode composed of an ohmic metal AuGe/Au respectively are formed and a gate electrode composed of a Schottky metal Ti/Pt/Au is formed between these electrodes in an active area on a GaAs substrate.
  • a lower electrode composed of a Al or Ti/Al metal film is formed on the GaAs substrate and a dielectric layer composed of an SiN film, for example, is formed on the lower electrode.
  • the SiN film is formed also on a surface of the FET.
  • Upper electrodes are formed also on the surfaces of the source, drain and gate electrodes of the FET via contact holes formed in the SiN film.
  • the step for forming the lower electrode of the MIM capacitor is carried out as a separate step from the step for forming the FET elements.
  • the whole manufacturing steps become longer, resulting in low throughput.
  • the reason why the manufacturing steps of the two must be different from each other is that the lower electrode of the MIM capacitor and the electrodes of the PET must be formed by different metallic materials. Therefore, a semiconductor device is desired, which realizes short manufacturing steps and enhances reliability of active and passive element portions.
  • One of the objects of the present invention is to provide an element structure of the MMIC having the active element and MIM capacitor enabling a reduction in the number of the manufacturing steps of the MMIC and also to provide a manufacturing method therefor.
  • a semiconductor device including an active element having an ohmic electrode and an MIM capacitor having a dielectric layer arranged between a lower electrode and an upper electrode is provided on a semiconductor substrate, wherein the lower electrode has substantially the same structure as that of the ohmic electrode.
  • a method for manufacturing the a semiconductor device including steps of forming an active element having an ohmic electrode, forming an MIM capacitor having a dielectric layer arranged between a lower electrode and an upper electrode on the semiconductor substrate, thereby the lower electrode being manufactured simultaneously with the ohmic electrode.
  • the lower electrode of the MIM capacitor may have the same structure as that of an n-type ohmic electrode or a p-type ohmic electrode, when the active element is a PIN diode. That is, an electrode structure composed of a single layer made of the same metallic material or a plurality of laminated layers. Further, the lower electrode of the MIM capacitor may have the same structure as that of the source electrode or drain electrode of the FET when the active element is a FET.
  • the lower electrode of the MIM capacitor can be formed simultaneously with the ohmic electrode of the active element, so that the number of the manufacturing steps are reduced and the throughput is improved.
  • FIG. 1 is a schematic cross sectional view of the MMIC according to an embodiment of the present invention.
  • FIG. 2A is a diagram showing a first step of the manufacturing method for the MMIC shown in FIG. 1 .
  • FIG. 2B is a diagram showing a second step of the manufacturing method for the MMIC shown in FIG. 1 .
  • FIG. 2C is a diagram showing a third step of the manufacturing method for the MMIC shown in FIG. 1 .
  • FIG. 2D is a diagram showing a fourth step of the manufacturing method for the MMIC shown in FIG. 1 .
  • FIG. 2E is a diagram showing a fifth step of the manufacturing method for the MMIC shown in FIG. 1 .
  • FIG. 2F is a diagram showing a sixth step of the manufacturing method for the MMIC shown in FIG. 1 .
  • FIG. 2G is a diagram showing a seventh step of the manufacturing method for the MMIC shown in FIG. 1 .
  • FIG. 3 is a schematic cross sectional view of the MMIC according to a second embodiment of the present invention.
  • FIG. 4A is a diagram showing a first step of the manufacturing method of the MMIC shown in FIG. 3 .
  • FIG. 4B is a diagram showing a second step of the manufacturing method for the MMIC shown in FIG. 3 .
  • FIG. 4C is a diagram showing a third step of the manufacturing method for the MMIC shown in FIG. 3 .
  • FIG. 4D is a diagram showing a fourth step diagram of the manufacturing method for the MMIC shown in FIG. 3 .
  • FIG. 4E is a diagram showing a fifth step of the manufacturing method for the MMIC shown in FIG. 3 .
  • FIG. 4F is a diagram showing a sixth step of the manufacturing method for the MMIC shown in FIG. 3 .
  • FIG. 4G is a diagram showing a seventh step of the manufacturing method for the MMIC shown in FIG. 3 .
  • FIG. 1 The schematic cross sectional view of the MMIC according to a first embodiment is shown in FIG. 1 .
  • An MMIC 100 has a structure that an FET element portion 101 as an active element portion and an MIM capacitor portion 102 are formed on a GaAs substrate 10 which is a compound semiconductor substrate.
  • the FET element portion 101 is formed on an active layer (channel layer) 12 formed on the GaAs substrate 10 .
  • a pair of insulating films 14 a and 14 b is formed at a predetermined interval on the active layer 12 .
  • a source electrode 16 a and a drain electrode 16 b are formed on both sides of the pair of insulating films 14 a and 14 b on the active layer 12 .
  • a gate electrode 18 a is formed between the pair of insulating films 14 a and 14 b on the active layer 12 .
  • a surface protective film 20 a is provided to cover surfaces of the pair of insulating films 14 a and 14 b , gate electrode 18 a , a part of the source electrode 16 a and a part of the drain electrode 16 b .
  • Upper electrodes 22 a and 22 b are formed on portions on the source electrode 16 a and drain electrode 16 b , where is not covered by the surface protective film 20 a.
  • the MIM capacitor portion 102 is formed on an insulating film 14 c formed on the GaAs substrate 10 .
  • a lower electrode 16 c is formed in a predetermined area on the insulating film 14 c .
  • a dielectric layer 20 b is formed on the insulating film 14 c to cover the area where the lower electrode 18 b is not formed and a predetermined area of the lower electrode 16 c .
  • An upper electrode 22 c is formed on the dielectric layer 20 b so as to hold the dielectric layer 20 b between it and the lower electrode 161 c.
  • FIGS. 2A to 2H show the manufacturing steps.
  • an insulating film 14 is formed uniformly on the active layer 12 provided on the GaAs substrate 10 . Openings are formed in the insulating film at portions where the source electrode 16 a and drain electrode 16 b of the FET element portion are formed by removing the insulating film by etching. Thus, the insulating film is divided into an insulating film 14 a formed in the FET element portion and an insulating film 14 c formed in the MIM capacitor portion.
  • the insulating layer 14 is provided to separate the lower electrode 18 b of the MIM capacitor portion from the GaAs substrate 10 , so as to prevent a leak current between them and a reduction in withstand voltage. Therefore, when such a leak current does not influence the characteristics of the MMIC 100 , the insulation film 14 is not always necessary.
  • the insulating films 14 a to 14 c may be formed using the lift-off method depending on the material used for the insulating film 14 .
  • a resist film 52 is formed at portions where the area for forming the source electrode and drain electrode is opened as shown in FIG. 2B .
  • the resist film 52 is formed by coating a resist film all over the surface of the substrate 10 and then using a photolithographic technology including steps of exposing and developing using a mask pattern. Thereafter, a metal film 16 for ohmic contact is deposited over the entire surface. AuGe/Au is preferably used as a metal film 16 .
  • the resist film 52 and the metal film 16 on the resist film 52 are then removed by the lift-off method, as shown in FIG. 2C . Then, heat treatment (alloying) is performed so as to permit the metal film 16 to make ohmic contact with the active layer 12 .
  • heat treatment alloying
  • the source electrode 16 a and the drain electrode 16 b which are positioned on both sides of the insulating films 14 a and 14 b , are simultaneously formed with the lower electrode 11 c in the MIM capacitor portion.
  • the source 16 a and the drain electrode 16 b which are ohmic electrodes of the FET element portion, and the lower electrode 16 c of the MIM capacitor portion are formed simultaneously, thereby decreasing the number of the manufacturing steps.
  • the surface roughness of the lower electrode 16 c and deformation of the edge portion cause a reduction in the reliability of the MIM capacitor, so that it is preferable to maintain the shape, which used to be before the heat treatment is performed as far as possible.
  • the heat treatment temperature is preferably controlled to 400° C. or lower thereby satisfactorily keeping the shape before the heat treatment is performed. Further, the lower limit of the heat treatment temperature for alloying depends on the kind of metal composing the ohmic electrode.
  • the resist film 54 is provided, in which a portion where the gate electrode 18 a is opened.
  • exposed portion of the insulating film 14 a is removed by RIE etching, for example.
  • the metal film 18 composed by Ti/Pt/Au, for example, is deposited over the entire surface as shown in FIG. 2D .
  • the resist film 54 and the metal film 18 thereon are removed by the lift-off method, and thus the gate electrode 18 a is formed as shown in FIG. 2E .
  • the surface protective film 20 a and dielectric layer 20 can be simultaneously formed respectively on the FET element portion and MIM capacitor portion, for example, by steps of laminating an SiN film on the entire surface, forming an etching mask with a resist layer, for example, with a predetermined pattern, forming contact holes for forming the source electrode 16 a and the drain electrode 16 b of the FET element portion and a contact hole (not drawn) of the gate electrode 18 a on the SiN film by etching, and removing the etching mask.
  • the surface protective film 20 a of the FET element portion and the dielectric layer 20 b of the MIM capacitor portion can be formed simultaneously, so that the number of the manufacturing steps can be reduced.
  • a resist film 56 is coated over entire surface except for a part of the surfaces of the source electrode 16 a and drain electrode 16 b , a part (not drawn) of the surface of the gate electrode 18 a , a predetermined area of the dielectric layer 20 b on the lower electrode 16 c and a part (not drawn) of the surface of the lower electrode 16 c .
  • a metal film 22 composed of Ti/Pt/Au, for example, is deposited over the entire surface.
  • the Ti layer is formed on the dielectric layer 20 b , so that high adhesion can be obtained between them.
  • the resist film 56 and metal film 22 formed thereon are removed by the lift-off method.
  • the MMIC 100 shown in FIG. 1 is completed by forming the upper electrodes 22 a and 22 b of the drain electrode 16 a and source electrode 16 b respectively, the upper electrode (not drawn) of the gate electrode 18 a , the upper electrode 22 c and metallic wires (not drawn) connected to lower electrode 16 c of the MIM capacitor which are shown in FIG. 1 .
  • FIG. 3 the schematic cross sectional view of the MMIC according to a second embodiment is shown in FIG. 3 .
  • the PIN diode portion 101 as an active element portion and the MIM capacitor portion 102 are formed on a GaAs substrate 10 A of the semi-insulating semiconductor substrate.
  • the PIN diode portion 101 includes an n-type semiconductor layer 32 formed on the GaAs substrate 10 A, a high-resistance semiconductor layer 36 formed on the n-type semiconductor layer 32 , a p-type semiconductor layer 38 formed on the high-resistance semiconductor layer 36 , an insulating layer 40 , an n-type ohmic electrode 42 a formed on the n-type semiconductor layer 32 , a p-type ohmic electrode 44 a formed on the p-type semiconductor layer 38 , an upper electrode 48 a formed on the n-type ohmic electrode 42 a , and an upper electrode 48 b formed on the p-type ohmic electrode 44 a.
  • the MIM capacitor portion 102 includes a highly-resistant layer 34 formed on the GaAs substrate 10 A, the insulating film 40 formed on the highly-resistant layer 34 , a lower electrode 45 formed on the insulating film 40 , a dielectric layer 46 formed on the lower electrode 45 , and an upper electrode 48 c formed on the dielectric layer 46 .
  • the lower electrode 45 has a two-layer structure composed of a lower layer portion 42 b and an upper layer portion 44 b.
  • FIGS. 4A to 4G are diagrams showing manufacturing steps.
  • the n-type semiconductor layer 32 , the high-resistance semiconductor layer 36 and the p-type semiconductor layer 38 are laminated on the GaAs substrate 10 A. Unnecessary portions are removed from the high-resistance semiconductor layer 36 and the p-type semiconductor layer 38 by mesa-etching.
  • a high resistance layer 34 is formed on the n-type semiconductor layer 32 other than the PIN diode portion using an ion injection isolation method.
  • the insulating film 40 is formed on the entire surface.
  • the portions where the electrode is formed on the n-type semiconductor layer 32 and on the p-type semiconductor layer 38 are removed, for example, by the etching process using a resist film as an etching mask. Further, the insulating film 40 is formed in the MIM capacitor portion in order to prevent a leak current flowing through the lower electrode 45 and to reduce the withstand voltage of the MIM capacitor.
  • a resist film 62 is formed having openings at portions on the n-type semiconductor layer 32 and on a part of the MIM capacitor. Then a metal film 42 composed of AuGe/Au, for example, enabling ohmic contact is deposited on the entire surface. Thereafter, the resist film 62 and the metal film 42 on the resist film 42 are removed by the lift-off method as shown in FIG. 4C .
  • a resist film 64 is formed, having openings at a part of the p-type semiconductor layer 38 and at a portion where the metal film 42 of the MIM capacitor portion is formed. Then a metal film 44 composed of AuZu, for example, enabling the ohmic contact is deposited on the entire surface.
  • the resist film 64 and the metal film 44 on the resist film 64 are removed by the lift-off method as shown in FIG. 4E .
  • the heat treatment for alloying is performed so as to permit the metal films 42 and 44 to make ohmic contact with the underlying substrates.
  • the heat treatment temperature is set at 400° C. or lower, similar to the case of the MMIC 100 explained previously. Thus the reliability of the MIM capacitor can be enhanced.
  • the metal film 42 on the n-type semiconductor layer 32 is changed to the n-type ohmic electrode 42 a
  • the metal film 44 on the p-type semiconductor layer 38 is changed to the p-type ohmic electrode 44 a
  • the metal films 42 and 44 on the insulating film 40 are also changed to the lower electrode 45 of the MIM capacitor.
  • the lower electrode 45 has a two-layer structure having the lower layer portion 42 b composed of the metal film 42 and the upper layer portion 44 b composed of the metal film 44 .
  • the lower layer portion 42 b has the same structure as that of the n-type ohmic electrode 42 a
  • the upper layer portion 44 b has the same structure as that of the p-type ohmic electrode 44 a.
  • the ohmic electrodes 42 a and 44 a of the PIN diode portion and the lower electrode 45 of the MIM capacitor are thus formed simultaneously, the number of the manufacturing steps are reduced. Further, the lower electrode 45 is composed of an ohmic contact metal film of both n-type and p-type semiconductors, so that the sheet resistance of the lower electrode 45 can be lowered.
  • the heat treatment of alloying for obtaining such an ohmic electrode can be performed respectively after removal of the resist film 62 as shown in FIG. 4C and after removal of the resist film 64 as shown in FIG. 4E .
  • the first heat treatment temperature is preferably selected higher than the next heat treatment temperature. It is possible to set such heat treatment temperature by selecting the composition of the metal films 42 and 44 .
  • the lower electrode 45 is composed of only the upper layer portion 44 b which is a p-type ohmic electrode when the resist film 62 is formed to cover the lower electrode area of the MIM capacitor.
  • the lower electrode 45 is composed of only the lower layer portion 42 b which is an n-type ohmic electrode when the resist film 62 is formed to cover the metal film 42 remaining on the MIM capacitor portion.
  • Such an electrode structure can be adopted, as long as the resistance of the lower electrode 45 can be controlled to its allowable magnitude, for example, when the metal films 42 and 44 are made thicker.
  • the dielectric layer 46 composed of a SiN film is provided by forming the SiN film on the entire surface, forming an etching mask composed of a resist film having a predetermined pattern on the SiN film, forming a contact holes on the SiN film by etching and removing the etching mask.
  • the contact holes are formed on the n-type ohmic electrode 42 a , on the p-type ohmic electrode 44 a and on the lower electrode 45 for connecting a metallic wire (not drawn) to the lower electrode 45 .
  • a resist film 66 is formed having openings on the tops of the n-type ohmic electrode 42 a , the p-type ohmic electrode 44 a and on a part of the dielectric layer 46 .
  • a metal film 48 composed of Ti/Pt/Au, for example, is deposited on the entire surface via the resist film 66 .
  • the resist film 66 is removed by the lift-off method.
  • the upper electrode 48 a connected to the n-type ohmic electrode 42 a , the upper electrode 48 b connected to the p-type ohmic electrode 44 a and the upper electrode 48 c of the MIM capacitor are formed, thereby completing the MMIC 110 .
  • the ohmic electrode composing the active element and the lower electrode composing the MIM capacitor can be formed simultaneously in the MMICs 100 and 110 , so that there is no need to manufacture the active element and MIM capacitor in the different manufacturing steps from each other. Thus the number of the manufacturing steps can be reduced and the throughput is improved.
  • the present invention is not limited to the embodiments aforementioned and can be modified and executed variously within a range not deviated from the objects of the present invention.
US12/045,482 2007-03-19 2008-03-10 Semiconductor device and manufacturing method therefor Abandoned US20080230823A1 (en)

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