US20080142946A1 - Wafer level package with good cte performance - Google Patents

Wafer level package with good cte performance Download PDF

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Publication number
US20080142946A1
US20080142946A1 US11/609,970 US60997006A US2008142946A1 US 20080142946 A1 US20080142946 A1 US 20080142946A1 US 60997006 A US60997006 A US 60997006A US 2008142946 A1 US2008142946 A1 US 2008142946A1
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United States
Prior art keywords
substrate
layer
die
dielectric layer
alloy
Prior art date
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Abandoned
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US11/609,970
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English (en)
Inventor
Wen-Kun Yang
Tung-Chuan Wang
Chao-nan Chou
Chih-Wei Lin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Chip Engineering Technology Inc
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Advanced Chip Engineering Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Advanced Chip Engineering Technology Inc filed Critical Advanced Chip Engineering Technology Inc
Priority to US11/609,970 priority Critical patent/US20080142946A1/en
Assigned to ADVANCED CHIP ENGINEERING TECHNOLOGY INC. reassignment ADVANCED CHIP ENGINEERING TECHNOLOGY INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHOU, CHAO-NAN, LIN, CHIH-WEI, WANG, TUNG-CHUAN, YANG, WEN-KUN
Priority to DE102007060313A priority patent/DE102007060313A1/de
Priority to SG200718688-5A priority patent/SG144082A1/en
Priority to TW096147716A priority patent/TWI353659B/zh
Priority to CNA2007101994828A priority patent/CN101202253A/zh
Priority to KR1020070129778A priority patent/KR20080055687A/ko
Priority to JP2007322487A priority patent/JP2008153668A/ja
Priority to US12/141,138 priority patent/US7655501B2/en
Publication of US20080142946A1 publication Critical patent/US20080142946A1/en
Abandoned legal-status Critical Current

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Definitions

  • This invention relates to a structure of wafer level package (WLP), and more particularly to a wafer level package with good CTE performance.
  • WLP wafer level package
  • the device density is increased and the device dimension is reduced, continuously.
  • the demand for the packaging or interconnecting techniques in such high density devices is also increased to fit the situation mentioned above.
  • an array of solder bumps is formed on the surface of the die.
  • the formation of the solder bumps may be carried out by using a solder composite material through a solder mask for producing a desired pattern of solder bumps.
  • the function of chip package includes power distribution, signal distribution, heat dissipation, protection and support . . . and so on.
  • the traditional package technique for example lead frame package, flex package, rigid package technique, can't meet the demand of producing smaller chip with high density elements on the chip.
  • Wafer level package is to be understood as meaning that the entire packaging and all the interconnections on the wafer as well as other processing steps are carried out before the singulation (dicing) into chips (dies).
  • singulation singulation
  • WLP technique is an advanced packaging technology, by which the die are manufactured and tested on the wafer, and then singulated by dicing for assembly in a surface-mount line. Because the wafer level package technique utilizes the whole wafer as one object, not utilizing a single chip or die, therefore, before performing a scribing process, packaging and testing has been accomplished; furthermore, WLP is such an advanced technique so that the process of wire bonding, die mount and under-fill can be omitted. By utilizing WLP technique, the cost and manufacturing time can be reduced, and the resulting structure of WLP can be equal to the die; therefore, this technique can meet the demands of miniaturization of electronic devices.
  • the pads of the semiconductor die will be redistributed through redistribution processes involving a redistribution layer (RDL) into a plurality of metal pads in an area array type.
  • RDL redistribution layer
  • the build up layer will increase the size of the package. Therefore, the thickness of the package is increased. This may conflict with the demand of reducing the size of a chip.
  • the prior art suffers complicated process to form the “Panel” type package. It needs the mold tool for encapsulation and the injection of mold material. It is unlikely to control the surface of die and compound at same level due to warp after heat curing the compound, the CMP process may be needed to polish the uneven surface. The cost is therefore increased.
  • the present invention provides a FO-WLP structure with good CTE performance and shrinkage size to overcome the aforementioned problem and also provide the better board level reliability test of temperature cycling.
  • the object of the present invention is to provide a WLP with good CTE performance and shrinkage size.
  • the further object of the present invention is to provide a WLP with a substrate having die receiving cavity for shrinking the device size.
  • the further object of the present invention is to provide a dielectric layer formed on the die and the substrate and refill into a gap between the die and the substrate to absorb thermal mechanical stress there between, wherein the dielectric layer includes an elastic dielectric layer, a photosensitive layer, a silicone dielectric based layer, siloxane polymer (SINR) layer, a polyimides (PI) layer or silicone resin layer.
  • the dielectric layer includes an elastic dielectric layer, a photosensitive layer, a silicone dielectric based layer, siloxane polymer (SINR) layer, a polyimides (PI) layer or silicone resin layer.
  • the present invention provides a structure of package comprising a substrate with a pre-formed die receiving cavity formed and/or terminal contact metal pads (for FR5/BT substrate) within an upper surface of the substrate.
  • a die is disposed within the die receiving cavity by adhesion and a dielectric layer formed on the die and the substrate.
  • At least one re-distribution built up layer (RDL) is formed on the dielectric layer and coupled to the die via contact pad.
  • Connecting structure, for example, UBM is formed over the re-distribution built up layer and on the terminal contact metal pads. Terminal Conductive bumps are coupled to the UBM.
  • the dielectric layer includes an elastic dielectric layer, silicone dielectric based material, BCB or PI.
  • the silicone dielectric based material comprises siloxane polymers (SINR), Dow Corning WL-5000 series, or composites thereof.
  • the dielectric layer comprises a photosensitive layer.
  • the dielectric layer is formed on the die and the substrate and refill into a gap between the die and the substrate to absorb thermal stress there between, wherein the dielectric layer includes an elastic dielectric layer, a photosensitive layer, a siloxane polymer (SINR) layer, a polyimides (PI) layer or silicone resin layer.
  • the material of the substrate includes organic epoxy type FR4, FR5, BT (Bismaleimide Triazine epoxy), PCB (print circuit board), PI (Polyimide type), alloy or metal.
  • the alloy includes Alloy42 (42% Ni-58% Fe) or Kovar (29% Ni-17% Co-54% Fe).
  • the substrate could be glass, ceramic or silicon.
  • FIG. 1 illustrates a cross-sectional view of a structure of fan-out WLP according to the present invention.
  • FIG. 2 illustrates a cross-sectional view of a structure of fan-out WLP according to the present invention.
  • FIG. 3 illustrates a cross-sectional view of a structure of fan-out WLP according to the present invention.
  • FIG. 4 illustrates a cross-sectional view of the combination of the substrate and the tool according to the present invention.
  • FIG. 5 illustrates a top view of the combination of the substrate and the tool according to the present invention.
  • FIG. 6 illustrates a cross-sectional view of the combination of the package attached on the PCB or Mother Board according to the present invention.
  • the present invention discloses a structure of WLP utilizing a substrate having predetermined terminal contact metal pads 3 formed thereon and a pre-formed cavity 4 formed into the substrate 2 .
  • a die is disposed within the die receiving cavity by adhesion.
  • a photosensitive material is coated over the die and the pre-formed substrate.
  • the material of the photosensitive material is formed of elastic material.
  • FIG. 1 illustrates a cross-sectional view of Fan-Out Wafer Level Package (FO-WLP) in accordance with one embodiment of the present invention.
  • FO-WLP Fan-Out Wafer Level Package
  • the structure of FO-WLP includes a substrate 2 having a terminal contact metal pads 3 (for organic substrate) and die receiving cavity 4 formed therein to receive a die 6 .
  • the cavity 4 is pre-formed within the substrate 2 .
  • a cover 22 is formed under the lower surface of the substrate 2 for laser mark or protection.
  • the material includes epoxy.
  • the die 6 is disposed within the die receiving cavity 4 on the substrate 2 and fixed by an adhesion material 8 (preferably, elastic based materials).
  • adhesion material 8 preferably, elastic based materials.
  • contact pads (Bonding pads) 10 are formed on the die 6 .
  • a photosensitive layer or dielectric layer 12 is formed over the die 6 and filling into the space between the die 6 and the sidewalls of the cavity 4 .
  • Pluralities of openings are formed within the dielectric layer 12 through the lithography process or exposure and develop procedure. The pluralities of openings are aligned to the contact pads or I/O pads 10 and terminal contact metal pads 3 (refer to FIG. 2 ), respectively.
  • the RDL (re-distribution layer) 14 is formed on the dielectric layer 12 by removing (seed layers) selected portions of metal layer formed over the layer 12 , wherein the RDL 14 keeps electrically connected with the die 6 through the I/O pads 10 and terminal contact metal pads 3 , A part of the material of the RDL will re-fills into the openings in the dielectric layer 12 .
  • a protection layer 16 is formed to cover the RDL 14 .
  • Terminal pads 18 are located on the protection layer 16 and connected to the RDL 14 and terminal contact metal pads 3 of substrate.
  • a scribe line 28 is defined between the units 2 for separating each unit 2 , any there is no dielectric layer (optional).
  • the dielectric layer 12 is formed atop of the die 6 and substrate 2 and fills the space surrounding the die 6 ; due to the dielectric layer 12 is elastic property, it acts as buffer area can absorb the thermal mechanical stress between the die 6 and substrate 2 during temperature cycling.
  • the aforementioned structure constructs LGA type package.
  • An alternative embodiment can be seen in FIG. 2 , Conductive balls 20 are formed on the terminal pads 18 . This type is called BGA type. The other parts are similar to FIG. 1 , therefore, the detailed description is omitted.
  • the terminal pads 18 act as the UBM (under ball metal) under the BGA scheme.
  • Pluralities of terminal contact conductive pads 3 are formed on the upper surface of the substrate 2 and under the RDL 14 .
  • the material of the substrate 2 is organic substrate likes FR5, BT, PCB with defined cavity or Alloy42 with pre etching circuit.
  • the organic substrate with high Glass transition temperature (Tg) are epoxy type FR5 or BT (Bismaleimide triazine) type substrate.
  • the Alloy42 is composed of 42% Ni and 58% Fe.
  • Kovar can be used also, and it is composed of 29% Ni, 17% Co, 54% Fe.
  • the glass, ceramic, silicon can be used as the substrate.
  • the CTE (X/Y direction) of the epoxy type organic substrate (FR5/BT) is around 16 and the CTE of the Tool of chip redistribution around is around 5 to 8 by employing the glass materials as the tool.
  • the FR5/BT can not return to original location after the temperature cycling (near to Glass transition temperature Tg) that causes the die shift in panel form during the WLP process which needs several high temperature process.
  • Tg Glass transition temperature
  • the dielectric layers formation, the heat curing die attached materials etc., the following process steps and tool are to make sure organic substrate can keep the original location and no any warp happen during process.
  • the substrate could be round type such as wafer type, the diameter could be 200, 300 mm or higher. It could be employed for rectangular type such as panel form.
  • FIG. 3 illustrates the substrate 2 for the panel wafer form after process but before singulation. As can be seen from the drawings, the substrate 2 is pre-formed with cavities 4 . In the upper portion of FIG. 4 , the units of FIG. 1 are arranged in a matrix form. A scribe line 28 is defined between the units 2 for separating each unit 2 .
  • FIG. 4 there is no cavity 4 formed at the peripheral (edge) area 42 of the substrate 2 .
  • the lower portion of the FIG. 4 is the combination of the glass carrier tool 40 and the substrate 2 after bonding and UV curing.
  • FIG. 5 shows that the edge area of substrate 2 does not include the die cavity, the periphery area will be used for sticking the glass carrier during WLP process. The substrate will be adhered with glass carrier and it will be stuck and hold the substrate during process. After the WLP process is completed, the area indicated by the dot line will be cut from the glass carrier, it means that the inner area defined by the dot line will be performed the sawing process for package singulation.
  • the dielectric layer 12 is preferably an elastic dielectric material which is made by silicone dielectric based materials comprising siloxane polymers (SINR), Dow Corning WL5000 series, and composites thereof.
  • the dielectric layer is made by a material comprising, polyimides (PI) or silicone resin.
  • PI polyimides
  • silicone resin a material comprising, polyimides (PI) or silicone resin.
  • it is a photosensitive layer for simple process.
  • the elastic dielectric layer is a kind of material with CTE larger than 100 (ppm/° C.), elongation rate about 40 percent (preferably 30 percent-50 percent), and the hardness of the material is between plastic and rubber.
  • the thickness of the elastic dielectric layer 18 depends on the stress accumulated in the RDL/dielectric layer interface during temperature cycling test.
  • FIG. 6 it illustrates the major portions that associate with the CTE issue.
  • the silicon die CTE is 2.3) is packaged inside the package.
  • FR5 or BT organic epoxy type material CTE ⁇ 16
  • CTE is the same as the PCB or Mother Board.
  • the gap between the die and the substrate is filled with elastic materials to absorb the thermal mechanical stress due to CTE mismatching (between die and the FR5/BT).
  • the dielectric layers 12 include elastic materials to absorb the stress between the die pads and the PCB.
  • the RDL metal is Cu/Au materials and the CTE is around 16 that is the same as the PCB and organic substrate, and the UBM 18 of contact bump be located on the terminal contact metal pads 3 of substrate.
  • the metal land of PCB is Cu, the CTE of Cu is around 16 that is match to the one of PCB. From the description above, the present invention may provide excellent CTE solution for the WLP.
  • CTE matching issue under the build up layers (PCB and substrate) is solved by the present scheme and it provides better reliability (no thermal stress in X/Y direction—on board) and the elastic DL is employed to absorb the Z direction stress. Only one material (Epoxy type) is involves the singulation. The gap between chip edge and cavity sidewall can be used to fill the elastic dielectric materials to absorb the mechanical/thermal stress.
  • the material of the RDL 24 comprises Ti/Cu/Au alloy or Ti/Cu/Ni/Au alloy; the thickness of the RDL 24 is between 2 um_and — 15 um.
  • the Ti/Cu alloy is formed by sputtering technique also as seed metal layers, and the Cu/Au or CU/Ni/Au alloy is formed by electroplating; exploiting the electro-plating process to form the RDL can make the RDL thick enough to withstand CTE mismatching during temperature cycling.
  • the metal pads 20 can be Al or Cu or combination thereof. If the structure of FO-WLP utilizes SINR as the elastic dielectric layer and Cu as the RDL, according the stress analysis not shown here, the stress accumulated in the RDL/dielectric layer interface is reduced.
  • the RDL 24 fans out of the die and communicates toward the terminal pads 18 .
  • the die 6 is received within the pre-formed cavity of the substrate, thereby reducing the thickness of the package.
  • the prior art violates the rule to reduce the die package thickness.
  • the package of the present invention will be thinner than the prior art.
  • the substrate is pre-prepared before package.
  • the cavity 4 is pre-determined. Thus, the throughput will be improved than ever.
  • the present invention discloses a fan-out WLP with reduced thickness and good CTE performance.
  • the process for the present invention includes providing an alignment tool with alignment pattern formed thereon. Then, the pattern glues is printed on the tool (be used for sticking the surface of dice), followed by using pick and place fine alignment system with flip chip function to re-distribute the known good dies on the tool with desired pitch. The pattern glues will stick the chips on the tool. Subsequently, the die attached materials is printed on the die back side (preferably, the elastic based materials). Then, the panel bonder is used to bond the substrate on to die back side; the upper surface of substrate except the cavities also be stuck on the pattern glues, then vacuum curing and separate the tool with panel wafer.
  • the pattern glues is printed on the tool (be used for sticking the surface of dice), followed by using pick and place fine alignment system with flip chip function to re-distribute the known good dies on the tool with desired pitch.
  • the pattern glues will stick the chips on the tool.
  • the die attached materials is printed on the die back side (preferably, the elastic based materials). Then
  • the die bonder machine with fine alignment is employed, and the die attached materials is dispensed on the cavity of substrate.
  • the die is placed on to the cavity of substrate.
  • the die attached materials is thermally cured to ensure the die is attached on the substrate.
  • a clean up procedure is performed to clean the dice surface by wet and/or dry clean.
  • Next step is to coat the dielectric materials on the panel, followed by performing vacuum procedure to ensure there is no bubble within the panel. Subsequently, lithography process is performed to open via (contact metal pads) and Al bonding pads and/or the scribe line (optional). Plasma clean step is then executed to clean the surface of via holes and Al bonding pads.
  • Next step is to sputter Ti/Cu as seed metal layers, and then Photo Resistor (PR) is coated over the dielectric layer and seed metal layers for forming the patterns of redistributed metal layers (RDL).
  • PR Photo Resistor
  • the electro plating is processed to form Cu/Au or Cu/Ni/Au as the RDL metal, followed by stripping the PR and metal wet etching to form the RDL metal trace.
  • the next step is to coat or print the top dielectric layer and to open the contact bump via to form the UBM and/or to open the scribe line (optional).
  • the heat re-flow procedure is performed to re-flow on the substrate side (for BGA type).
  • the testing is executed.
  • Panel wafer level final testing is performed by using vertical probe card. After the testing, the substrate is sawed to singular the package into individual units. Then, the packages are respectively picked and placed the package on the tray or tape and reel.
  • the process is simple for forming Panel wafer type and is easy to control the roughness of panel surface.
  • the thickness of panel (die attached) is easy to be controlled and die shift issue will not occurs during process.
  • the injection mold tool is omitted and warp and CMP polish process will not be introduced either.
  • the substrate is pre-prepared with pre-form cavity and terminal contact metal pads (for organic substrate); the size of cavity equal to (die size+plus around 50 um to 100 um per/side; it can be used as stress buffer releasing area by filling the elastic dielectric materials to absorb the thermal stress due to the CTE difference between silicon die and substrate (FR5/BT)).
  • the packaging throughput will be increased (manufacturing cycle time was reduced) due to apply the simple build up layers on top the surface of die.
  • the terminal pads are formed on the same surface to the dice active surface.
  • the dice placement process is the same as the current process. No core paste (resin, epoxy compound, silicone rubber, etc.) filling is necessary for the present invention. CTE mismatching issue is overcome during panel form process and the deepness between die and substrate FR4 is only around ⁇ 20-30 um (act as die attached thickness), the surface level of die and substrate can be the same after the die is attached on the cavities of substrate. Only silicone dielectric material (preferably SINR) is coated on the active surface and the substrate (preferably FR45 or BT) surface. The contact pads are opened by using photo mask process only due to the dielectric layer (SINR) is photosensitive layer for opening the contacting open. Vacuum process during SINR coating is used to eliminate the bubble issue during filling the gap between die and side wall of cavity of substrate.
  • SINR silicone dielectric material
  • the die attached material is printed on the back-side of dice before substrate be bonded together with dice (chips).
  • the reliability for both package and board level is better than ever, especially, for the board level temperature cycling test, it was due to the CTE of substrate and PCB mother board are identical, hence, no thermal mechanical stress be applied on the solder bumps/balls; the previous failure mode (solder ball crack) during temperature cycling on board test were not obvious.
  • the cost is low and the process is simple. It is easy to form the combo package (dual dice package).

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  • Manufacturing & Machinery (AREA)
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US11/609,970 US20080142946A1 (en) 2006-12-13 2006-12-13 Wafer level package with good cte performance
DE102007060313A DE102007060313A1 (de) 2006-12-13 2007-12-12 Wafer Level Package (WLP) mit guter CTE-Eigenschaft und Verfahren zu deren Herstellung
SG200718688-5A SG144082A1 (en) 2006-12-13 2007-12-13 Wafer level package with good cte performance and method of the same
TW096147716A TWI353659B (en) 2006-12-13 2007-12-13 Water level package with good cte performance and
CNA2007101994828A CN101202253A (zh) 2006-12-13 2007-12-13 具有良好热膨胀系数效能的圆片级封装及其方法
KR1020070129778A KR20080055687A (ko) 2006-12-13 2007-12-13 Ｃｔｅ 특성이 양호한 웨이퍼 레벨 패키지 및 그 제조 방법
JP2007322487A JP2008153668A (ja) 2006-12-13 2007-12-13 優れたｃｔｅ性能を有するウェハレベルパッケージおよびその方法
US12/141,138 US7655501B2 (en) 2006-12-13 2008-06-18 Wafer level package with good CTE performance

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US7655501B2 (en) 2010-02-02
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