US20050116744A1 - Inverter circuit - Google Patents

Inverter circuit Download PDF

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Publication number
US20050116744A1
US20050116744A1 US10/898,364 US89836404A US2005116744A1 US 20050116744 A1 US20050116744 A1 US 20050116744A1 US 89836404 A US89836404 A US 89836404A US 2005116744 A1 US2005116744 A1 US 2005116744A1
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United States
Prior art keywords
terminal
diode
inverter circuit
voltage
voltage drive
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Abandoned
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US10/898,364
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English (en)
Inventor
Toru Iwagami
Mamoru Seo
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Publication date
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Assigned to MITSUBISHI DENKI KABUSHIKI KAISHA reassignment MITSUBISHI DENKI KABUSHIKI KAISHA ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: IWAGAMI, TORU, SEO, MAMORU
Publication of US20050116744A1 publication Critical patent/US20050116744A1/en
Priority to US12/076,575 priority Critical patent/US7683678B2/en
Priority to US12/076,580 priority patent/US7924064B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
    • H03K17/0814—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the output circuit
    • H03K17/08148—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the output circuit in composite switches
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/538—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a push-pull configuration
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S315/00—Electric lamp and discharge devices: systems
    • Y10S315/07—Starting and control circuits for gas discharge lamp using transistors

Definitions

  • the present invention relates to an inverter circuit.
  • An inverter circuit generally includes high-voltage and low-voltage switching elements connected in series between a power supply potential and a GND potential, and high-voltage and low-voltage drive circuits for respectively controlling actuation of the high-voltage and low-voltage switching elements.
  • the inverter circuit conventionally used is introduced in Japanese Patent Application Laid-Open Nos. 2003-178895, 9-219977 (1997), 10-42575 (1998), and in PCT Publication No. WO 01/59918, for example.
  • the conventional inverter circuit faces the problem below.
  • the inverter circuit At the time when the high-voltage switching element is turned off, the inverter circuit is placed in a free-wheeling mode of an FWD connected in inverse-parallel to the low-voltage switching element (FWD of the lower arm). At this time, a negative surge voltage is generated at an output terminal of the inverter circuit, which voltage is the product of di/dt during turn-off of the high-voltage switching element and an inductance in a free-wheeling loop of the FWD of the lower arm.
  • This surge voltage when being at a predetermined level or higher, may cause breakdown or malfunction of the high-voltage drive circuit. A higher switching current is likely to generate increase in surge voltage, thus causing difficulty in obtaining a large current-carrying capacity of the inverter circuit.
  • the inverter circuit includes a high-voltage switching element and a low-voltage switching element, a high-voltage drive circuit, a capacitor, a diode, and a resistor.
  • the high-voltage and low-voltage switching elements are connected in series between a power supply potential and a GND potential.
  • the high-voltage drive circuit has a terminal connected to a current emission terminal of the high-voltage switching element while supplying a reference potential of a high-potential inner circuit.
  • the terminal of the high-voltage drive circuit will be referred to as a terminal VS.
  • the diode has a series connection to the capacitor between the terminal VS and the GND potential, with such a polarity that a forward current flows from the GND potential to the terminal VS.
  • the resistor is connected in parallel either to the diode or to the capacitor, or both.
  • a negative surge voltage as a result of turn-off of the high-voltage switching element is suppressed accordingly.
  • the inverter circuit includes a high-voltage switching element and a low-voltage switching element, a high-voltage drive circuit, and a diode.
  • the high-voltage and low-voltage switching elements are connected in series between a power supply potential and a GND potential.
  • the high-voltage drive circuit has a terminal connected to the GND potential while supplying a reference potential of a low-potential inner circuit.
  • the terminal will be referred to as a terminal COM.
  • the diode is connected between the terminal COM and the GND potential, with such a polarity that a forward current flows form the terminal COM to the GND potential.
  • a negative surge voltage as a result of turn-off of the high-voltage switching element is suppressed accordingly.
  • the inverter circuit includes a high-voltage switching element and a low-voltage switching element, a high-voltage drive circuit, and a diode.
  • the high-voltage and low-voltage switching elements are connected in series between a power supply potential and a GND potential.
  • the high-voltage drive circuit has a terminal connected through a bootstrap power supply capacitor to a current emission terminal of the high-voltage switching element.
  • the terminal of the high-voltage drive circuit will be referred to as a terminal VDB.
  • the diode has a series connection to the bootstrap power supply capacitor between the current emission terminal and the terminal VDB, with such a polarity that a forward current flows from the current emission terminal to the terminal VDB.
  • a negative surge voltage as a result of turn-off of the high-voltage switching element is suppressed accordingly.
  • FIG. 1 is a circuit diagram showing the configuration of an inverter circuit according to a first preferred embodiment of the present invention
  • FIG. 2 is a circuit diagram schematically showing the configuration inside an HVIC
  • FIG. 3 is a circuit diagram corresponding to FIG. 1 , showing the configuration of an inverter circuit according to a modification of the first preferred embodiment
  • FIG. 4 is a circuit diagram showing the configuration of an inverter circuit according to a second preferred embodiment of the present invention.
  • FIG. 5 is a circuit diagram showing the configuration inside a level shift circuit of FIG. 2 when a diode is connected to a terminal COM of the HVIC;
  • FIG. 6 is a circuit diagram corresponding to FIG. 4 , showing the configuration of an inverter circuit according to a third preferred embodiment of the present invention.
  • FIG. 7 is a circuit diagram corresponding to FIG. 4 or 6 , showing the configuration of an inverter circuit according to a fourth preferred embodiment of the present invention.
  • FIG. 8 is a circuit diagram corresponding to FIG. 4 or 6 , showing the configuration of an inverter circuit according to a fifth preferred embodiment of the present invention.
  • FIG. 9 is a circuit diagram corresponding to FIG. 4 , showing a first configuration of an inverter circuit according to a sixth preferred embodiment of the present invention.
  • FIG. 10 is a circuit diagram corresponding to FIG. 6 , showing a second configuration of the inverter circuit according to the sixth preferred embodiment
  • FIG. 11 is a circuit diagram corresponding to FIG. 7 , showing a third configuration of the inverter circuit according to the sixth preferred embodiment
  • FIG. 12 is a circuit diagram corresponding to FIG. 8 , showing a fourth configuration of the inverter circuit according to the sixth preferred embodiment
  • FIG. 13 is a circuit diagram showing the configuration of an inverter circuit according to a seventh preferred embodiment of the present invention.
  • FIG. 14 is a circuit diagram showing the configuration inside the level shift circuit of FIG. 2 when a diode is connected to a terminal VDB of the HVIC.
  • FIG. 1 is a circuit diagram showing the configuration of an inverter circuit according to a first preferred embodiment of the present invention.
  • the inverter circuit is of two or more phases (generally three phases), whereas FIG. 1 shows the configuration of a single-phase circuit.
  • the configuration of FIG. 1 is an extracted portion from the inverter circuit which is mainly relevant to the present invention.
  • the inverter circuit includes a series connection of an IGBT (high-voltage switching element) 3 and an IGBT (low-voltage switching element) 4 between a power supply potential Vcc and a GND potential, and an HVIC (high-voltage drive circuit) 1 and an LVIC (low-voltage drive circuit) 2 for respectively controlling actuation of the IGBTs 3 and 4 .
  • FIG. 2 is a circuit diagram schematically showing the configuration inside the HVIC 1 .
  • the HVIC 1 includes an input circuit, a one-shot circuit, a level shift circuit, a control power reduction protective circuit, and a drive circuit.
  • the configuration inside the HVIC 1 shown in FIG. 2 is common in second through seventh preferred embodiments discussed later.
  • the HVIC 1 has terminals Vcc, PIN, COM, VDB, HO and VS.
  • the terminal Vcc receives power to drive a low-potential inner circuit of the HVIC 1 (including the input circuit and the one-short circuit shown in FIG. 2 ) from an external control power supply VD of about 15 V.
  • the terminal PIN receives an input signal from an external microcomputer.
  • the terminal COM is connected to the GND potential, and serves to supply a reference potential of the low-potential inner circuit.
  • the terminal VDB is connected through a bootstrap power supply capacitor 100 to the emitter (current emission terminal) of the IGBT 3 .
  • the terminal HO is connected to the gate of the IGBT 3 .
  • the terminal VS is connected to the emitter of the IGBT 3 , and serves to supply a reference potential of a high-potential inner circuit (including the control power reduction protective circuit and the drive circuit shown in FIG. 2 ).
  • the inverter circuit includes the bootstrap power supply capacitor 100 which is charged by the control power supply VD when the IGBT 4 is in the on state.
  • the bootstrap power supply capacitor 100 supplies HVIC 1 with power to drive the high-potential inner circuit through the terminal VDB.
  • the inverter circuit further includes a capacitor 5 , a diode 6 , and a resistor 7 .
  • the capacitor 5 is connected between the terminal VS and the GND potential.
  • the diode 6 has a series connection to the capacitor 5 between the terminal VS and the GND potential, with such a polarity that a forward current flows from the GND potential to the terminal VS.
  • the resistor 7 is connected in parallel to the capacitor 5 .
  • the IGBT 3 When the terminal PIN of the HVIC receives an on signal (high-level signal), the IGBT 3 is turned on to cause a current I 1 to flow as shown in FIG. 1 . When the terminal PIN thereafter receives an off signal (low-level signal), the IGBT 3 is turned off to cause a current 12 to flow as shown in FIG. 1 . At the instant of flow of the current 12 , a negative surge voltage is generated which is the product of di/dt during turn-off of the IGBT 3 and an inductance in bold-lined interconnection shown in FIG. 1 .
  • the inverter circuit of the first preferred embodiment is allowed to suppress a surge voltage by means of a series connection of the capacitor 5 and the diode 6 between the terminal VS and the GND potential. Further, as the first preferred embodiment prevents flow of a direct current, the inverter circuit can be constituted by the inexpensive capacitor 5 and the diode 6 .
  • the first preferred embodiment still further characteristically uses the resistor 7 to discharge electric charges stored in the capacitor 5 resulting from a surge voltage, thus advantageously preventing reduction in surge absorption by the capacitor 5 .
  • FIG. 3 is a circuit diagram corresponding to FIG. 1 , showing the configuration of an inverter circuit according to a modification of the first preferred embodiment.
  • the configuration of FIG. 1 has a parallel connection of the resistor 7 and the capacitor 5
  • an alternative configuration of FIG. 3 has a parallel connection of a resistor 8 and the diode 6 .
  • both the resistors 7 and 8 may be provided.
  • the inverter circuit shown in FIG. 3 provides the same effect as obtained by the inverter circuit of FIG. 1 .
  • FIG. 4 is a circuit diagram showing the configuration of an inverter circuit according to a second preferred embodiment of the present invention.
  • the inverter circuit is of two or more phases (generally three phases), whereas FIG. 4 shows the configuration of a single-phase circuit.
  • the configuration of FIG. 4 is an extracted portion from the inverter circuit which is mainly relevant to the present invention.
  • the inverter circuit of the second preferred embodiment includes a diode 10 as an element to suppress a surge voltage resulting from turn-off of the IGBT 3 .
  • the diode 10 is modularized as a DIP-IPM (dual-in-line package intelligent power module) 9 .
  • the diode 10 has an anode connected to the terminal COM of the HVIC 1 , and a cathode connected to a terminal 50 of the DIP-IPM 9 .
  • the diode 10 is provided between the terminal COM of the HVIC 1 and the GND potential, with such a polarity that a forward current flows from the terminal COM of the HVIC 1 to the GND potential.
  • FIG. 5 is a circuit diagram showing the configuration inside the level shift circuit of FIG. 2 when the diode 10 is connected to the terminal COM of the HVIC 1 .
  • the diode 10 serves to provide voltage clamp (reverse blocking) between the terminals COM and VDB.
  • the second preferred embodiment causes no application of a surge voltage at an excessive level between the terminals COM and VDB while preventing flow of a current, whereby the HVIC 1 is protected from breakdown or malfunction.
  • FIG. 6 is a circuit diagram corresponding to FIG. 4 , showing the configuration of an inverter circuit according to a third preferred embodiment of the present invention.
  • the usual diode 10 shown in FIG. 4 is replaced by a fast recovery diode 1 1 that is the same in polarity as the diode 10 .
  • the diode 10 continuously receives a circuit current of the HVIC 1 supplied from the control power supply VD.
  • the terminal VDB is subjected to application of the foregoing negative surge voltage (that is, when the diode 10 is reverse biased by this negative surge voltage)
  • the surge voltage is applied accordingly between the terminals COM and VDB in a recovery time of the diode 10 .
  • malfunction of the HVIC 1 is likely.
  • the usual diode 10 shown in FIG. 4 is replaced by the fast recovery diode 11 .
  • the fast recovery diode 11 requires shorter recovery time than the usual diode 10 and hence, application of the surge voltage between the terminals COM and VDB continues for a shorter length of time, whereby enhanced malfunction capability is obtained.
  • FIG. 7 is a circuit diagram corresponding to FIG. 4 or 6 , showing the configuration of an inverter circuit according to a fourth preferred embodiment of the present invention.
  • the usual diode 10 of FIG. 4 or the fast recovery diode 11 of FIG. 6 is replaced by a Zener diode 12 having a Zener voltage Vz 1 that is the same in polarity as the diode 10 or the fast recovery diode 11 .
  • the Zener voltage Vz 1 of the Zener diode 12 has such a level that the sum of the voltages VD 0 and Vz 1 is not higher than the rated voltage Vm.
  • the inverter circuit of the fourth preferred embodiment in the event of application of a surge voltage at an excessive level, the voltage between the terminals Vcc and COM of the HVIC 1 is clamped at the voltage of VD 0 +Vz 1 which is not higher than the rated voltage Vm. As a result, breakage of the HVIC 1 is prevented.
  • FIG. 8 is a circuit diagram corresponding to FIG. 4 or 6 , showing the configuration of an inverter circuit according to a fifth preferred embodiment of the present invention.
  • the inverter circuit of the fifth preferred embodiment further includes a Zener diode 13 having a Zener voltage Vz 2 in addition to the usual diode 10 of FIG. 4 or the fast recovery diode 11 of FIG. 6 .
  • the Zener diode 13 has an anode connected to the terminal COM of the HVIC 1 , and a cathode connected to the terminal Vcc of the HVIC 1 .
  • the Zener voltage Vz 2 of the Zener diode 13 has a level which is not higher than the rated voltage Vm between the terminals Vcc and COM of the HVIC 1 .
  • the inverter circuit of the fifth preferred embodiment in the event of application of a surge voltage at an excessive level, the voltage between the terminals Vcc and COM of the HVIC 1 is clamped at the Zener voltage Vz 2 which is not higher than the rated voltage Vm. As a result, breakdown of the HVIC 1 is prevented.
  • FIG. 9 is a circuit diagram corresponding to FIG. 4 , showing a first configuration of an inverter circuit according to a sixth preferred embodiment of the present invention.
  • FIG. 4 shows the single diode 10 , whereas the inverter circuit actually has a configuration of two or more phases (generally three phases).
  • the HVIC 1 and the control power supply VD are provided in each phase. That is, the diode 10 of FIG. 4 is provided responsive to the HVIC 1 in each phase.
  • the terminals COM of the HVICs 1 in the respective phases are connected to each other in a DIP-IPM 15 . That is, only one control power supply VD is required as a common control power supply among the HVICs 1 in two or more phases, thus correspondingly requiring only one diode 16 as a common diode among the HVICs 1 in two or more phases.
  • the diode 16 is provided outside the DIP-IPM 15 .
  • the diode 16 has an anode connected to a terminal 51 of the DIP-IPM 15 , and a cathode connected to the GND potential of the control power supply VD.
  • the terminal 51 is connected to the terminals COM of the HVICs 1 .
  • FIG. 10 is a circuit diagram corresponding to FIG. 6 , showing a second configuration of the inverter circuit according to the sixth preferred.
  • the inverter circuit of FIG. 10 includes only one fast recovery diode 17 as a common diode among the HVICs 1 in two or more phases that replaces the fast recovery diode 11 ( FIG. 6 ) which is provided responsive to the HVIC 1 in each phase.
  • FIG. 11 is a circuit diagram corresponding to FIG. 7 , showing a third configuration of the inverter circuit according to the sixth preferred embodiment.
  • the inverter circuit of FIG. 11 includes only one Zener diode 18 as a common diode among the HVICs 1 in two or more phases that replaces the Zener diode 12 ( FIG. 7 ) which is provided responsive to the HVIC 1 in each phase.
  • FIG. 12 is a circuit diagram corresponding to FIG. 8 , showing a fourth configuration of the inverter circuit according to the sixth preferred embodiment.
  • the inverter circuit of FIG. 12 includes only one Zener diode 19 as a common diode among the HVICs 1 in two or more phases that replaces the Zener diode 13 ( FIG. 8 ) which is provided responsive to the HVIC 1 in each phase.
  • the Zener diode 19 has an anode connected to the terminal 51 of the DIP-IPM 15 , and a cathode connected to a terminal 52 of the DIP-IPM 15 having a connection to the terminals Vcc of the HVICs 1 .
  • the inverter circuit of the sixth preferred embodiment characteristically includes the diode 16 , the fast recovery diode 17 , or the Zener diode 18 or 19 each serving as a common diode among the HVICs 1 in two or more phases. As compared with the configuration where these diodes are provided in each phase, the inverter circuit of the sixth preferred embodiment realizes simpler configuration.
  • FIG. 13 is a circuit diagram showing the configuration of an inverter circuit according to a seventh preferred embodiment of the present invention.
  • the inverter circuit is of two or more phases (generally three phases), whereas FIG. 13 shows the configuration of a single-phase circuit.
  • the configuration of FIG. 13 is an extracted portion from the inverter circuit which is mainly relevant to the present invention.
  • the inverter circuit of the seventh preferred embodiment includes a diode 21 as an element to suppress a surge voltage resulting from turn-off of the IGBT 3 .
  • the diode 21 is provided outside a DIP-IPM 20 .
  • the diode 21 has an anode connected to the bootstrap power supply capacitor 100 , and a cathode connected to a terminal 53 of the DIP-IPM 20 .
  • the terminal 53 is connected to the terminal VDB of the HVIC 1 .
  • the diode 21 thus has a series connection to the bootstrap power supply capacitor 100 between the emitter of the IGBT 3 and the terminal VDB of the HVIC 1 , with such a polarity that a forward current flows from the emitter to the terminal VDB.
  • FIG. 14 is a circuit diagram showing the configuration inside the level shift circuit of FIG. 2 when the diode 21 is connected to the terminal VDB of the HVIC 1 .

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)
  • Power Conversion In General (AREA)
US10/898,364 2003-11-28 2004-07-26 Inverter circuit Abandoned US20050116744A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US12/076,575 US7683678B2 (en) 2003-11-28 2008-03-20 Inverter circuit
US12/076,580 US7924064B2 (en) 2003-11-28 2008-03-20 Inverter circuit

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JP2003398732A JP4313658B2 (ja) 2003-11-28 2003-11-28 インバータ回路
JPJP2003-398732 2003-11-28

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US12/076,580 Division US7924064B2 (en) 2003-11-28 2008-03-20 Inverter circuit

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US12/076,575 Expired - Fee Related US7683678B2 (en) 2003-11-28 2008-03-20 Inverter circuit
US12/076,580 Expired - Fee Related US7924064B2 (en) 2003-11-28 2008-03-20 Inverter circuit

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US (3) US20050116744A1 (de)
JP (1) JP4313658B2 (de)
KR (1) KR100668097B1 (de)
CN (1) CN100449929C (de)
DE (1) DE102004057187B4 (de)
FR (1) FR2863118B1 (de)

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US9130452B2 (en) 2013-03-20 2015-09-08 Samsung Electro-Mechanics Co., Ltd. Gate driving device including plurality of gate drivers supplied with equally divided voltage and inverter having the same
US9294007B2 (en) 2012-10-04 2016-03-22 Samsung Electro-Mechanics Co., Ltd. Gate driving circuit and inverter having the same
US9425787B2 (en) 2013-11-26 2016-08-23 Samsung Electro-Mechanics Co., Ltd. Gate driving device and inverter having the same
US10857905B2 (en) * 2017-09-15 2020-12-08 Hitachi Automotive Systems, Ltd. Electronic control unit
US11909299B2 (en) 2018-07-19 2024-02-20 Mitsubishi Electric Corporation Power converting apparatus, motor driving apparatus, and air conditioner

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JP2008029163A (ja) * 2006-07-25 2008-02-07 Fuji Electric Systems Co Ltd 電圧駆動型半導体スイッチング素子の駆動回路
CN101517880B (zh) 2006-09-22 2011-12-07 松下电器产业株式会社 空调机
US8598921B2 (en) * 2006-11-22 2013-12-03 Ct-Concept Holding Gmbh Control circuit and method for controlling a power semiconductor switch
JP5251553B2 (ja) * 2009-02-02 2013-07-31 三菱電機株式会社 半導体装置
JP5503897B2 (ja) * 2009-05-08 2014-05-28 三菱電機株式会社 半導体装置
AT508993B1 (de) * 2009-10-27 2012-05-15 Felix Dipl Ing Dr Himmelstoss Ein- und mehrphasige umrichter mit der möglichkeit zur erhöhung der spannung
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KR20050052339A (ko) 2005-06-02
JP2005160268A (ja) 2005-06-16
FR2863118B1 (fr) 2007-09-14
CN100449929C (zh) 2009-01-07
US7924064B2 (en) 2011-04-12
US20080211547A1 (en) 2008-09-04
KR100668097B1 (ko) 2007-01-15
CN1622443A (zh) 2005-06-01
FR2863118A1 (fr) 2005-06-03
JP4313658B2 (ja) 2009-08-12
US20090180228A1 (en) 2009-07-16
DE102004057187B4 (de) 2014-01-23
US7683678B2 (en) 2010-03-23

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