US20040242171A1 - Transmitter circuit, transmission circuit and driver unit - Google Patents

Transmitter circuit, transmission circuit and driver unit Download PDF

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Publication number
US20040242171A1
US20040242171A1 US10/853,654 US85365404A US2004242171A1 US 20040242171 A1 US20040242171 A1 US 20040242171A1 US 85365404 A US85365404 A US 85365404A US 2004242171 A1 US2004242171 A1 US 2004242171A1
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United States
Prior art keywords
circuit
output terminal
terminal
input signal
inverting output
Prior art date
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Abandoned
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US10/853,654
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English (en)
Inventor
Akio Hosokawa
Kouichi Nishimura
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Renesas Electronics Corp
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NEC Electronics Corp
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Assigned to NEC ELECTRONICS CORPORATION reassignment NEC ELECTRONICS CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HOSOKAWA, AKIO, NISHIMURA, KOUICHI
Publication of US20040242171A1 publication Critical patent/US20040242171A1/en
Assigned to RENESAS ELECTRONICS CORPORATION reassignment RENESAS ELECTRONICS CORPORATION CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: NEC ELECTRONICS CORPORATION
Priority to US13/436,640 priority Critical patent/US8421727B2/en
Abandoned legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/153—Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant
    • H03K5/1534—Transition or edge detectors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/028—Arrangements specific to the transmitter end
    • H04L25/0286—Provision of wave shaping within the driver
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0275—Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/08—Details of image data interface between the display device controller and the data line driver circuit
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0272—Arrangements for coupling to multiple lines, e.g. for differential transmission

Definitions

  • This invention relates to a transmitter circuit, a transmission circuit and a driver unit. More particularly, the invention relates to a transmitter circuit, a transmission circuit and a driver unit applicable to a liquid crystal display device, an organic electroluminescence display device and a plasma display device.
  • a timing controller LSI chip which successively generates and outputs one horizontal line of a grayscale data signal and scanning signal from one frame of image signals
  • a source driver LSI chip which serves as a driver unit that receive the grayscale data signal and drive respective ones of data lines of a display panel, are mounted on a printed circuit board.
  • Transmission of signals between the timing controller LSI chip and the source driver LSI chip, as well as transmission of signals between the source driver LSI chips that are cascade-connected, is achieved by transmission lines consisting of printed conductor.
  • An LVDS (Low Voltage Differential Signaling) interface for example, is a high-speed interface used as the transmission circuit.
  • the conventional transmitter circuit of an LVDS interface includes a constant-current source 6 having one end connected to a high-potential power supply VDD; a constant-current source 7 having one end connected to a low-potential power supply VSS; an N-channel MOS transistor N 1 and an N-channel MOS transistor N 2 serving as switching means connected serially between the other end of the constant-current source 6 and the other end of the constant-current source 7 ; an N-channel MOS transistor N 3 and an N-channel MOS transistor N 4 serving as switching means connected serially between the other end of the constant-current source 6 and the other end of the constant-current source 7 ; a non-inverting output terminal 2 connected to the node of the N-channel MOS transistor N 1 and N-channel MOS transistor N 2 ; and an inverting output terminal 3 connected to the node of the N-channel MOS transistor N 3 and N-channel MOS transistor N 4 .
  • a terminating resistor of a receiver circuit is connected between the non-inverting output terminal 2 and inverting output terminal 3 via a pair of transmission lines, and a voltage comparator of the receiver circuit recognizes signal logic by discriminating the voltage across the terminating resistor.
  • a CMOS-level non-inverted input data signal supplied to an input terminal 1 is applied to the gate terminal of the N-channel MOS transistor N 1 and to the gate terminal of the N-channel MOS transistor N 4 .
  • An inverting input data signal which is a result of the non-inverted input data signal being inverted by the CMOS-type inverter circuit 5 , is applied to the gate terminal of the N-channel MOS transistor N 2 and to the gate terminal of the N-channel MOS transistor N 3 .
  • the N-channel MOS transistors N 1 and N 4 turn on, the N-channel MOS transistors N 2 and N 3 turn off, loop signal current flows from the constant-current source 6 to the constant-current source 7 via the N-channel MOS transistor N 1 , non-inverting output terminal 2 , transmission line, terminating resistor, transmission line, inverting output terminal 3 and N-channel MOS transistor N 4 , and the receiver circuit recognizes the logic H level.
  • the N-channel MOS transistors N 1 and N 4 turn off, the N-channel MOS transistors N 2 and N 3 turn on, loop signal current in the opposite direction flows from the constant-current source 6 to the constant-current source 7 via the N-channel MOS transistor N 3 , non-inverting output terminal 3 , transmission line, terminating resistor, transmission line, non-inverting output terminal 2 and N-channel MOS transistor N 2 , and the receiver circuit recognizes the logic L level.
  • Patent Document 1
  • the resistance component of a transmission line consisting of copper conductor on a printed circuit board is several tens of milliohms
  • the resistance component of a transmission line consisting of aluminum or copper conductor formed on a glass substrate is several hundred ohms because both the conductor thickness and conductor width are small owing to the fabrication process for the display panel.
  • the output capacitance of the transmitter circuit and the input capacitance of the receiver circuit is several picofarads.
  • an object of the present invention is to provide a transmitter circuit, a transmission circuit and a driver unit in which high-speed signal transmission can be performed by reducing blunting of the signal waveform at the input end of the receiver circuit even if the transmission line has a high resistance component as in the manner of aluminum or copper conductor on a glass substrate.
  • a transmitter circuit in accordance with one aspect of the present invention, comprising a driver circuit, which has a non-inverting output terminal and an inverting output terminal, for outputting a signal current, whose loop direction changes based upon an input signal, to the non-inverting output terminal and inverting output terminal; and an output-waveform control circuit for detecting a waveform edge of the input signal and increasing the signal current temporarily.
  • the output-waveform control circuit preferably includes an edge detecting circuit for outputting a detection signal when the edge is detected; switch means turned on by the detection signal; and a current source for supplying a current, which is added to the signal current, when the switch means has been turned on.
  • the output-waveform control circuit preferably includes a first inverter to which a non-inverted input signal is applied; a first capacitor having one end connected to an output terminal of the first inverter circuit and another end connected to the inverting output terminal; a second inverter circuit to which an inverted input signal is applied; and a second capacitor having one end connected to an output terminal of the second inverter circuit and another end connected to the non-inverting output terminal.
  • the driver circuit preferably includes a first transistor, which has a non-inverting output terminal and an inverting output terminal, to which a non-inverted input signal is applied, for switching in response and passing a current from a high-potential power supply to the non-inverting output terminal; a third transistor, to which the inverted input signal is applied, for switching in response and passing a current from the high-potential power supply to the inverting output terminal; a fourth transistor, to which the non-inverted input signal is applied, for switching in response and passing a current from the inverting output terminal to a low-potential power supply; and a second transistor, to which the inverted input signal is applied, for switching in response and passing a current from the non-inverting output terminal to the low-potential power supply.
  • a transmitter circuit in accordance with another aspect of the present invention, comprising a driver circuit, which has a non-inverting output terminal and an inverting output terminal, for outputting a differential voltage, whose polarity changes based upon an input signal, to the non-inverting output terminal and inverting output terminal; and an output-waveform control circuit for detecting a waveform edge of the input signal and increasing the differential voltage temporarily.
  • the output-waveform control circuit in the transmitter circuit preferably includes an edge detecting circuit for outputting a first detection signal when a rising edge of the waveform is detected and a second detection signal when a falling edge of the waveform is detected; switch means for pulling up the non-inverting output terminal in response to the first detection signal; switch means for pulling down the inverting output terminal in response to the first detection signal; switch means for pulling down the non-inverting output terminal in response to the second detection signal; and switch means for pulling up the inverting output terminal in response to the second detection signal.
  • the driver circuit includes a potential dividing circuit for generating high- and low-level potential-divided voltages; switch means for selecting the potential-divided voltage based upon a non-inverted input signal and outputting the voltage to the non-inverting output terminal; and switch means for selecting the potential-divided voltage based upon the non-inverted input signal and outputting the voltage to the inverting output terminal.
  • the foregoing object is attained by providing a transmission circuit comprising the above-described transmitter circuit; a transmission line having one end connected to the non-inverting output terminal and inverting output terminal of the transmitter circuit; and a receiver circuit connected to the other end of the transmission line.
  • a driver unit in accordance with another aspect of the present invention, comprising a shift register circuit to which is input grayscale data for driving data lines of a matrix display panel; and the above-described transmitter circuit connected to a serial output end of the shift register circuit.
  • the drive unit according to the present invention preferably comprises the transmission line described above.
  • the transmission line of the driver unit according to the present invention comprises a conductor on a glass substrate of the matrix display panel.
  • FIG. 1 is a circuit diagram illustrating a transmitter circuit according to a first embodiment of the present invention
  • FIG. 2 is a circuit diagram illustrating a transmission circuit having the transmitter circuit of the first embodiment
  • FIG. 3 is a diagram useful in describing the operation of the transmitter circuit of the first embodiment
  • FIG. 4 is a circuit diagram illustrating a transmitter circuit according to a second embodiment of the present invention.
  • FIG. 5 is a diagram useful in describing the operation of the transmitter circuit of the second embodiment
  • FIG. 6 is a circuit diagram illustrating a transmitter circuit according to a third embodiment of the present invention.
  • FIG. 7 is a diagram useful in describing the operation of the transmitter circuit of the third embodiment.
  • FIG. 8 is a circuit diagram illustrating a transmitter circuit according to a fourth embodiment of the present invention.
  • FIG. 9 is a block diagram of driver units according to a fifth embodiment of the present invention.
  • FIG. 10 is a diagram illustrating the structure of a matrix display panel having the driver units of the fifth embodiment.
  • FIG. 11 is a circuit diagram illustrating a transmitter circuit according to the prior art.
  • FIG. 1 is a diagram illustrating a configuration of a transmitter circuit according to a first embodiment of the present invention.
  • the transmitter circuit includes an input terminal 1 , a non-inverting output terminal 2 , an inverting output terminal 3 , a driver circuit 4 and an output-waveform control circuit 8 .
  • the driver circuit 4 includes a CMOS-type inverter circuit 5 , a constant-current source 6 for signal current source, a constant-current source 7 for signal current sink, and N-channel MOS transistors N 1 , N 2 , N 3 and N 4 .
  • One end of the constant-current source 6 is connected to a high-potential power supply VDD and the other end thereof is connected to the drain terminal of the N-channel MOS transistor N 1 and to the drain terminal of the N-channel MOS transistor N 3 .
  • One end of the constant-current source 7 is connected to a low-potential power supply VSS and the other end thereof is connected to the source terminal of the N-channel MOS transistor N 2 and to the source terminal of N-channel MOS transistor N 4 .
  • the source terminal of the N-channel MOS transistor N 1 is connected to the drain terminal of the N-channel MOS transistor N 2 and the source terminal of the N-channel MOS transistor N 3 is connected to the drain terminal of the N-channel MOS transistor N 4 .
  • the input terminal 1 is connected to the gate terminal of the N-channel MOS transistor N 1 , the gate terminal of the N-channel MOS transistor N 4 and the input terminal of the inverter circuit 5 , and the output terminal of the inverter circuit 5 is connected to the gate terminal of the N-channel MOS transistor N 2 and to the gate terminal of the N-channel MOS transistor N 3 .
  • the non-inverting output terminal 2 is connected to the source terminal of the N-channel MOS transistor N 1 and the inverting output terminal 3 is connected to the source terminal of the N-channel MOS transistor N 3 .
  • the output-waveform control circuit 8 includes an edge detecting circuit 9 , a constant-current source 12 for a signal current source, switch means 13 , a constant-current source 15 for signal current sink and switch means 16 .
  • the edge detecting circuit 9 includes a CMOS-type non-inverting buffer circuit 10 and a CMOS-type exclusive-OR gate 11 .
  • the input terminal of the non-inverting buffer circuit 10 and a first input terminal of the exclusive-OR gate 11 are tied together and connected to the input terminal 1 serving as the input terminal of the edge detecting circuit 9 .
  • the output terminal of the non-inverting buffer circuit 10 is connected to a second input terminal of the exclusive-OR gate 11 .
  • the edge detecting circuit 9 detects the rising and falling edges of the waveform of a non-inverted input data signal that is supplied to the input terminal 1 and outputs an edge detection signal EMP from the output terminal thereof.
  • the pulse width of the edge detection signal EMP is equal to the delay time of the non-inverting buffer circuit 10 , and the delay time can be set appropriately. If the non-inverting buffer circuit 10 is composed by an even-number stages of inverter circuits, then the delay time can be changed by changing the number of stages that operate.
  • the switch means 13 includes a CMOS-type inverter circuit 14 and a P-channel MOS transistor P 1 .
  • the source terminal of the P-channel MOS transistor P 1 is connected to the high-potential power supply VDD
  • the drain terminal of the P-channel MOS transistor P 1 is connected to one end of the constant-current source 12
  • the gate terminal of the P-channel MOS transistor P 1 is connected to the output terminal of the inverter circuit 14 .
  • the input terminal of the inverter circuit 14 is connected to the output terminal of the exclusive-OR gate 11 serving as the output terminal of the edge detecting circuit 9 .
  • the P-channel MOS transistor P 1 is turned on when the edge detection signal EMP at the VDD level (the logic H level) is input.
  • the other end of the constant-current source 12 serially connected to the switch means 13 is connected to the drain terminal of the N-channel MOS transistor N 1 and to the drain terminal of the N-channel MOS transistor N 3 .
  • the source of an N-channel MOS transistor N 5 serving as switch means 16 is connected to the low-potential power supply VSS, the drain of the N-channel MOS transistor N 5 is connected to one end of the constant-current source 15 and the gate terminal of the N-channel MOS transistor N 5 is connected to the output terminal of the exclusive-OR gate 11 .
  • the N-channel MOS transistor N 5 is turned on when the edge detection signal EMP at the VDD level (the logic H level) is input.
  • the other end of the constant-current source 15 serially connected to the switch means 16 is connected to the source terminal of the N-channel MOS transistor N 2 and to the source terminal of the N-channel MOS transistor N 4 .
  • FIG. 2 is a circuit diagram illustrating a transmission circuit having the transmitter circuit according to this embodiment.
  • the transmission circuit includes a transmitter circuit 43 according to this embodiment, a balanced transmission line 44 , which comprises a pair of lines, connected at one end to the non-inverting output terminal 2 and to the inverting output terminal 3 of the transmitter circuit 43 , and a receiver circuit 45 connected to the other end of the transmission line 44 .
  • the receiver circuit 45 includes a terminating resistor RL connected to the other end of the transmission line 44 , and a differential-type voltage comparator CMP having a non-inverted input terminal and an inverting input terminal connected to respective ones of the two ends of the terminating resistor RL.
  • the voltage comparator CMP recognizes signal logic by discriminating the voltage across the terminating resistor RL.
  • the transmission line 44 which comprises aluminum or copper conductor on the glass substrate of a matrix display panel, has a high resistance component.
  • the non-inverting output terminal 2 has a parasitic capacitance CO 1 with respect to the low-potential power supply VSS, the inverting output terminal 3 a parasitic capacitance CO 2 with respect to the low-potential power supply VSS, the non-inverting terminal of the receiver circuit 45 a parasitic capacitance CI 1 with respect to the low-potential power supply VSS, and the inverting terminal of the receiver circuit 45 a parasitic capacitance CI 2 with respect to the low-potential power supply VSS.
  • the CMOS-level non-inverted input data signal that enters the input terminal 1 is applied to the gate terminal of the N-channel MOS transistor N 1 and to the gate terminal of the N-channel MOS transistor N 4 .
  • An inverted input data signal which is a result of the non-inverted input data signal being inverted by the CMOS-type inverter circuit 5 , is applied to the gate terminal of the N-channel MOS transistor N 2 and to the gate terminal of the N-channel MOS transistor N 3 .
  • the N-channel MOS transistor N 1 in response to input of the non-inverted input data signal, switches to pass the current from the high-potential power supply VDD to the non-inverting output terminal 2 ;
  • the N-channel MOS transistor N 3 in response to input of the inverted input data signal, switches to pass the current from the high-potential power supply VDD to the inverting output terminal 3 ;
  • the N-channel MOS transistor N 4 in response to input of the non-inverted input data signal, switches to pass the current from the inverting output terminal 3 to the low-potential power supply VSS;
  • the N-channel MOS transistor N 2 in response to input of the non-inverted input data signal, switches to pass the current from the non-inverting output terminal 2 to the low-potential power supply VSS.
  • the non-inverted input data signal is at the VDD level serving as logic H
  • the N-channel MOS transistors N 1 and N 4 turn on
  • the N-channel MOS transistors N 2 and N 3 turn off
  • loop signal current flows from the constant-current source 6 to the constant-current source 7 via the N-channel MOS transistor N 1 , non-inverting output terminal 2 , transmission line 44 , terminating resistor RL, transmission line 44 , inverting output terminal 3 and N-channel MOS transistor N 4
  • the receiver circuit 45 recognizes the logic H level.
  • the non-inverted input data signal is at the VSS level serving as logic L
  • the N-channel MOS transistors N 1 and N 4 turn off
  • the N-channel MOS transistors N 2 and N 3 turn on
  • loop signal current in the opposite direction flows from the constant-current source 6 to the constant-current source 7 via the N-channel MOS transistor N 3 , non-inverting output terminal 3 , transmission line 44 , terminating resistor RL, transmission line 44 , non-inverting output terminal 2 and N-channel MOS transistor N 2
  • the receiver circuit recognizes the logic L level.
  • FIG. 3 is a diagram useful in describing the operation of the transmitter circuit according to the first embodiment in the transmission circuit illustrated in FIG. 2.
  • a waveform VI indicates the non-inverted input data signal applied to the input terminal 1
  • a waveform V 2 the edge detection signal EMP that is output from the output terminal of the exclusive-OR gate 11
  • a waveform V 3 the differential output voltage across the non-inverting output terminal 2 and inverting output terminal 3
  • a waveform V 4 the voltage across the terminating resistor RL
  • a waveform V 5 the voltage across the terminating resistor RL when signal transmission is performed by the prior-art transmitter circuit illustrated in FIG. 11.
  • the edge detection signal EMP remains at the VSS level (the logic L level) and the VDD-level (H-level) edge detection signal EMP is not output.
  • the non-inverted input data signal is at the VDD level (logic H level)
  • loop signal current flows from the constant-current source 6 to the constant-current source 7 via the N-channel MOS transistor N 1 , non-inverting output terminal 2 , transmission line 44 , terminating resistor RL, transmission line 44 , inverting output terminal 3 and N-channel MOS transistor N 4 .
  • the edge detecting circuit 9 detects the rising edge of the waveform of the non-inverted input data signal and outputs the edge detection signal EMP at the VDD level (the logic H level).
  • the switch means 13 turns on, the current of the constant-current source 12 is added to the current of the constant-current source 6 , the switch means 16 also turns on, the current of the constant-current source 15 is added to the current of the constant-current source 7 and the loop signal current increases.
  • the switch means 13 and 16 turn off again and the steady state is attained.
  • the differential output voltage across the non-inverting output terminal 2 and inverting output terminal 3 takes on a signal waveform whose voltage amplitude becomes large temporarily in comparison with the steady state for a period of time equivalent to the pulse width of the edge detection signal EMP measured from the timing of the rising edge of the waveform of the non-inverted input data signal.
  • the edge detecting circuit 9 detects the falling edge of the waveform of the non-inverted input data signal and outputs the edge detection signal EMP at the VDD level (the logic H level).
  • the switch means 13 turns on, the current of the constant-current source 12 is added to the current of the constant-current source 6
  • the switch means 16 also turns on, the current of the constant-current source 15 is added to the current of the constant-current source 7 and the loop signal current increases.
  • the differential output voltage across the non-inverting output terminal 2 and inverting output terminal 3 takes on a waveform whose voltage amplitude becomes large temporarily in comparison with the steady state for a period of time equivalent to the pulse width of the edge detection signal EMP measured from the timing of the falling edge of the waveform of the non-inverted input data signal.
  • the pulse width of the edge detection signal EMP is set in accordance with the relationship among the resistance value of the aluminum or copper conductor, the parasitic capacitors CO 1 , CO 2 , CI 1 and CI 2 and the current values of the constant-current source 12 and constant-current source 15 in such a manner that the voltage across the terminating resistor RL will take on an excellent waveform.
  • the transmitter circuit according to the first embodiment of the present invention is provided with the output-waveform control circuit 8 and is adapted so as to increase the output signal amplitude temporarily from the edge of the input data signal waveform.
  • the transmission line has a high resistance component as in the case of aluminum or copper conductor on a glass substrate, blunting of the signal at the input end of the receiver circuit is reduced and it becomes possible to achieve high-speed signal transmission.
  • FIG. 4 is a circuit diagram illustrating a transmitter circuit according to a second embodiment of the present invention. Structurally, the transmitter circuit according to the second embodiment of FIG. 4 differs from the transmitter circuit according to the first embodiment of FIG. 1 only in that the output-waveform control circuit 8 is modified to an output-waveform control circuit 17 .
  • the two transmitter circuits are structurally identical in all other respects. Components in FIG. 4 identical with those shown in FIG. 1 are designated by like reference characters and need not be described again.
  • the transmitter circuit according to the second embodiment includes the input terminal 1 , non-inverting output terminal 2 , inverting output terminal 3 , driver circuit 4 and output-waveform control circuit 17 .
  • the output-waveform control circuit 17 includes CMOS-type inverter circuits 18 and 20 and capacitors 19 and 21 .
  • the input terminal of the inverter circuit 20 is connected to the input terminal 1 and has the non-inverted input data signal applied thereto.
  • One end of the capacitor 21 is connected to the output terminal of the inverter circuit 20 and the other end of the capacitor 21 is connected to the inverting output terminal 3 .
  • the input terminal of the inverter circuit 18 is connected to the output terminal of the inverter circuit 5 and has the inverted input data signal applied thereto.
  • One end of the capacitor 19 is connected to the output terminal of the inverter circuit 18 and the other end of the capacitor 19 is connected to the non-inverting output terminal 2 .
  • the capacitor 21 differentiates the output voltage of the inverter circuit 20 and applies the resultant signal to the inverting output terminal 3
  • the capacitor 19 differentiates the output voltage of the inverter circuit 18 and applies the resultant signal to the non-inverting output terminal 2 .
  • FIG. 5 is a diagram useful in describing the operation of the transmitter circuit according to the second embodiment in the transmission circuit illustrated in FIG. 2.
  • the waveform VI indicates the non-inverted input data signal applied to the input terminal 1
  • a waveform V 6 the differential output voltage across the non-inverting output terminal 2 and inverting output terminal 3
  • a waveform V 7 the voltage across the terminating resistor RL.
  • loop signal current flows from the constant-current source 6 to the constant-current source 7 via the N-channel MOS transistor N 1 , non-inverting output terminal 2 , transmission line 44 , terminating resistor RL, transmission line 44 , inverting output terminal 3 and N-channel MOS transistor N 4 .
  • the non-inverted input data signal changes from the VSS level (logic L level) to the VDD level (logic H level)
  • loop signal current flows from the constant-current source 6 to the constant-current source 7 via the N-channel MOS transistor N 1 , non-inverting output terminal 2 , transmission line 44 , terminating resistor RL, transmission line 44 , inverting output terminal 3 and N-channel MOS transistor N 4 .
  • the inverter circuit 20 detects the rising edge of the waveform of the non-inverted input data signal and a voltage that is the result of differentiating the output voltage of the inverter circuit 20 by the capacitor 21 is added to the voltage at the inverting output terminal 3 .
  • the inverter circuit 18 detects the falling edge of the waveform of the inverted input data signal and a voltage that is the result of differentiating the output voltage of the inverter circuit 18 by the capacitor 19 is added to the voltage at the non-inverting output terminal 2 , whereby the loop signal current is increased. Accordingly, the differential output voltage across the non-inverting output terminal 2 and inverting output terminal 3 takes on a waveform whose voltage amplitude becomes large temporarily in comparison with the steady state from the timing of the rising edge of the waveform of the non-inverted input data signal.
  • the non-inverted input data signal changes from the VDD level (logic H level) to the VSS level (logic L level)
  • oppositely directed loop signal current flows from the constant-current source 6 to the constant-current source 7 via the N-channel MOS transistor N 3 , inverting output terminal 3 , transmission line 44 , terminating resistor RL, transmission line 44 , non-inverting output terminal 2 and N-channel MOS transistor N 2 .
  • the inverter circuit 20 detects the falling edge of the waveform of the non-inverted input data signal and a voltage that is the result of differentiating the output voltage of the inverter circuit 20 by the capacitor 21 is added to the voltage at the inverting output terminal 3 .
  • the inverter circuit 18 detects the rising edge of the waveform of the inverted input data signal and a voltage that is the result of differentiating the output voltage of the inverter circuit 18 by the capacitor 19 is added to the voltage at the non-inverting output terminal 2 , whereby the loop signal current is increased. Accordingly, the differential output voltage across the non-inverting output terminal 2 and inverting output terminal 3 takes on a waveform whose voltage amplitude becomes large temporarily in comparison with the steady state from the timing of the falling edge of the waveform of the non-inverted input data signal.
  • the capacitance values of the capacitors 19 and 21 are set in accordance with the relationship among the resistance value of the aluminum or copper conductor and the parasitic capacitors CO 1 , CO 2 , CI 1 and CI 2 (see FIG. 2) in such a manner that the voltage across the terminating resistor RL will take on an excellent waveform.
  • the voltage across the terminating resistor RL becomes an excellent waveform exhibiting rapid rise and fall that follow up well the non-inverted input data signal.
  • the edge of the waveform of the non-inverted input data signal is detected by the inverter circuit 20 and a voltage that is the result of differentiating the output voltage of the inverter circuit 20 is added to the voltage at the inverting output terminal 3 .
  • the edge of the non-inverted input data signal is detected by the inverter circuit 18 and a voltage that is the result of differentiating the output voltage of the inverter circuit 18 is added to the voltage at the non-inverting output terminal 2 . Accordingly, effects similar to these of the first embodiment are obtained by circuitry of a scale smaller than that of the transmitter circuit of the first embodiment.
  • FIG. 6 is a circuit diagram illustrating a transmitter circuit according to a third embodiment of the present invention.
  • the transmitter circuit according to the third embodiment includes the input terminal 1 , the non-inverting output terminal 2 , the inverting output terminal 3 , a driver circuit 22 and an output-waveform control circuit 36 .
  • the driver circuit 22 includes a CMOS-type inverter circuit 23 , potential dividing circuits 24 and 27 and switch means 25 , 26 , 28 and 29 .
  • the potential dividing circuit 24 has resistors R 1 , R 2 and R 3 connected serially between the high-potential power supply VDD and low-potential power supply VSS for generating a potential-divided voltage VH (high level) from the connection node of the resistors R 1 and R 2 and a potential-divided voltage VL (low level), which is lower than the potential-divided voltage VH, from the connection node of the resistors R 2 and R 3 .
  • the potential dividing circuit 27 has resistors R 4 , R 5 and R 6 connected serially between the high-potential power supply VDD and low-potential power supply VSS for generating a potential-divided voltage VH (high level) from the connection node of the resistors R 4 and R 5 and a potential-divided voltage VL (low level), which is lower than the potential-divided voltage VH, from the connection node of the resistors R 5 and R 6 .
  • the switch means 25 includes an N-channel MOS transistor N 6 and a P-channel MOS transistor P 2 and is a transfer gate obtained by connecting the source-drain line of the N-channel MOS transistor N 6 in parallel with the source-drain line of the P-channel MOS transistor P 2 .
  • the potential-divided voltage VH from the potential dividing circuit 24 is applied to one end of the switch means 25 ; the other end of the switch means 25 is connected to the non-inverting output terminal 2 .
  • the switch means 26 includes an N-channel MOS transistor N 7 and a P-channel MOS transistor P 3 and is a transfer gate obtained by connecting the source-drain line of the N-channel MOS transistor N 7 in parallel with the source-drain line of the P-channel MOS transistor P 3 .
  • the potential-divided voltage VL from the potential dividing circuit 24 is applied to one end of the switch means 26 ; the other end of the switch means 26 is connected to the non-inverting output terminal 2 .
  • the input terminal 1 is connected to the gate terminal of the N-channel MOS transistor N 6 , the gate terminal of the P-channel MOS transistor P 3 and the input terminal of the inverter circuit 23 .
  • the output terminal of the inverter circuit 23 is connected to the gate terminal of the P-channel MOS transistor P 1 and to the gate terminal of the N-channel MOS transistor N 7 .
  • the switch means 25 and 26 select the potential-divided voltage VH and output it to the non-inverting output terminal 2 when the CMOS-level non-inverted input data signal that enters the input terminal 1 is at the VDD level (the logic H level), and select the potential-divided voltage VL and output it to the non-inverting output terminal 2 when the non-inverted input data is at the VSS level (the logic L level).
  • the switch means 28 includes an N-channel MOS transistor N 8 and a P-channel MOS transistor P 4 and is a transfer gate obtained by connecting the source-drain line of the N-channel MOS transistor N 8 in parallel with the source-drain line of the P-channel MOS transistor P 4 .
  • the potential-divided voltage VH from the potential dividing circuit 27 is applied to one end of the switch means 28 ; the other end of the switch means 28 is connected to the inverting output terminal 3 .
  • the switch means 29 includes an N-channel MOS transistor N 9 and a P-channel MOS transistor P 5 and is a transfer gate obtained by connecting the source-drain line of the N-channel MOS transistor N 8 in parallel with the source-drain line of the P-channel MOS transistor P 5 .
  • the potential-divided voltage VL from the potential dividing circuit 27 is applied to one end of the switch means 29 ; the other end of the switch means 28 is connected to the inverting output terminal 3 .
  • the input terminal 1 is connected to the gate terminal of the P-channel MOS transistor P 4 and to the gate terminal of the N-channel MOS transistor N 9
  • the output terminal of the inverter circuit 23 is connected to the gate terminal of the N-channel MOS transistor N 8 and to the gate terminal of the P-channel MOS transistor P 5 .
  • the switch means 28 and 29 select the potential-divided voltage VL and output it to the inverting output terminal 3 when the CMOS-level non-inverted input data signal that enters the input terminal 1 is at the VDD level (the logic H level), and select the potential-divided voltage VH and output it to the inverting output terminal 3 when the non-inverted input data is at the VSS level (the logic L level).
  • the output-waveform control circuit 36 includes an edge detecting circuit 30 and switch means 37 , 39 , 40 and 42 .
  • the edge detecting circuit 30 includes a CMOS-type non-inverting buffer circuit 31 , a CMOS-type exclusive-OR gate 32 , a CMOS-type inverter circuit 33 and CMOS-type AND gates 34 and 35 .
  • An input terminal of the non-inverting buffer circuit 31 , a first input terminal of the exclusive-OR gate 32 , the input terminal of the inverter circuit 33 and a first input terminal of the AND gate 34 are tied together and connected to the input terminal 1 as the input terminal of the edge detecting circuit 30 .
  • the output terminal of the non-inverting buffer circuit 31 is connected to a second input terminal of the exclusive-OR gate 32 .
  • the output terminal of the exclusive-OR gate 32 is connected to a second input terminal of the AND gate 34 and to a second input terminal of the AND gate 35 .
  • the output terminal of the inverter circuit 33 is connected to a first input terminal of the AND gate 35 .
  • the edge detecting circuit 30 detects the rising edge of the waveform of the non-inverted input data signal that enters the input terminal 1 , thereby outputting the edge detection signal EMP (UP) from the output terminal of the AND gate 34 .
  • the edge detecting circuit 30 detects the falling edge of the waveform of the non-inverted input data signal, thereby outputting the edge detection signal EMP (DN) from the output terminal of the AND gate 35 .
  • the pulse width of the edge detection signals EMP (UP) and EMP (DN) is equal to the delay time of the non-inverting buffer circuit 31 .
  • This delay time can be set appropriately. If the non-inverting buffer circuit 31 is constructed from an even-number of inverter circuit stages, then the delay time can be changed by changing the number of stages that operate.
  • the switch means 37 includes a CMOS-type inverter circuit 38 and a P-channel MOS transistor P 6 .
  • the source terminal of the P-channel MOS transistor P 6 is connected to the high-potential power supply VDD
  • the drain terminal of the P-channel MOS transistor P 6 is connected to the inverting output terminal 3
  • the gate terminal of the P-channel MOS transistor P 6 is connected to the output terminal of the inverter circuit 38
  • the input terminal of the inverter circuit 38 is connected to the output terminal of the AND gate 35 .
  • the P-channel MOS transistor P 6 is turned on when the edge detection signal EMP (DN) at the VDD level (the logic H level) is input, thereby pulling up the inverting output terminal 3 toward the high-potential power supply VDD.
  • EMP edge detection signal
  • the switch means 40 includes a CMOS-type inverter circuit 41 and a P-channel MOS transistor P 7 .
  • the source terminal of the P-channel MOS transistor P 7 is connected to the high-potential power supply VDD
  • the drain terminal of the P-channel MOS transistor P 7 is connected to the non-inverting output terminal 2
  • the gate terminal of the P-channel MOS transistor P 7 is connected to the output terminal of the inverter circuit 41
  • the input terminal of the inverter circuit 41 is connected to the output terminal of the AND gate 34 .
  • the P-channel MOS transistor P 7 is turned on when the edge detection signal EMP (UP) at the VDD level (the logic H level) is input, thereby pulling up the non-inverting output terminal 2 toward the high-potential power supply VDD.
  • EMP edge detection signal
  • the source of an N-channel MOS transistor N 10 serving as switch means 39 is connected to the low-potential power supply VSS, the drain of the N-channel MOS transistor N 10 is connected to the inverting output terminal 3 , and the gate terminal of the N-channel MOS transistor N 10 is connected to the output terminal of the AND gate 34 .
  • the N-channel MOS transistor N 10 is turned on when the edge detection signal EMP (UP) at the VDD level (the logic H level) is input, thereby pulling down the inverting output terminal 3 toward the low-potential power supply VSS.
  • EMP edge detection signal
  • the source of an N-channel MOS transistor N 11 serving as switch means 42 is connected to the low-potential power supply VSS, the drain of the N-channel MOS transistor N 11 is connected to the non-inverting output terminal 2 , and the gate terminal of the N-channel MOS transistor N 11 is connected to the output terminal of the AND gate 35 .
  • the N-channel MOS transistor N 11 is turned on when the edge detection signal EMP (DN) at the VDD level (the logic H level) is input, thereby pulling down the non-inverting output terminal 2 toward the low-potential power supply VSS.
  • FIG. 7 is a diagram useful in describing the operation of the transmitter circuit according to the third embodiment in the transmission circuit illustrated in FIG. 2.
  • waveform VI indicates the non-inverted input data signal applied to the input terminal 1
  • a waveform V 8 the edge detection signal EMP (UP) that is output from the output terminal of the AND gate 34
  • a waveform V 9 the edge detection signal EMP (DN) that is output from the output terminal of the AND gate 35
  • a waveform V 11 the differential output voltage across the non-inverting output terminal 2 and inverting output terminal 3
  • a waveform V 11 the voltage across the terminating resistor RL.
  • the edge detection signal EMP (UP) and the edge detection signal EMP (DN) remain at the VSS level (the logic L level) and the VDD-level (H-level) edge detection signal EMP (UP) or edge detection signal EMP (DN) is not output.
  • the non-inverted input data signal is at the VDD level (logic H level)
  • the potential-divided voltage VH is output to the non-inverting output terminal 2 and the potential-divided voltage VL is output to the inverting output terminal 3 .
  • loop signal current flows from the non-inverting output terminal 2 to the inverting output terminal 3 via the transmission line 44 , terminating resistor RL and transmission line 44 .
  • the non-inverted input data signal is at the VSS level (logic L level)
  • the potential-divided voltage VH is output to the inverting output terminal 3
  • the potential-divided voltage VL is output to the non-inverting output terminal 2 .
  • loop signal current flows from the inverting output terminal 3 to the non-inverting output terminal 2 via the transmission line 44 , terminating resistor RL and transmission line 44 .
  • the differential output voltage across the non-inverting output terminal 2 and inverting output terminal 3 has a voltage amplitude in the steady state.
  • the edge detecting circuit 30 detects the rising edge of the waveform of the non-inverted input data signal and outputs the VDD-level (logic H level) edge detection signal EMP (UP).
  • the switch means 39 turns on and the inverting output terminal 3 is pulled down. Further, the switch means 40 also turns on and the non-inverting output terminal 2 is pulled up. Hence the differential output voltage across the non-inverting output terminal 2 and inverting output terminal 3 increases, thereby increasing the loop signal current.
  • EMP edge detection signal
  • the differential output voltage across the non-inverting output terminal 2 and inverting output terminal 3 takes on a signal waveform whose voltage amplitude becomes large temporarily in comparison with the steady state for a period of time equivalent to the pulse width of the edge detection signal EMP (UP) measured from the timing of the rising edge of the waveform of the non-inverted input data signal.
  • EMP edge detection signal
  • the non-inverted input data signal changes from the VDD level (logic H level) to the VSS level (logic L level)
  • the potential-divided voltage VH is output to the inverting output terminal 3
  • the potential-divided voltage VL is output to the non-inverting output terminal 2 .
  • loop signal current flows from the inverting output terminal 3 to the non-inverting output terminal 2 via the transmission line 44 , terminating resistor RL and transmission line 44 .
  • the edge detecting circuit 30 detects the falling edge of the waveform of the non-inverted input data signal and outputs the VDD-level (logic H level) edge detection signal EMP (DN).
  • the switch means 39 turns on and the inverting output terminal 3 is pulled up. Further, the switch means 42 also turns on and the non-inverting output terminal 2 is pulled down. Hence the differential output voltage across the non-inverting output terminal 2 and inverting output terminal 3 increases, thereby increasing the loop signal current.
  • EMP edge detection signal
  • the differential output voltage across the non-inverting output terminal 2 and inverting output terminal 3 takes on a signal waveform whose voltage amplitude becomes large temporarily in comparison with the steady state for a period of time equivalent to the pulse width of the edge detection signal EMP (DN) measured from the timing of the falling edge of the waveform of the non-inverted input data signal.
  • EMP edge detection signal
  • the pulse width of the edge detection signals EMP (UP) and EMP (DN) is set in accordance with the relationship among the resistance value of the aluminum or copper conductor, and the parasitic capacitors CO 1 , CO 2 , CI 1 and CI 2 in such a manner that the voltage across the terminating resistor RL will take on an excellent waveform.
  • the transmitter circuit according to this embodiment is of the voltage-output type, signal transmission based upon a differential voltage signal rather than a loop current can be achieved without connecting the terminating resistor RL.
  • FIG. 8 is a circuit diagram illustrating a transmitter circuit according to a fourth embodiment of the present invention.
  • the transmitter circuit according to the fourth embodiment of FIG. 8 differs from the transmitter circuit according to the third embodiment of FIG. 6 only in that the output-waveform control circuit 36 in the transmitter circuit of the third embodiment shown in FIG. 6 is replaced with the output-waveform control circuit 17 of the transmitter circuit according to the second embodiment shown in FIG. 4.
  • the two transmitter circuits are structurally identical in all other respects. Components in FIG. 8 identical with those shown in FIGS. 4 and 6 are designated by like reference characters and need not be described again.
  • the transmitter circuit according to the fourth embodiment includes the input terminal 1 , non-inverting output terminal 2 , inverting output terminal 3 , driver circuit 22 and output-waveform control circuit 17 .
  • FIG. 9 is a block diagram of driver units according to a fifth embodiment of the present invention. Specifically, two source driver LSI chips 46 serving as the driver units according to this embodiment are connected in cascade. Further, FIG. 10 is a diagram illustrating the structure of a matrix display panel having driver units according to this embodiment. As illustrated in FIG. 10, a timing controller LSI chip 51 and a plurality of source driver LSI chips 46 are mounted directly on a glass substrate 50 of a matrix display panel of a TFT liquid crystal device, organic EL display device or plasma display device. The timing controller LSI chip 51 and the source driver LSI chips 46 perform transmission of grayscale data signals, and the plurality of source driver LSI chips 46 perform transmission of grayscale data signals in cascade.
  • Transmission is via a transmission line consisting of aluminum or copper conductor formed on the glass substrate 50 by the manufacturing process of the matrix display panel. If the matrix display panel has, e.g., 1024 columns, then eight of the source driver LSI chips 46 each having 128 columns would be connected in cascade.
  • each source driver LSI chip 46 includes the transmitter circuit 43 , the receiver circuit 45 , a shift register 47 , a latch circuit 48 and a data-line driver circuit 49 .
  • the transmitter circuit 43 is any one of the transmitter circuit of the first embodiment shown in FIG. 1, the transmitter circuit of the second embodiment shown in FIG. 4, the transmitter circuit of the third embodiment shown in FIG. 6 or the transmitter circuit of the fourth embodiment shown in FIG. 8. Further, the transmitter circuit 43 , receiver circuit 45 and the transmission line 44 between the transmitter circuit 43 and the receiver circuit 45 constitute the transmission circuit shown in FIG. 2.
  • the timing controller LSI chip 51 When the timing controller LSI chip 51 stores one frame of image data in a frame memory, the timing controller LSI chip 51 successively inputs one horizontal line of grayscale data, which is for driving a data line of the matrix display panel, to cascade-connected shift registers 47 via the transmitter circuit 43 , transmission line 44 and receiver circuit 45 while applying a shift clock to each of the source driver LSI chips 46 .
  • the grayscale data When 128 columns of grayscale data is stored in the shift register 47 , the grayscale data is transferred to the latch circuit 48 in response to a control signal from the timing controller LSI chip 51 .
  • analog driving voltage corresponding to the grayscale data held in the latch circuit 48 is sent from the data-line driver circuit 49 to the data line (source line of the TFT) of the matrix display panel, whereby a display is presented.
  • the drive unit is provided with the transmitter circuit 43 connected to the serial output terminal of one shift register 47 , and the receiver circuit 45 connected to the serial input terminal of the other shift register 47 .
  • the source driver LSI chips 46 and timing controller LSI chip 51 are mounted on the glass substrate 50 of the matrix display panel and signal transmission is performed by high-resistance aluminum or copper conductor formed on the glass substrate 50 , blunting or rounding of the signal waveform at the input terminal of the receiver circuit 45 is reduced, thereby making it possible to perform high-speed transmission of a grayscale data signal.
  • driver circuit in the transmitter circuit according to the first and second embodiments relies upon N-channel MOS transistors, these can be replaced with P-channel MOS transistors.
  • the non-inverting buffer for delay in the transmitter circuit may be adapted so as to latch the non-inverted input data signal by a delay clock.
  • the effect of the present invention is that it is possible to implement a transmitter circuit, transmission circuit and driver unit in which even if a transmission line has a high resistance component, as is the case with aluminum or copper conductor formed on a glass substrate, blunting or rounding of the signal waveform at the input terminal of the receiver circuit is reduced, thereby making it possible to perform high-speed signal transmission.

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US8421727B2 (en) 2013-04-16
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CN1320758C (zh) 2007-06-06
US20120188214A1 (en) 2012-07-26
JP2004357004A (ja) 2004-12-16

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