TWM595890U - 晶片封裝構造及其電路板 - Google Patents

晶片封裝構造及其電路板 Download PDF

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TWM595890U
TWM595890U TW109201720U TW109201720U TWM595890U TW M595890 U TWM595890 U TW M595890U TW 109201720 U TW109201720 U TW 109201720U TW 109201720 U TW109201720 U TW 109201720U TW M595890 U TWM595890 U TW M595890U
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circuit
chip
circuit board
trench
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TW109201720U
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馬宇珍
黃信豪
周文復
許國賢
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頎邦科技股份有限公司
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Priority to TW109201720U priority Critical patent/TWM595890U/zh
Priority to CN202020213478.3U priority patent/CN211792240U/zh
Publication of TWM595890U publication Critical patent/TWM595890U/zh
Priority to US16/986,415 priority patent/US20210257287A1/en
Priority to JP2020003374U priority patent/JP3228842U/ja
Priority to KR2020200002919U priority patent/KR20210001929U/ko

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Abstract

一種晶片封裝構造包含一種電路板、一晶片及一填充膠，該電路板包含一載板、複數個第一線路及複數個第二線路，該載板具有一晶片設置區及一填充膠覆蓋區，各該第一線路的一第一線路段設置於該填充膠覆蓋區，各該第一線路的一內接腳及該第二線路設置於該晶片設置區，該第二線路未設置於相鄰該些第一線路的該些內接腳之間，各該內接腳及該第二線路用以接合該晶片的複數個凸塊，使相鄰的各第一線路段間具有一較大寬度的溝槽，該溝槽可供該填充膠流動，以填充至該電路板與該晶片之間，並可避免在該電路板與該晶片之間產生氣泡。

Description

晶片封裝構造及其電路板
本創作是關於一種晶片封裝構造及其電路板，尤其是一種將虛線路(dummy lead)設置於一晶片設置區的晶片封裝構造及其電路板。
由於電子產品的微小化及多功能化，使得一晶片及承載該晶片的一電路板也必須微小化，然而，當該晶片及該電路板微小化時，並不利填充於該晶片及該電路板間的一填充膠流動，尤其是該晶片設有複數個虛凸塊(dummy bump)時，該電路板也必須設有複數個虛線路(dummy lead)，以接合該些虛凸塊，在有限的電路板面積下，當該些虛線路越多時，該填充膠流動更不易流動至該晶片及該電路板間，其將造成氣泡被包覆於該晶片及該電路板間。
此外，當該些虛線路越多時，在熱壓合製程中，相鄰的虛線路或虛凸塊會因該電路板收縮或膨脹而相互接觸，而導致短路。
再者，當該些虛線路設計越多時，在形成該些虛線路及複數個非虛線路的製程後的電性測試，並無法檢測出相鄰的該些虛線路及該些非虛線路已發生橋接(bridge)現象，必須在晶片壓合至電路板後的電性測試，才能被檢測出訊號異常，相對地，造成製造成本的浪費及降低產品良率。
本創作的一種晶片封裝構造及其電路板的目的，是使位於一填充膠覆蓋區且相鄰的複數個線路間具有一較大溝槽，以利一填充膠能快速填充於一晶片與一電路板之間，避免產生氣泡被包覆於該晶片及該電路板間，且可在一熱壓合製程中，避免相鄰的線路或凸塊相互接觸而導致短路，此外，在形成線路的製程中，可避免相鄰的線路發生橋接(bridge)現象。
本創作之一種電路板包含一載板、複數個第一線路、複數個第二線路及一防焊層，該載板具有一晶片設置區及一填充膠覆蓋區，沿著一第一軸方向，該填充膠覆蓋區鄰接該晶片設置區，各該第一線路具有一內接腳及一第一線路段，該第一線路段連接該內接腳，沿著一與該第一軸方向相交的第二軸方向，該些第一線路排列設置於該載板，且相鄰的各第一線路段間具有一第一溝槽，該第一溝槽具有一第一寬度，各該第一線路的該內接腳設置於該晶片設置區，該些內接腳用以接合一晶片的複數個第一凸塊，各該第一線路的該第一線路段設置於該填充膠覆蓋區，各該第二線路設置於該晶片設置區，且各該第二線路未設置於相鄰該些第一線路的該些內接腳之間，各該第二線路用以接合該晶片的一第二凸塊，各該第二線路具有一寬度，該第一寬度不小於該寬度，該防焊層覆蓋該載板並顯露出該晶片設置區、該填充膠覆蓋區、該些內接腳、該些第一線路段、該第一溝槽及該第二線路。
本創作之一種晶片封裝構造包含上述的一電路板、一晶片及一填充膠，該晶片設置於該晶片設置區，該晶片具有複數個第一凸塊及複數個第二凸塊，該些第一凸塊接合於該些內接腳，該第二凸塊接合於該第二線路，該填充膠，填充於該載板與該晶片之間，且該填充膠覆蓋該填充膠覆蓋區及該些第一線路段。
本創作藉由各該第二線路設置於該晶片設置區，且各該第二線路未設置於相鄰該些第一線路的該些內接腳之間，使得相鄰的各第一線路段間具有一較大寬度的該第一溝槽，藉由該第一溝槽避免填出充該填充膠時，產生氣泡被包覆於該晶片及該電路板間，且藉由各該第二線路設置於該晶片設置區，避免在一熱壓合製程中，相鄰的線路或凸塊相互接觸，而發生短路情形，此外，在形成該些線路的製程中，藉由各該第二線路設置於該晶片設置區，可避免相鄰的線路發生橋接(bridge)現象。
請參閱第1及2圖，其為本創作一種電路板100的實施例，請參閱第3、4及5圖，其為本創作一種晶片封裝構造10，該晶片封裝構造10包含該電路板100、一晶片200及一填充膠300，請參閱第1及2圖，該電路板100包含一載板110、複數個第一線路120、複數個第二線路140及一防焊層150，該載板110的材料選自於聚亞醯胺(Polyimide，PI)，但不以此為限制，該載板110具有一晶片設置區111及一填充膠覆蓋區112，沿著一第一軸Y方向，該填充膠覆蓋區112鄰接該晶片設置區111，在本實施例中，該載板110具有一線路佈局區113，該線路佈局區113鄰接該填充膠覆蓋區112，且該填充膠覆蓋區112位於該晶片設置區111及該線路佈局區113之間，該防焊層150覆蓋該線路佈局區113。
請參閱第1及2圖，沿著一與該第一軸Y方向相交的第二軸X方向，該些第一線路120排列設置於該載板110，各該第一線路120具有一內接腳121及一第一線路段122，該第一線路段122連接該內接腳121，各該內接腳121設置於該晶片設置區111，各該第一線路段122設置於該填充膠覆蓋區112，請參閱第2圖，相鄰的各第一線路段122間具有一第一溝槽131，該第一溝槽131具有一第一寬度W1，較佳地，該第一寬度W1不小於5μm(微米)，相鄰的各該內接腳121間具有一第二溝槽132，該第二溝槽132連通該該第一溝槽131，該第二溝槽132具有一第二寬度W2，該第二寬度W2不小於該第一寬度W1。
請參閱第3、4及5圖，該些內接腳121用以接合該晶片200的複數個第一凸塊210，在本實施例中，各該第一線路120具有一第二線路段123及一外接腳124，該第二線路段123設置於該線路佈局區113，該防焊層150覆蓋各該第二線路段123，並顯露出各該外接腳124，該第二線路段123連接該第一線路段122，且該第一線路段122位於該內接腳121與該第二線路段123之間，該外接腳124用以接合至另一電子元件(圖未繪出)。
請參閱第1及2圖，該些第二線路140設置於該晶片設置區111，且各該第二線路140未設置於相鄰的該些內接腳121之間，在本實施例中，該第一軸Y通過該第一溝槽131及該第二線路140，使該些第一線路120與該些第二線路140間，具有較大的空間，以供該填充膠300在該電路板100與該晶片200流動，各該第二線路140用以接合該晶片200的一第二凸塊220(請參閱第3、4及5圖)，各該第二線路140具有一寬度W，且相鄰的該些第二線路140間具有一第三溝槽141，該第三溝槽141具有一第三寬度W3，該第一寬度W1不小於該寬度W，較佳地，該第二寬度W2也不小於該第二線路140的該寬度W。
由於該載板110會因材料、製程環境溫度及製程時間等條件的不同而造成膨脹或收縮，使得該第一溝槽131、該第二溝槽132及該第三溝槽141的寬度會隨著該載板110的膨脹或收縮而變寬或變窄，而造成該第一溝槽131、該第二溝槽132及該第三溝槽141的寬度無法符合規格要求，為使該第一溝槽131、該該第二溝槽132及該第三溝槽141的寬度符合規格要求，該第一溝槽131的該第一寬度W1、該第二溝槽132的該第二寬度W2及該第三溝槽141的該第三寬度W3應符合下列公式。
Figure 02_image001
且
Figure 02_image003
，其中W1為該第一寬度、A1為一第一補償值、R1為一第一預定值、C為一係數，該第一預定值為該第一溝槽131的規格要求值、該系數不大於0.001。
Figure 02_image005
且
Figure 02_image007
，其中W2為該第二寬度、A2為一第二補償值、R2為一第二預定值、C為一係數，該第二預定值為該第二溝槽132的規格要求值、該系數不大於0.001。
Figure 02_image009
且
Figure 02_image011
，其中W3為該第三寬度、A3為一第三補償值、R3為一第三預定值、C為一係數，該第三預定值為該第三溝槽141的規格要求值、該系數不大於0.001。
請參閱第3及4圖，該電路板100在一熱壓合製程中，該載板110因受熱而膨脹或收縮，藉由該補償值，使各該內接腳121及各該第二線路140能分別對接各該第一凸塊210及各該第二凸塊220，以避免該晶片200的該些第一凸塊210接合至該些內接腳121時，或該些第二凸塊220接合至該些第二線路140時產生偏移，而造成斷路或接合面積不足的情形。
請參閱第1及2圖，該防焊層150覆蓋該載板110並顯露出該晶片設置區111、該填充膠覆蓋區112、該些內接腳121、該些第一線路段122、該第一溝槽131及該第二線路140，在本實施例中，該防焊層150覆蓋該線路佈局區113、該些第二線路段123及該些外接腳124。
請參閱第3、4及5圖，該晶片封裝構造10的該晶片200設置於該晶片設置區111，該些第一凸塊210接合於該些內接腳121，該些第二凸塊220接合於該第二線路140，在本實施例中，請參閱第3及5圖，沿著該第二軸X方向，該晶片200具有一長度L，該長度L不大於42μm(微米)，各該第一凸塊210具有一厚度D，該厚度D不大於18μm(微米)，較佳地，各該第一凸塊210的該厚度D與各該第二凸塊220的一厚度實質上相同。
請參閱第5圖，該填充膠300填充於該載板110與該晶片200之間，且該填充膠300包覆該些內接腳121、該些第一凸塊210及該些第二凸塊220，且該填充膠300覆蓋該填充膠覆蓋區112及該些第一線路段122。
本創作藉由各該第二線路140設置於該晶片設置區111，且各該第二線路140未設置於相鄰該些第一線路120的該些內接腳121之間，使得相鄰的各第一線路段122間具有一較大寬度的該第一溝槽131，以在形成該些線路的製程中，避免相鄰的線路發生橋接(bridge)現象；並且可在該熱壓合製程中，避免相鄰的該些第一凸塊210或相鄰的該些第一線路120相互接觸，而發生短路情形；再者，在填充該填充膠300時，塗佈於該填充膠覆蓋區112的該填充膠300能藉由該第一溝槽131流動至該載板110與該晶片200之間，以避免產生氣泡被包覆於該晶片200及該電路板100間。
本創作之保護範圍當視後附之申請專利範圍所界定者為準，任何熟知此項技藝者，在不脫離本創作之精神和範圍內所作之任何變化與修改，均屬於本創作之保護範圍。
10:晶片封裝構造 100:電路板 110:載板 111:晶片設置區 112:填充膠覆蓋區 113:線路佈局區 120:第一線路 121:內接腳 122:第一線路段 123:第二線路段 124:外接腳 131:第一溝槽 132:第二溝槽 140:第二線路 141:第三溝槽 150:防焊層 200:晶片 210:第一凸塊 220:第二凸塊 300:填充膠 D:厚度 L:長度 W:寬度 W1:第一寬度 W2:第二寬度 W3:第三寬度 Y:第一軸 X:第二軸
第1圖：本創作的電路板的俯視圖。 第2圖：第1圖的局部放大圖。 第3圖：本創作的晶片封裝構造的俯視圖。 第4圖：第3圖的局部放大圖。 第5圖：本創作的晶片封裝構造的剖視圖。
100:電路板
110:載板
111:晶片設置區
112:填充膠覆蓋區
113:線路佈局區
120:第一線路
121:內接腳
122:第一線路段
123:第二線路段
124:外接腳
131:第一溝槽
132:第二溝槽
140:第二線路
141:第三溝槽
150:防焊層
Y:第一軸
X:第二軸

Claims (10)

  1. 一種電路板，包含： 一載板，具有一晶片設置區及一填充膠覆蓋區，沿著一第一軸方向，該填充膠覆蓋區鄰接該晶片設置區； 複數個第一線路，各該第一線路具有一內接腳及一第一線路段，該第一線路段連接該內接腳，沿著一與該第一軸方向相交的第二軸方向，該些第一線路排列設置於該載板，且相鄰的各第一線路段間具有一第一溝槽，該第一溝槽具有一第一寬度，各該第一線路的該內接腳設置於該晶片設置區，該些內接腳用以接合一晶片的複數個第一凸塊，各該第一線路的該第一線路段設置於該填充膠覆蓋區； 複數個第二線路，設置於該晶片設置區，且各該第二線路未設置於相鄰該些第一線路的該些內接腳之間，各該第二線路用以接合該晶片的一第二凸塊，各該第二線路具有一寬度，該第一寬度不小於該寬度；以及 一防焊層，覆蓋該載板，並顯露出該晶片設置區、該填充膠覆蓋區、該些內接腳、該些第一線路段、該第一溝槽及該第二線路。
  2. 如請求項1的電路板，其中相鄰的各該內接腳間具有一第二溝槽，該第二溝槽連通該該第一溝槽，該第二溝槽具有一第二寬度，該第二寬度不小於該第一寬度，且該第二寬度不小於該第二線路的該寬度。
  3. 如請求項1的電路板，其中該第一溝槽的該第一寬度符合下列公式：
    Figure 03_image001
    且
    Figure 03_image003
    其中W1為該第一寬度、A1為一第一補償值、R1為一第一預定值、C為一係數，該第一預定值為該第一溝槽的規格要求值、該系數不大於0.001。
  4. 如請求項2的電路板，其中該第二溝槽的該第二寬度符合下列公式：
    Figure 03_image005
    且
    Figure 03_image007
    其中W2為該第二寬度、A2為一第二補償值、R2為一第二預定值、C為一係數，該第二預定值為該第二溝槽的規格要求值、該系數不大於0.001。
  5. 如請求項1至4中任一項的電路板，其中相鄰的該些第二線路間具有一第三溝槽，該第三溝槽具有一第三寬度，該第三寬度符合下列公式：
    Figure 03_image009
    且
    Figure 03_image011
    其中W3為該第三寬度、A3為一第三補償值、R3為一第三預定值、C為一係數，該第三預定值為該第三溝槽的規格要求值、該系數不大於0.001。
  6. 如請求項1的電路板，其中該第一寬度不小於5μm(微米)。
  7. 如請求項1的電路板，其中該第一軸通過該第一溝槽及該第二線路。
  8. 一種晶片封裝構造，包含： 一請求項1至7中任一項的電路板； 一晶片，設置於該晶片設置區，該晶片具有複數個第一凸塊及複數個第二凸塊，該些第一凸塊接合於該些內接腳，該些第二凸塊接合於該第二線路；以及 一填充膠，填充於該載板與該晶片之間，且該填充膠覆蓋該填充膠覆蓋區及該些第一線路段。
  9. 如請求項8的晶片封裝構造，其中沿著該第二軸方向，該晶片具有一長度，該長度不大於42μm(微米)。
  10. 如請求項8或9的晶片封裝構造，其中各該第一凸塊具有一厚度，該厚度不大於18μm(微米)。
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