TWI823452B - 半導體封裝構造及其電路板 - Google Patents
半導體封裝構造及其電路板 Download PDFInfo
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Abstract
一種半導體封裝構造包含一晶片、一電路板及一填充膠,該電路板包含一載板、一圖案化金屬層及一保護層,該載板的一表面包含一線路設置區、一晶片設置區及一導流單元設置區,該晶片設置於該晶片設置區,並與該圖案化金屬層的複數個線路電性連接,該圖案化金屬層的至少一導流單元設置於該導流單元設置區,該導流單元包含一鏤空部及複數個導流槽,各該導流槽連通該鏤空部且呈輻射狀排列,該些導流槽用以引導該保護層朝向該鏤空部流動,該鏤空部及該些導流槽用以引導該填充膠朝向該保護層流動,以使該填充膠覆蓋該保護層以增加該半導體封裝構造的結構強度。
Description
本發明是關於一種半導體封裝構造及其電路板,特別是一種以輻射狀排列的導流槽引導一保護層及一填充膠的半導體封裝構造及其電路板。
請參閱第1圖,習知的一種電路板10包含一載板11、複數個線路12及一保護層13,該載板11的一表面11a包含一線路設置區11b及一晶片設置區11c,該些線路12設置於該線路設置區11b,且各該線路12的一內接腳12a位於該晶片設置區11c,該保護層13覆蓋該些線路12並顯露出該些內接腳12a,一晶片20設置於該晶片設置區11c並與該些內接腳12a電性連接,一填充膠30填充於該晶片20與該電路板10之間以構成一半導體封裝構造。
請參閱第1及2圖,在該線路設置區11b形成該保護層13覆蓋該些線路12時,該保護層13在該晶片設置區11c角隅的外側會發生溢流不足的情形,且在該填充膠30填充於該晶片20與該電路板10之間時,該填充膠30在該晶片設置區11c角隅的外側也會發生溢流不足的情形,而導致在該晶片設置區11c角隅的外側,該保護層13與該填充膠30之間會形成有一顯露該表面11a的一區域11d,當進行一剝離測試(Peeling Test)時,該區域11d會造成該填充膠30剝離該載板11,因而影響該半導體封裝構造的結構強度,且剝離該載板11的該填充膠30也會造成該些內接腳12a斷離該些線路12。
本發明的主要目的是在一載板的一晶片設置區的一角隅外側設置至少一導流單元,該導流單元的複數個導流槽呈輻射狀排列,且該些導流槽與該導流單元的一鏤空部相連通,以藉由該些導流槽引導覆蓋複數個線路的一保護層朝向該鏤空部流動,以及引導填充於該晶片與該電路板之間的一填充膠由該角隅朝向該保護層流動,並使該填充膠覆蓋位於該些導流槽的該保護層。
本發明的一種半導體封裝構造,包含一晶片、一電路板及一填充膠,該電路板包含一載板、一圖案化金屬層及一保護層,該載板具有一表面,該表面包含一線路設置區、一晶片設置區及一導流單元設置區,該線路設置區位於該晶片設置區外側,該晶片設置區的一第一邊界及一第二邊界於一角隅相交,沿著該第一邊界延伸一第一直線,沿著該第二邊界延伸一第二直線,該導流單元設置區位於該第一直線及該第二直線之間,該圖案化金屬層具有複數個線路及至少一導流單元,該些線路設置於該線路設置區,且各該線路的一內接腳位於該晶片設置區中,該導流單元設置於該導流單元設置區,該導流單元包含一鏤空部及複數個導流槽,各該導流槽連通該鏤空部且呈輻射狀排列,該鏤空部位於該角隅與該些導流槽之間,且該鏤空部相鄰該角隅,各該導流槽具有相連通的一第一導流部及一第二導流部,該第一導流部連通該鏤空部,且該第一導流部位於該鏤空部與該第二導流部之間,該保護層覆蓋該些線路,並填充於各該第二導流部,該保護層顯露出該些內接腳、該鏤空部及該些第一導流部,該晶片設置於該晶片設置區,並與該些內接腳電性連接,該填充膠填充於該晶片與該電路板之間,且該填充膠覆蓋位在該導流單元設置區的該鏤空部、該些第一導流部及位於該些第二導流部的該保護層,該保護層與該填充膠在各該第二導流部形成一第一重疊接合層。
本發明的一種半導體封裝構造的電路板包含一載板、一圖案化金屬層及一保護層,該載板具有一表面,該表面包含一線路設置區、一晶片設置區及一導流單元設置區,該線路設置區位於該晶片設置區外側,該晶片設置區用以供一晶片設置,該晶片設置區的一第一邊界及一第二邊界於一角隅相交,沿著該第一邊界延伸一第一直線,沿著該第二邊界延伸一第二直線,該導流單元設置區位於該第一直線及該第二直線之間,該圖案化金屬層具有複數個線路及至少一導流單元,該些線路設置於該線路設置區,且各該線路的一內接腳位於該晶片設置區中,各該內接腳用以與該晶片電性連接,該導流單元設置於該導流單元設置區,該導流單元包含一鏤空部及複數個導流槽,各該導流槽連通該鏤空部且呈輻射狀排列,該鏤空部位於該角隅與該些導流槽之間,且該鏤空部相鄰該角隅,各該導流槽具有相連通的一第一導流部及一第二導流部,該第一導流部連通該鏤空部,且該第一導流部位於該鏤空部與該第二導流部之間,該保護層覆蓋該些線路,並填充於各該第二導流部,該保護層顯露出該些內接腳、該鏤空部及該些第一導流部。
本發明藉由呈輻射狀排列的該些導流槽的各該第二導流部引導該保護層朝向各該第一導流部及該鏤空部流動,以及藉由該鏤空部及該些導流槽的各該第一導流部引導該填充膠由該角隅朝向各該第二導流部流動,並使該填充膠覆蓋該保護層,以使該填充膠與該保護層結合成一體,以增加該半導體封裝構造的結構強度,並可避免該填充膠剝離該載板,而造成該些內接腳斷離該些線
路。
請參閱第8及11圖,本發明的一種半導體封裝構造包含一晶片100、一電路板200及一填充膠300,請參閱第3及5圖,該電路板200包含一載板210、一圖案化金屬層220及一保護層230,該載板210具有一表面211,該表面211包含一線路設置區211a、一晶片設置區211b及一導流單元設置區211c,該線路設置區211a位於該晶片設置區211b外側,請參閱第8圖,該晶片設置區211b用以供該晶
片100設置。
請參閱第3及4圖,該晶片設置區211b的一第一邊界A及一第二邊界B於一角隅C相交,沿著該第一邊界A延伸一第一直線A1,沿著該第二邊界B延伸一第二直線B1,該導流單元設置區211c位於該第一直線A1及該第二直線B1之間,該導流單元設置區211c相鄰該線路設置區211a。
請參閱第3及4圖,該圖案化金屬層220具有複數個線路221及至少一導流單元222,該些線路221設置於該線路設置區211a,且各該線路221的一內接腳221a位於該晶片設置區211b中,各該內接腳221a用以與該晶片100電性連接,該導流單元222設置於該導流單元設置區211c,該導流單元222包含一鏤空部222a及複數個導流槽222b,各該導流槽222b連通該鏤空部222a且呈輻射狀排列,該鏤空部222a位於該角隅C與該些導流槽222b之間,且該鏤空部222a相鄰該角隅C,各該導流槽222b具有相連通的一第一導流部222b1及一第二導流部222b2,該第一導流部222b1連通該鏤空部222a,且該第一導流部222b1位於該鏤空部222a與該第二導流部222b2之間,各該第一導流部222b1具有一第一寬度W1,各該第二導流部222b2具有一第二寬度W2,該第一寬度W1實質等於該第二寬度W2。
請參閱第3及4圖,在本實施例中,該導流單元222包含複數個間隔肋222c,各該間隔肋222c由該鏤空部222a呈輻射狀排列於相鄰的各該導流槽222b之間,各該間隔肋222c具有一第一間隔部222c1及一第二間隔部222c2,各該第一間隔部222c1位於相鄰的各該第一導流部222b1之間,各該第二間隔部222c2位於相鄰的各該第二導流部222b2之間,各該間隔肋222c具有一寬度W,該寬度W由該第一間隔部222c1朝該第二間隔部222c2方向逐漸增大。
請參閱第5至7圖,該保護層230以一網版印刷製程形成於該載板
210,並覆蓋該些線路221,該保護層230之材質選自於綠漆(Solder Mask),但不以此為限,藉由該些導流槽222b的各該第二導流部222b2引導未固化前的該保護層230朝向各該第一導流部222b1及該鏤空部222a流動,並覆蓋該些第二間隔部222c2,該保護層230並填充於各該導流槽222b的該第二導流部222b2,請參閱第5圖,該保護層230顯露出該些內接腳221a、該鏤空部222a、該些第一導流部222b1及該些第一間隔部222c1,請參閱第5及6圖,沿著該第二導流部222b2朝向該第一導流部222b1方向,填充於各該第二導流部222b2的該保護層230形成一第三導流部222b3,請參閱第4、6及7圖,該第三導流部222b3連通該第一導流部222b1,各該第三導流部222b3具有一第三寬度W3,該第三寬度W3不大於該第二寬度W2。
請參閱第8圖,該晶片100設置於該晶片設置區211b,並與該些內接腳221a電性連接,請參閱第8至10圖,在一塗膠製程中,該填充膠300填充於該晶片100與該電路板200之間,在該填充膠300未固化前,藉由該鏤空部222a及該些第一導流部222b1引導該填充膠300由該角隅C朝向該些第二導流部222b2方向流動,使該填充膠300覆蓋位在該導流單元設置區211c的該鏤空部222a、該些第一導流部222b1、該些第一間隔部222c1、位於該些第二導流部222b2及該些第二間隔部222c2上的該保護層230,在本實施例中,該填充膠300經由該些第一導流部222b1覆蓋該些第三導流部222b3,該保護層230與在各該第二導流部222b2中的該填充膠300形成一第一重疊接合層S1,該保護層230與在各該第二間隔部222c2上的該填充膠300形成一第二重疊接合層S2,該第一重疊接合層S1及該第二重疊接合層S2構成該保護層230與該填充膠300的一重疊接合層S,使該填充膠300與該保護層230在該角隅C外側的該導流單元設置區211c結合成一體。
請參閱第8及11圖,本發明藉由呈輻射狀排列的該導流槽222b的各該第二導流部222b2引導該保護層230朝向各該第一導流部222b1及該鏤空部222a流動,以及藉由該鏤空部222a及該些導流槽222b的各該第一導流部222b1引導該填充膠300由該角隅C朝向各該第二導流部222b2流動,並使該填充膠300覆蓋該鏤空部222a、該些第一導流部222b1及位於該些第二導流部222b2的該保護層230及位於該些第二間隔部222c2上的該保護層230,以使該填充膠300與該保護層230結合成一體,因此進行一剝離測試(Peeling Test)時,可避免該填充膠300由該鏤空部222a剝離該載板210,而造成該些內接腳221a斷離該些線路221,且由於該填充膠300黏結於該保護層230,因此可增加該半導體封裝構造的結構強度。
本發明之保護範圍當視後附之申請專利範圍所界定者為準,任何熟知此項技藝者,在不脫離本發明之精神和範圍內所作之任何變化與修改,均屬於本發明之保護範圍。
10:電路板
11:載板
11a:表面
11b:線路設置區
11c:晶片設置區
11d:區域
12:線路
12a:內接腳
13:保護層
20:晶片
30:填充膠
100:晶片
200:電路板
210:載板
211:表面
211a:線路設置區
211b:晶片設置區
211c:導流單元設置區
220:圖案化金屬層
221:線路
221a:內接腳
222:導流單元
222a:鏤空部
222b:導流槽
222b1:第一導流部
222b2:第二導流部
222b3:第三導流部
222c:間隔肋
222c1:第一間隔部
222c2:第二間隔部
230:保護層
300:填充膠
A:第一邊界
A1:第一直線
B:第二邊界
B1:第二直線
C:角隅
S:重疊接合層
S1:第一重疊接合層
S2:第二重疊接合層
W:寬度
W1:第一寬度
W2:第二寬度
W3:第三寬度
第1圖:習知的半導體封裝構造的上視圖。
第2圖:習知的半導體封裝構造的剖視圖。
第3圖:本發明的電路板的上視圖。
第4圖:本發明的導流單元的局部放大圖。
第5圖:本發明的電路板的上視圖。
第6圖:本發明的導流單元被保護層覆蓋的剖視圖。
第7圖:沿著第6圖D-D線的剖視圖。
第8圖:本發明的半導體封裝構造的上視圖。
第9圖:本發明的導流單元被保護層及填充膠覆蓋的剖視圖。
第10圖:沿著第9圖E-E線的剖視圖。
第11圖:本發明的半導體封裝構造的剖視圖。
200:電路板
210:載板
211:表面
211a:線路設置區
211b:晶片設置區
211c:導流單元設置區
220:圖案化金屬層
221:線路
221a:內接腳
222:導流單元
222a:鏤空部
222b:導流槽
222b1:第一導流部
222b2:第二導流部
222c:間隔肋
A:第一邊界
A1:第一直線
B:第二邊界
B1:第二直線
C:角隅
Claims (16)
- 一種半導體封裝構造,包含:一晶片;一電路板,包含:一載板,具有一表面,該表面包含一線路設置區、一晶片設置區及一導流單元設置區,該線路設置區及導流單元設置區位於該晶片設置區外側,該晶片設置區的一第一邊界及一第二邊界於一角隅相交,沿著該第一邊界延伸一第一直線,沿著該第二邊界延伸一第二直線,該導流單元設置區位於該第一直線及該第二直線之間;一圖案化金屬層,具有複數個線路及至少一導流單元,該些線路設置於該線路設置區,且各該線路的一內接腳位於該晶片設置區中,該導流單元設置於該導流單元設置區,該導流單元包含一鏤空部及複數個導流槽,各該導流槽連通該鏤空部且呈輻射狀排列,該鏤空部位於該角隅與該些導流槽之間,且該鏤空部相鄰該角隅,各該導流槽具有相連通的一第一導流部及一第二導流部,該第一導流部連通該鏤空部,且該第一導流部位於該鏤空部與該第二導流部之間;及一保護層,覆蓋該些線路,並填充於各該第二導流部,該保護層顯露出該些內接腳、該鏤空部及該些第一導流部,該晶片設置於該晶片設置區,並與該些內接腳電性連接;以及一填充膠,填充於該晶片與該電路板之間,且該填充膠覆蓋位在該導流單元設置區的該鏤空部、該些第一導流部及位於該些第二導流部的該保護層,該保護層與該填充膠在各該第二導流部形成一第一重疊接合層。
- 如請求項1之半導體封裝構造,其中該導流單元包含複數個間隔 肋,各該間隔肋由該鏤空部呈輻射狀排列於相鄰的各該導流槽之間,各該間隔肋具有一第一間隔部及一第二間隔部,各該第一間隔部位於相鄰的各該第一導流部之間,各該第二間隔部位於相鄰的各該第二導流部之間,該保護層覆蓋該些第二間隔部,並顯露出該些第一間隔部。
- 如請求項2之半導體封裝構造,其中該填充膠覆蓋該些第一間隔部及位於該些第二間隔部上的該保護層,該保護層與該填充膠在各該第二間隔部上形成一第二重疊接合層,該第一重疊接合層及該第二重疊接合層構成該保護層與該填充膠的一重疊接合層。
- 如請求項1或2之半導體封裝構造,其中填充於該第二導流部的該保護層形成一第三導流部,該第三導流部連通該第一導流部,該填充膠覆蓋該些第三導流部。
- 如請求項1之半導體封裝構造,其中各該第一導流部具有一第一寬度,各該第二導流部具有一第二寬度,該第一寬度等於該第二寬度。
- 如請求項4之半導體封裝構造,其中各該第一導流部具有一第一寬度,各該第二導流部具有一第二寬度,各該第三導流部具有一第三寬度,該第三寬度不大於該第二寬度。
- 如請求項6之半導體封裝構造,其中該第一寬度等於該第二寬度。
- 如請求項2之半導體封裝構造,其中各該間隔肋具有一寬度,該寬度由該第一間隔部朝該第二間隔部方向逐漸增大。
- 一種半導體封裝構造的電路板,包含:一載板,具有一表面,該表面包含一線路設置區、一晶片設置區及一導流單元設置區,該線路設置區及導流單元設置區位於該晶片設置區外側,該晶片設置 區用以供一晶片設置,該晶片設置區的一第一邊界及一第二邊界於一角隅相交,沿著該第一邊界延伸一第一直線,沿著該第二邊界延伸一第二直線,該導流單元設置區位於該第一直線及該第二直線之間;一圖案化金屬層,具有複數個線路及至少一導流單元,該些線路設置於該線路設置區,且各該線路的一內接腳位於該晶片設置區中,各該內接腳用以與該晶片電性連接,該導流單元設置於該導流單元設置區,該導流單元包含一鏤空部及複數個導流槽,各該導流槽連通該鏤空部且呈輻射狀排列,該鏤空部位於該角隅與該些導流槽之間,且該鏤空部相鄰該角隅,各該導流槽具有相連通的一第一導流部及一第二導流部,該第一導流部連通該鏤空部,且該第一導流部位於該鏤空部與該第二導流部之間;及一保護層,覆蓋該些線路,並填充於各該第二導流部,該保護層顯露出該些內接腳、該鏤空部及該些第一導流部,該鏤空部及該些第一導流部用以引導填充於該晶片與該電路板之間的一填充膠由該角隅朝向該些第二導流部方向流動,使該填充膠覆蓋位在該導流單元設置區的該鏤空部、該些第一導流部、位於該些第二導流部上的該保護層。
- 如請求項9之半導體封裝構造的電路板,其中該導流單元包含複數個間隔肋,各該間隔肋由該鏤空部呈輻射狀排列於相鄰的各該導流槽之間,各該間隔肋具有一第一間隔部及一第二間隔部,各該第一間隔部位於相鄰的各該第一導流部之間,各該第二間隔部位於相鄰的各該第二導流部之間,該保護層覆蓋該些第二間隔部並顯露出該些第一間隔部。
- 如請求項10之半導體封裝構造的電路板,其中位於該些第二間隔部上的該保護層及該些第一間隔部用以供一填充膠覆蓋。
- 如請求項9或10之半導體封裝構造的電路板,其中填充於該第二導流部的該保護層形成一第三導流部,該第三導流部連通該第一導流部,該些第三導流部用以供一填充膠覆蓋。
- 如請求項9之半導體封裝構造的電路板,其中各該第一導流部具有一第一寬度,各該第二導流部具有一第二寬度,該第一寬度等於該第二寬度。
- 如請求項12之半導體封裝構造的電路板,其中各該第一導流部具有一第一寬度,各該第二導流部具有一第二寬度,各該第三導流部具有一第三寬度,該第三寬度不大於該第二寬度。
- 如請求項14之半導體封裝構造的電路板,其中該第一寬度等於該第二寬度。
- 如請求項10之半導體封裝構造的電路板,其中各該間隔肋具有一寬度,該寬度由該第一間隔部朝該第二間隔部方向逐漸增大。
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- 2022-07-18 CN CN202210843436.1A patent/CN117374015A/zh active Pending
-
2023
- 2023-05-02 JP JP2023076285A patent/JP2024006975A/ja active Pending
- 2023-05-04 US US18/143,133 patent/US20240008171A1/en active Pending
- 2023-05-08 KR KR1020230058987A patent/KR20240002906A/ko unknown
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102709198A (zh) * | 2011-03-28 | 2012-10-03 | 华东科技股份有限公司 | 防止基板周边外露的模封阵列处理方法 |
TW201421619A (zh) * | 2012-11-21 | 2014-06-01 | Powertech Technology Inc | 防止爬膠污染之覆晶接合結構 |
TW201943032A (zh) * | 2018-04-03 | 2019-11-01 | 南茂科技股份有限公司 | 半導體封裝結構及其製造方法 |
TWM624524U (zh) * | 2021-11-23 | 2022-03-11 | 頎邦科技股份有限公司 | 半導體封裝構造 |
Also Published As
Publication number | Publication date |
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CN117374015A (zh) | 2024-01-09 |
KR20240002906A (ko) | 2024-01-08 |
JP2024006975A (ja) | 2024-01-17 |
TW202404427A (zh) | 2024-01-16 |
US20240008171A1 (en) | 2024-01-04 |
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