TWI807272B - 具有鈹摻雜的肖特基接觸層的空乏型高電子遷移率場效電晶體（ｈｅｍｔ）半導體裝置 - Google Patents
具有鈹摻雜的肖特基接觸層的空乏型高電子遷移率場效電晶體（ｈｅｍｔ）半導體裝置 Download PDFInfo
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Abstract
一種半導體裝置，具有基板，基板上的一對III族-氮化物層形成：在該對III族-氮化物層中的下層中具有二維電子氣(2DEG)通道的異質接面；在該對III族-氮化物層的上層上的蓋帽鈹摻雜的III族-氮化物層；以及與鈹摻雜的III族-氮化物層的蓋帽的部分肖特基接觸中的電性接觸。
Description
本揭露大體而言涉及空乏型高電子遷移場效電晶體(High Electron Mobile Field Effect Transistor；HEMT)半導體裝置，更具體地涉及具有肖特基接觸層的空乏型HEMT半導體裝置。
如本領域中已知的，基於例如GaN、AlGaN、InN、AlN及ScAlN的III族-氮化物材料的有源半導體裝置，例如二極體及FET(場效電晶體)，最近表現出優異的RF/微波性能，藉由最佳化材料、製程、裝置和設計技術實現，舉例而言，參見GaN-Based Schottky Diode by Yaqi Wang,http：//dx.doi.org/10.5772/intechopen.77024(2017年11月27日提交、2018年4月5日審核、2018年9月12日發
布)。
為這些半導體裝置增加肖特基障壁高度的先前嘗試是引入介電絕緣體，例如氮化矽或氧化矽、氮化鋁或氧化鋁，以及各種其他介電膜，以形成MIS(金屬-絕緣體-半導體)FET。這種MIS方法在絕緣膜與半導體之間的表面狀態方面存在問題。更具體地，這些表面狀態俘獲載體並導致FET的不穩定操作。
據報導，InGaAs肖特基二極體上的薄P型InGaAs層會增加肖特基障壁高度(P.Kordo
et al.,Schottky barrier height enhancement on n-In0.53Ga0.47As,J.Appl.Phys.72,2347(1992))。還有報導指出，在AlGaN/GaN HEMT上摻雜鎂(Mg)的5nm P型GaN蓋帽層提高電晶體擊穿電壓並且降低電流散射(Li et al.,Device Characteristics of AlGaN/GaN HEMTs with p-GaN Cap Layer,ECS Journal of Solid State Science and Technology,6(11)S3125-S3128(2017))。雖然已經有報導鎂摻雜的P型GaN蓋帽裝置，但鎂的使用會在沉積系統中產生記憶效應，這會使未來的生長面臨因鎂雜質摻入程度增加的風險。鎂摻雜是唯一被報導用於GaN的P型摻雜劑。
依據本揭露，提供一種半導體裝置，包括：一對堆疊的III族-氮化物半導體層，該對堆疊的III族-氮化物半導體層形成異質接面，具有2DEG通道形成在該對堆
疊的III族-氮化物層中的下層中；源極電極設置在該對堆疊的III族-氮化物層中的上層之上；汲極電極設置在該對堆疊的III族-氮化物層中的上層之上；鈹摻雜的III族-氮化物材料的蓋帽層設置在該對堆疊的III族-氮化物層中的上層上，此摻雜的III族-氮化物材料的蓋帽層從該源極電極的歐姆接觸區域延伸到該汲極電極的歐姆接觸區域；閘極電極與摻雜的III族-氮化物材料的該蓋帽層肖特基接觸並且設置在該源極電極與該汲極電極之間。因此，摻雜的III族-氮化物層的蓋帽層也用作肖特基接觸層。
在一實施例中，鈹III族-氮化物材料的蓋帽層是鈹摻雜氮化鎵。
在一實施例中，提供一種半導體結構，包括：基板；在該基板上的一對III族-氮化物層形成：在該對III族-氮化物層中的下層中具有二維電子氣(2 Dimensional Electron Gas；2DEG)通道的異質接面；以及在該對III族-氮化物層的上層上的鈹摻雜的III族-氮化物蓋帽層；以及與具有在1nm與10nm之間的厚度的該鈹摻雜的III族-氮化物蓋帽層的部分肖特基接觸的電性觸點。
在一實施例中，鈹的摻雜濃度在從1×1016/cm3到5×1019/cm3的範圍內。
發明人已經認識到，略高肖特基障壁的好處，同時維持負臨界值電壓(空乏型模式)，可以藉由保持鈹摻雜III族-氮化物蓋帽層(Be：GaN)很薄來實現，因為沒有人嘗試建立增強模式HEMT，如在2019年4月9日提交、轉讓給
與本發明相同的受讓人的美國共同未決專利申請案(序號16/379,077，發明人Hwang等，發明名稱"SEMICONDUCTOR STRUCTURE HAVING BOTH ENHANCEMENT MODE GROUP III-N HIGH ELECTRON MOBILITY TRANSISTORS AND DEPLETION MODE GROUP III-N HIGH ELECTRON MOBILITY TRANSISTORS")中所述，在此藉由引用併入，障壁層與通道層之間的極化錯置沒有上限。
發明人認識到不需要P型導電性來提高肖特基障壁高度，而是需要能夠位移費米能階的表面針孔以改變有效肖特基障壁高度，如可以用受體陷阱狀態完成，因此使用鈹作為III族-氮化物的摻雜物；在III族-氮化物生長中，鈹是一種比鎂更易於製程使用的摻雜物。更具體地，在一實施例中，發明人藉由實驗發現具有5×1018/cm3的摻雜濃度的鈹可以將GaN的電阻率從100Ohm-cm(未摻雜的GaN)增加到2.2×103Ohm-cm(鈹摻雜的GaN)。
此外，發明人已經認識到，藉由MBE在GaN中摻雜鈹可以達到5×1019/cm3，而不會在材料中產生額外的缺陷和混亂，最終導致結構裂化。低於1×1016/cm3的摻雜程度在位移能帶結構以實現增強的肖特基障壁高度方面變得效率差。此外，鈹的蒸氣壓使得鈹在用於MBE生長後不會產生不希望的背景摻雜或腔室記憶效應。發明人藉由實驗發現，藉由MBE在一些空乏型模式AlGaN/GaN HEMT上生長的5×1018/cm3鈹摻雜GaN的25nm蓋帽層可以將能帶結構修改為產生增強模式HEMT，表明鈹摻雜可以有效地
在GaN中產生受體能階狀態。
發明人已經認識到，用作GaN(Be：GaN)的受體能階摻雜物的鈹在高溫下穩定，舉例而言，高達至少900攝氏度，在生長和加工步驟中都是穩定的。具有鈹摻雜物的GaN層的電阻率增加，這與鎂摻雜的GaN不同，後者電阻率降低並觀察到P型導電性。藉由在二極體和FET的III族-氮化物材料結構的頂部生長厚度為1nm至10nm的鈹摻雜的III族-氮化物蓋帽層，這種鈹摻雜的GaN提供了一種傑出的材料，用於增加二極體和FET的有效肖特基障壁高度。鈹摻雜蓋帽層增加了肖特基障壁高度。增加的障壁高度提供許多益處，包含：1.減少閘極漏電流；2.提高擊穿電壓；3.提高二極體和FET的可靠性。此外，此層用作表面鈍化以改善RF裝置中的電流散射。
更進一步地，發明人已經認識到，在III族-氮化物HEMT的表面上添加摻雜的III族-氮化物蓋帽層無助於增加III族-氮化物HEMT的2DEG中的極化感應電荷。III族-氮化物HEMT由一對堆疊的III族-氮化物層形成。這對堆疊的III族-氮化物層中的下層是通道層，而這對堆疊的III族-氮化物層中的上層是障壁層。一對堆疊的III族-氮化物層形成異質接面，異質接面處的極化錯置導致在通道層中形成2DEG。障壁層可以由一或多個III族-氮化物層形成，使得障壁層中的III族-氮化物層以某種方式有助於在異質接面處建立極化錯置。III族-氮化物蓋帽層可以是與障壁層直接接觸的一或多個III族-氮化物半導體層。III族-
氮化物蓋帽層中的材料不像障壁層中的III族-氮化物材料那樣有助於極化錯置的增加，而是III族-氮化物蓋帽層材料改善了表面鈍化、洩漏和散射。
更進一步地，發明人已經認識到，在本文中，在空乏型HEMT之上的薄鈹摻雜的III族-氮化物蓋帽層的目的是增加具有空乏型HEMT的閘極接觸的肖特基障壁高度。空乏型HEMT障壁層上方的鈹摻雜III族-氮化物蓋帽層的厚度應小於障壁層厚度的四分之一，以維持空乏型HEMT的2DEG中的電荷密度。
本揭露的一或多個實施例的細節將在以下描述及伴隨的圖式中闡述。根據說明書、圖式以及申請專利範圍，本揭露的其他特徵、目的和優點將是顯而易見的。
10:半導體結構
12:空乏型高電子遷移率場效電晶體
18:單晶基板
20:層
22:層
23:2DEG
24:層
25:蓋帽層
26:源極電極
27:歐姆接觸區域
28:汲極電極
29:歐姆接觸區域
34:閘極電極
40:能帶能量圖
42:傳導帶能量曲線
44:垂直能量軸
46:水平距離軸
48:障壁距離範圍
50:距離
52:虛線
54:陰影區域
70:能帶能量圖
72:傳導帶能量曲線
74:障壁蓋帽距離範圍
△
78:正向增加
[圖1]為根據本揭露的半導體裝置的截面示意圖；[圖2A]是根據先前技術的半導體裝置的能帶能量圖的示意圖；以及[圖2B]是根據本揭露的半導體裝置的能帶能量圖的示意圖。
各圖式中相似的參考符號指示相似的元件。
依據參考圖1，圖1所示的半導體結構10具有
空乏型(D型)場效電晶體12，在此是D型HEMT。如圖所示，D型HEMT 12包含源極電極26、汲極電極28和設置在源極電極26與汲極電極28之間的閘極電極34。
更具體地，半導體結構10包含單晶基板18，在此例如是碳化矽(SiC)，和外延生長的III族-氮化物結構，在此是外延生長的III族-氮化物結構半導體層20、22、24堆疊；層20是一或多個外延生長的III族-氮化物材料，形成HEMT結構的成核和緩衝區，層22是外延生長的未摻雜的III族-氮化物通道材料，具有電阻率低於層20材料，這裡例如GaN，以及層24是一或多個外延生長的III族-氮化物障壁材料，這裡例如AlGaN。這對堆疊的III族-氮化物半導體層22和24與GaN通道層22中的2DEG(由虛線23指示)通道形成異質接面。在AlGaN障壁層24上形成鈹摻雜的III族-氮化物蓋帽層25，這裡是鈹摻雜的GaN蓋帽層25。需注意，GaN蓋帽層25從源極電極26的歐姆接觸區域27延伸到汲極電極28的歐姆接觸區域29。閘極電極34與鈹摻雜的III族-氮化物蓋帽層25肖特基接觸。還需注意，源極電極26和汲極電極28與GaN通道層22歐姆接觸。歐姆接觸區域27和29可以藉由金屬接觸的熱退火或藉由半導體再生長製程形成，並在2DEG 23與源極和汲極電極26和28之間提供歐姆接觸。歐姆接觸區域27和29可以藉由各種方法來實現，由此在形成層25和24之前沒有、部分或全部移除層25和24。
更具體地，在以任何常規方式形成具有基板
18和層20、22、24的結構之後，在AlGaN障壁層24的表面上沉積鈹摻雜的III族-氮化物蓋帽層25。在此，鈹摻雜的III族-氮化物蓋帽層25中的III族-氮化物材料是GaN。舉例而言，在此使用分子束外延裝備沉積1nm至10nm的鈹摻雜GaN，從而沉積單晶、外延生長的Be：GaN層；鈹摻雜的III族-氮化物蓋帽層25，如圖所示。Be：GaN蓋帽層的厚度必須維持在肖特基閘極觸點下方1nm到10nm之間，以防止夾斷電壓和跨導顯著降低並影響微波裝置的RF性能，並防止空穴氣體在Be：GaN蓋帽層中形成。
需注意，在本文中，在空乏型HEMT之上的鈹摻雜的III族-氮化物蓋帽層的目的是增加具有空乏型HEMT的閘極接觸的肖特基障壁高度。空乏型HEMT障壁層上方的鈹摻雜III族-氮化物蓋帽層的厚度應小於障壁層厚度的四分之一，以維持空乏型HEMT的2DEG中的電荷密度。
這裡，在此實施例中，鈹在GaN中的摻雜濃度為5×1018/cm3，並且發明人藉由實驗發現將GaN的電阻率從未摻雜的GaN為100Ohm-cm到鈹摻雜的GaN為2.2×103Ohm-cm。接著用開口遮蔽蓋帽層25的表面以暴露Be：GaN蓋帽層25的將要形成源極電極26和汲極電極28的部分。合適的蝕刻劑，例如氯基乾電漿蝕刻，用於蝕刻Be：GaN蓋帽層25和10nm的AlGaN障壁層24。接著使用金屬合金和熱退火以任何常規方式形成源極電極26和汲極電極28與通道層22中的2DEG歐姆接觸。如圖所示，在形成源極電極
和汲極電極26和28之後，閘極電極34形成為與Be：GaN蓋帽層25肖特基接觸。
現在參考圖2A，能帶能量圖40示出AlGaN/GaN HEMT傳導帶能量曲線42，對於其中Be：GaN蓋帽層25為0nm的結構10。傳導帶能量是沿著垂直能量軸44和水平距離軸46繪製的，水平距離軸46描繪了結構10的表面下方的距離。水平距離軸46從0開始，其對應於AlGaN III族-氮化物障壁層24的表面，並且表示隨著其向右增加而在表面下方更深的位置。位置X表示AlGaN III族-氮化物障壁層24和GaN通道層22之間的介面的位置。對應於AlGaN III族-氮化物障壁層24的傳導帶能量曲線42的部分繪製在從0到X延伸的障壁距離範圍48之上。對應於GaN通道層22的傳導帶能量曲線42的部分繪製在緩衝距離範圍內，50對應於大於X的距離。虛線52代表費米能量，陰影區域54代表當傳導帶能量曲線42低於虛線52時在AlGaN III族-氮化物障壁層24與GaN通道層22之間的介面處形成的2DEG通道。有效肖特基障壁高度被定義為表面與2DEG之間的傳導帶能量曲線42的最高能量點，或就水平軸上的距離而言，在0和X之間。符號
56代表能帶能量圖40中有效肖特基障壁高度的能階。
現在參考圖2B，第二能帶能量圖70示出Be：GaN/AlGaN/GaN HEMT傳導帶能量曲線72，對於帶有Be：GaN蓋帽層25的結構10。傳導帶能量是沿著垂直能量軸44和水平距離軸46繪製的，水平距離軸46描繪了結構10
的表面下方的距離。水平距離軸46從0開始，其對應於鈹摻雜的GaN蓋帽層25的表面，並且表示隨著其向右增加而在表面下方更深的位置。位置Y表示鈹摻雜的GaN蓋帽層25與AlGaN III族-氮化物障壁層24之間的介面的位置。位置X+Y表示AlGaN III族-氮化物障壁層24與GaN通道層22之間的介面的位置。對應於鈹摻雜的GaN蓋帽層25的傳導帶能量曲線72的部分繪製延伸從0到Y的障壁蓋帽距離範圍74上。對應於AlGaN III族-氮化物障壁層24的傳導帶能量曲線72的部分繪製在從Y到X+Y延伸的障壁距離範圍48之上。對應於GaN通道層22的傳導帶能量曲線42的部分繪製在緩衝距離範圍內，50對應於大於X+Y的距離。有效肖特基障壁高度被定義為傳導帶能量曲線42的最高能量點，在表面與2DEG之間，或根據水平軸上的距離，在0和X+Y之間。
由GaN中的鈹摻雜產生的受體能階狀態導致能帶結構向上位移，從而增加有效障壁高度。符號
76代表能帶能量圖70中有效肖特基障壁高度的能階。能帶能量圖40所描繪結構的有效肖特基障壁高度的能量位置由符號
56表示。符號△
78表示使用鈹摻雜的GaN蓋帽層25實現的有效肖特基障壁高度的正向增加。
現在應當理解，根據本揭露的半導體裝置包含：一對堆疊的III族-氮化物半導體層，該對堆疊的III族-氮化物半導體層形成異質接面，具有2DEG通道形成在該對堆疊的III族-氮化物層中的下層中；源極電極設置在該
對堆疊的III族-氮化物層中的上層之上；汲極電極設置在該對堆疊的III族-氮化物層中的上層之上；鈹摻雜的III族-氮化物材料的蓋帽層設置在該對堆疊的III族-氮化物層中的上層上，此摻雜的III族-氮化物材料的層從該源極電極的歐姆接觸區域延伸到該汲極電極的歐姆接觸區域；閘極電極與摻雜的III族-氮化物材料的該蓋帽層肖特基接觸並且設置在該源極電極與該汲極電極之間。此半導體裝置可以單獨地或組合地包含一或多個以下所述的特徵，包含：其中鈹摻雜的III族-氮化物材料的該蓋帽層是鈹摻雜氮化鎵；其中該鈹摻雜的III族-氮化物材料是具有在1nm與10nm之間的厚度的層；其中鈹的摻雜濃度在從1×1016/cm3到5×1019/cm3的範圍內；或其中該半導體裝置是空乏型場效電晶體。
現在還應該理解，依據本揭露的半導體裝置包含：基板；在該基板上的一對III族-氮化物層形成：在該對III族-氮化物層中的下層中具有二維電子氣(2DEG)通道的異質接面；在該對III族-氮化物層的上層上的蓋帽鈹摻雜的III族-氮化物層；以及與鈹摻雜的III族-氮化物層的該蓋帽的部分肖特基接觸的電性觸點。半導體裝置可以單獨地或組合地包含一或多個以下所述的特徵，包含：其中該蓋帽鈹摻雜的III族-氮化物是具有在1nm與10nm之間的厚度的層；或其中鈹的摻雜濃度在從1×1016/cm3到5×1019/cm3的範圍內。
本揭露的多個實施例已經被描述。然而，將
理解的是，在不脫離本揭露的精神和範圍的情況下，可以做出各種修改。AlGaN障壁層，儘管用於GaN通道層的常見III族-氮化物障壁層不是唯一適用的III族-氮化物障壁材料。在纖鋅礦或六方晶體結構中與氮鍵合的任何III族元素組合都將適用，這些組合會產生與第二III族-氮化物通道層的介面極化錯置和2DEG的形成。III族元素包括IIIA族元素(B、Al、Ga、In)和IIIB族元素(Sc、Y、La和鑭系元素)及其所有組合。通道層和障壁層的組成不需要始終是同質的，並且可以由多層、III族元素的多種組合或III族元素組成的梯度組成。附加實施例包含其中鈹摻雜的接觸層在整個裝置上具有不同厚度的結構，舉例而言，均勻的10nm厚的鈹摻雜蓋帽層被乾式蝕刻至閘極接觸下方5nm的厚度。
此外，應當理解，相對於基板18的晶體結構，可以使用其他單晶基板18，例如獨立式III族-氮化物基板或能夠沉積具有單一明確定義的晶體定向的一或多個結晶III族-氮化物覆蓋層的任何晶體基板。這包含藉由將一或多種結晶材料沉積在另一種結晶材料上而形成的異質接面結構，或藉由將一或多層結合在一起以定義結晶表面區域並支持一或多種III族-氮化物材料的結晶生長而形成的異質接面結構。因此，其他實施例也在所附請求項的範圍內。
10:半導體結構
12:空乏型高電子遷移率場效電晶體
18:單晶基板
20:層
22:層
23:層
24:層
25:蓋帽層
26:源極電極
27:歐姆接觸區域
28:汲極電極
29:歐姆接觸區域
34:閘極電極
Claims (10)
- 一種半導體裝置，包括：一對堆疊的III族-氮化物半導體層，該對堆疊的III族-氮化物半導體層形成異質接面，具有2DEG通道形成在該對堆疊的III族-氮化物半導體層中的下層中；源極電極設置在該對堆疊的III族-氮化物半導體層中的上層之上；汲極電極設置在該對堆疊的III族-氮化物半導體層中的上層之上；鈹摻雜的III族-氮化物材料的蓋帽層設置在該對堆疊的III族-氮化物半導體層中的上層上，該鈹摻雜的III族-氮化物材料的蓋帽層從該源極電極的歐姆接觸區域延伸到該汲極電極的歐姆接觸區域；以及閘極電極與該鈹摻雜的III族-氮化物材料的該蓋帽層肖特基接觸並且設置在該源極電極與該汲極電極之間，其中，該鈹摻雜的III族-氮化物材料的該蓋帽層在該閘極電極下方的部分具有小於該鈹摻雜的III族-氮化物材料的該蓋帽層的其他部分的厚度。
- 如請求項1所述的半導體裝置，其中鈹摻雜的III族-氮化物材料的該蓋帽層是鈹摻雜氮化鎵。
- 如請求項1所述的半導體裝置，其中該鈹摻雜的III族-氮化物材料是具有在1nm與10nm之間的厚度的層。
- 如請求項1所述的半導體裝置，其中鈹的摻雜濃度在從1×1016/cm3到5×1019/cm3的範圍內。
- 如請求項2所述的半導體裝置，其中該鈹摻雜的III族-氮化物材料是具有在1nm與10nm之間的厚度的層。
- 如請求項1所述的半導體裝置，其中該半導體裝置是空乏型場效電晶體。
- 一種半導體裝置，包括：基板；在該基板上的一對III族-氮化物層形成：在該對III族-氮化物層中的下層中具有二維電子氣(2DEG)通道的異質接面；在該對III族-氮化物層的上層上的鈹摻雜的III族-氮化物材料的蓋帽層；以及與該鈹摻雜的III族-氮化物材料的蓋帽層的部分肖特基接觸的電性觸點，其中，該鈹摻雜的III族-氮化物材料的蓋帽層在該電性觸點下方的部分具有小於該鈹摻雜的III族-氮化物材料的蓋帽層的其他部分的厚度。
- 如請求項7所述的半導體裝置，其中該鈹摻雜的III族-氮化物材料的蓋帽層是具有在1nm與10nm之間的厚度的層。
- 如請求項7所述的半導體裝置，其中鈹的摻雜濃度在從1×1016/cm3到5×1019/cm3的範圍內。
- 如請求項9所述的半導體裝置，其中該鈹摻雜的III族-氮化物材料的蓋帽層是具有在1nm與10nm之間的厚度的層。
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| KR20230007512A (ko) | 2023-01-12 |
| US11362190B2 (en) | 2022-06-14 |
| WO2021236199A1 (en) | 2021-11-25 |
| JP2023527310A (ja) | 2023-06-28 |
| TW202145579A (zh) | 2021-12-01 |
| EP4154322A1 (en) | 2023-03-29 |
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