US9620598B2 - Electronic device including a channel layer including gallium nitride - Google Patents
Electronic device including a channel layer including gallium nitride Download PDFInfo
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- US9620598B2 US9620598B2 US14/741,567 US201514741567A US9620598B2 US 9620598 B2 US9620598 B2 US 9620598B2 US 201514741567 A US201514741567 A US 201514741567A US 9620598 B2 US9620598 B2 US 9620598B2
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- barrier layer
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- channel layer
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- 229910002601 GaN Inorganic materials 0.000 title description 3
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title 1
- 230000004888 barrier function Effects 0.000 claims abstract description 149
- 239000004065 semiconductor Substances 0.000 claims abstract description 97
- 238000009825 accumulation Methods 0.000 claims abstract description 82
- 239000000463 material Substances 0.000 claims abstract description 80
- 150000001875 compounds Chemical class 0.000 claims abstract description 17
- 230000035508 accumulation Effects 0.000 claims description 80
- 239000012535 impurity Substances 0.000 claims description 66
- 230000009467 reduction Effects 0.000 claims description 33
- 239000000370 acceptor Substances 0.000 claims description 24
- 239000000758 substrate Substances 0.000 claims description 19
- 230000006911 nucleation Effects 0.000 claims description 9
- 238000010899 nucleation Methods 0.000 claims description 9
- 229910052799 carbon Inorganic materials 0.000 claims description 8
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 6
- 230000007423 decrease Effects 0.000 claims description 4
- 239000008186 active pharmaceutical agent Substances 0.000 claims 9
- 239000002019 doping agent Substances 0.000 claims 1
- 239000000969 carrier Substances 0.000 abstract description 41
- 230000009286 beneficial effect Effects 0.000 abstract 1
- 125000006850 spacer group Chemical group 0.000 description 13
- 239000000203 mixture Substances 0.000 description 12
- 238000000034 method Methods 0.000 description 8
- 230000008901 benefit Effects 0.000 description 6
- 229910052795 boron group element Inorganic materials 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 230000000052 comparative effect Effects 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000004377 microelectronic Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 229910010271 silicon carbide Inorganic materials 0.000 description 3
- 229910004613 CdTe Inorganic materials 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- -1 alkyl compound Chemical class 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 229910052749 magnesium Inorganic materials 0.000 description 2
- 230000005012 migration Effects 0.000 description 2
- 238000013508 migration Methods 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 230000000737 periodic effect Effects 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229910052696 pnictogen Inorganic materials 0.000 description 2
- 229910052596 spinel Inorganic materials 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 229910016420 Ala Inb Inorganic materials 0.000 description 1
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910026161 MgAl2O4 Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 150000001450 anions Chemical class 0.000 description 1
- 229910052790 beryllium Inorganic materials 0.000 description 1
- 229910052793 cadmium Inorganic materials 0.000 description 1
- UHYPYGJEEGLRJD-UHFFFAOYSA-N cadmium(2+);selenium(2-) Chemical compound [Se-2].[Cd+2] UHYPYGJEEGLRJD-UHFFFAOYSA-N 0.000 description 1
- 229910052800 carbon group element Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 150000001768 cations Chemical class 0.000 description 1
- 229910052798 chalcogen Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 description 1
- 150000004820 halides Chemical class 0.000 description 1
- 150000004678 hydrides Chemical class 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 150000002902 organometallic compounds Chemical class 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000011029 spinel Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 230000005533 two-dimensional electron gas Effects 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
- H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78681—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/404—Multiple field plate structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
Definitions
- the present disclosure relates to electronic devices, and more particularly to, electronic devices including channel layers having compound semiconductor materials.
- Microelectronic devices such as transistors, diodes, and other microelectronic devices can be formed with a compound semiconductor material, such as SiC, GaN, InP, CdTe, etc. that allows such microelectronic devices to be operated at relatively higher temperatures, higher breakdown voltages, lower on-resistance, thus higher efficiency as compared to their Si-based counterparts.
- a compound semiconductor material such as SiC, GaN, InP, CdTe, etc. that allows such microelectronic devices to be operated at relatively higher temperatures, higher breakdown voltages, lower on-resistance, thus higher efficiency as compared to their Si-based counterparts.
- a transistor can have a channel layer that includes a compound semiconductor material, such as GaN.
- Such transistor can have an dynamic on-resistance (R DSON ) that is dramatically higher at a higher temperature, such as at 150° C., during the on and off switching operations, as compared to about room temperature (25° C.).
- R DSON dynamic on-resistance
- V DS voltage difference between the drain and source
- High dynamic R DSON is undesired.
- FIG. 1 includes an illustration of a cross-sectional view of a portion of a workpiece including a substrate, a nucleation layer, and a superlattice structure.
- FIG. 2 includes an illustration of a cross-sectional view of the workpiece of FIG. 1 after forming a semiconductor layer over the superlattice structure.
- FIG. 3 includes an illustration of a cross-sectional view of the workpiece of FIG. 2 after forming a channel layer and a barrier layer over the semiconductor layer.
- FIG. 4 includes an illustration of a cross-sectional view of the workpiece of FIG. 3 after forming a substantially completed transistor.
- FIG. 5 includes an illustration of a cross-sectional view of a portion of a workpiece similar to one the illustrated in FIG. 4 except that the transistor structure is an enhancement-mode transistor.
- FIG. 6 includes an illustration of a cross-sectional view of a portion of a workpiece similar to one the illustrated in FIG. 4 except that a spacer layer is disposed between the channel layer and the barrier layer.
- FIG. 7 includes an illustration of a cross-sectional view of a portion of a workpiece similar to one the illustrated in FIG. 5 except that a spacer layer is disposed between the channel layer and the barrier layer.
- FIG. 8 includes a plot of on-resistance versus drain-to-source voltage at 25° C. and 150° C. for different transistors.
- compound semiconductor intended to mean a semiconductor material that includes at least two different elements. Examples include SiC, SiGe, GaN, InP, Al a Ga (1 ⁇ a) N, CdTe, and the like.
- a III-V semiconductor material is intended to mean a semiconductor material that includes at least one trivalent metal element and at least one Group 15 element.
- a III-N semiconductor material is intended to mean a semiconductor material that includes at least one trivalent metal element and nitrogen.
- a Group 13-Group 15 semiconductor material is intended to mean a semiconductor material that includes at least one Group 13 element and at least one Group 15 element.
- a II-VI semiconductor material is intended to mean a semiconductor material that includes at least one divalent metal element and at least one Group 16 element.
- carrier impurity is intended to mean (1) when an acceptor, an impurity within a compound having a different valence state as compared to at least 90% of all cations within the compound, or (2) when a donor, an impurity within a compound having a different valence as compared to at least 90% of all anions within the compound.
- C, Mg, and Si are acceptors with respect to GaN because they can trap electrons.
- Al is not a carrier impurity with respect to GaN because Al and Ga have a 3+ valence.
- a carrier impurity may be intentionally added or may be present as a naturally occurring impurity or as a consequence of forming a layer that includes the impurity.
- Acceptors and donors are carrier impurities of opposite carrier types.
- carrier impurity concentration or “concentration of a carrier impurity”, when referring to a layer or a region, is intended to mean an average concentration for such layer or region.
- normal operation and “normal operating state” refer to conditions under which an electronic component or device is designed to operate.
- the conditions may be obtained from a data sheet or other information regarding voltages, currents, capacitance, resistance, or other electrical parameters.
- normal operation does not include operating an electrical component or device well beyond its design limits.
- An electronic device can include a transistor having a channel layer.
- the electronic device can include a back barrier to confine carriers within the channel layer.
- the back barrier can include a material with larger band gap than the material of the channel layer.
- An example would be the channel is made of GaN, and back barrier is Al x Ga (1 ⁇ x) N, wherein 0 ⁇ x ⁇ 1.
- the channel layer can be doped with carrier impurities, such as acceptors or donors.
- the electronic device can include a layer that is closer to the channel layer, and another layer that is farther from the channel layer.
- the layer closer to the channel layer can be a carrier barrier that reduces the likelihood that carriers will enter the semiconductor layer, and the layer farther from the channel layer can be a carrier accumulation layer, such that if a carrier passes from the channel layer through the carrier barrier layer, the carrier can be held in the carrier accumulation layer, which can help reduce leakage current.
- carrier impurity atoms can be carrier traps that trap carriers. As the temperature and electric field increase, some of carriers within the carrier traps become de-trapped.
- the carrier barrier layer has less carrier trapping sites as compared to a conventional superlattice structure that may contact the channel layer. Thus, the carriers are more likely to be confined within the channel layer by higher bandgap energy.
- the carrier accumulation layer may have relatively more carrier traps than the carrier barrier layer. Thus, if de-trapped carriers pass from the channel layer through the carrier barrier layer or are emitted from the carrier barrier layer, the de-trapped carriers can pass to the charge accumulation layer.
- the charge accumulation layer has a greater concentration of carrier impurities, and therefore, can trap the carriers within the carrier traps. Such an embodiment may reduce leakage current when the transistor is off.
- an electronic device can include a substrate, a carrier accumulation layer overlying the substrate, a carrier barrier layer overlying the carrier accumulation layer, and a channel layer of a transistor overlying the carrier barrier layer.
- the channel layer can include a compound semiconductor material and have a thickness in a range of 50 nm to 550 nm.
- an electronic device can include a substrate, a carrier accumulation region overlying the substrate, a carrier barrier layer overlying the carrier accumulation layer, and a channel layer of a transistor overlying the carrier barrier layer.
- the channel layer can include GaN.
- the carrier accumulation layer, the carrier barrier layer, or each of the carrier accumulation layer and the carrier barrier layer can include Al x Ga (1 ⁇ x) N, wherein x is in a range of 0.08 to 0.12.
- the concepts as disclosed herein may be useful for transistors having channel layers that include compound semiconductor materials.
- the compound semiconductor material can include two different Group 14 elements, such as SiC, SiGe, or the like; a III-V semiconductor material, such as a Group 13-Group 15 semiconductor material (GaN, InP, GaAs, Al a Ga (1 ⁇ a) N, Al a In b Ga (1 ⁇ a ⁇ b) N, etc., a III-N semiconductor material, or the like; or a II-VI semiconductor material, such as ZnO, CdSe, or the like.
- Group 14 elements such as SiC, SiGe, or the like
- III-V semiconductor material such as a Group 13-Group 15 semiconductor material (GaN, InP, GaAs, Al a Ga (1 ⁇ a) N, Al a In b Ga (1 ⁇ a ⁇ b) N, etc., a III-N semiconductor material, or the like
- II-VI semiconductor material such as ZnO, CdSe, or the like.
- FIG. 1 includes an illustration of a cross-sectional view of a portion of a workpiece that includes a substrate 100 , a nucleation layer 120 , and a superlattice structure 140 .
- the substrate 100 has a primary surface 102 and can include silicon, GaN, diamond, sapphire (monocrystalline Al 2 O 3 ), silicon carbide (SiC), aluminum nitride (AlN), gallium oxide (Ga 2 O 3 ), spinel (MgAl 2 O 4 ), another suitable substantially monocrystalline material, or the like.
- the selection of the particular material and crystal orientation along the primary surface 102 can be selected depending upon the composition of the superlattice structure 140 that will be subsequently formed over the substrate 100 .
- the nucleation layer 120 can help to epitaxially grow the superlattice structure 140 .
- the nucleation layer 120 may include one or more elements that are common to the subsequently formed superlattice structure 140 .
- the nucleation layer can include aluminum nitride when an aluminum-containing superlattice structure 140 is being formed over the nucleation layer 120 .
- the thickness of the nucleating layer can be in a range of 20 nm to 1000 nm.
- the superlattice structure 140 can include a plurality of films.
- the composition of the films may depend on the voltage at which the electronic device operates, the composition of the subsequently-formed channel layer, or both.
- the overall thickness of the superlattice structure can be in a range of 0.1 micron to 100 microns. In a particular embodiment, the overall thickness is in a range of 1 micron to 10 microns. As the operating voltage increases, the complexity and overall thickness of the superlattice structure can increase.
- the channel layer includes GaN
- superlattice structure includes Al z Ga (1 ⁇ z) N, where 0 ⁇ z ⁇ 1.
- the content of Al decreases and the content of Ga content increases as the distance from the nucleation layer 120 increases.
- the superlattice structure 140 includes a lower region 142 and an upper region 144 .
- Each of the lower and upper regions 142 and 144 can include a single film, a plurality of films, or be part of a larger film. The significance of the regions, and the upper region 144 in particular, will become more apparent when describing design considerations and alternative embodiments later in this specification.
- a semiconductor layer 240 is formed over the superlattice structure 140 .
- the semiconductor layer 240 can be a back barrier with a larger band gap to confine carriers, such as electrons or holes, within a subsequently-formed channel layer.
- the semiconductor layer 240 includes a charge accumulation layer 242 that is closer to the superlattice structure 140 and a charge barrier layer 244 that is closer to the subsequently-formed channel layer.
- the charge accumulation layer 242 abuts the region 144 of the superlattice structure 140 .
- the semiconductor layer 240 may include further regions or discrete films, and thus, the layers 242 and 244 may be spaced apart from each other.
- a channel layer 340 is formed over the semiconductor layer 240 , and a barrier layer 350 is formed over the channel layer 340 .
- the carrier barrier layer 244 is disposed between and abuts the carrier accumulation layer 242 and the channel layer 340 in the embodiment as illustrated.
- the nucleation layer 120 , the superlattice structure 140 , the semiconductor layer 240 , and channel layer 340 , the barrier layer 350 , or any combination thereof can be formed using Molecular Beam Epitaxy (MBE), Physical Vapor Deposition (PVD), or using chemical vapor deposition techniques such as, for example, a Metalorganic Chemical Vapor Deposition (MOCVD) technique, a Plasma-enhanced Chemical Vapor Deposition (PECVD) technique, a Low Pressure Chemical Vapor Deposition (LPCVD) technique, or the like.
- MBE Molecular Beam Epitaxy
- PVD Physical Vapor Deposition
- chemical vapor deposition techniques such as, for example, a Metalorganic Chemical Vapor Deposition (MOCVD) technique, a Plasma-enhanced Chemical Vapor Deposition (PECVD) technique, a Low Pressure Chemical Vapor Deposition (LPCVD) technique, or the like.
- the semiconductor layer 240 is epitaxially grown from the superlattice structure 140
- the channel layer 340 is epitaxially grown from the semiconductor layer 240
- the barrier layer is epitaxially grown from the channel layer 340 .
- the epitaxial growth can be performed as a chemical vapor deposition using an organometallic compound, a hydride, or a halide.
- an alkyl compound may be used.
- a gallium source may include Ga(C x H 2x+1 )) 3 , where x is 1 to 3.
- a nitrogen source can include NH 3 or N 2 H 4 .
- Carrier impurities such as acceptors or donors, may be incorporated from one or more of the sources (for example, C from the Ga source gas) or may be separately added if needed or desired.
- acceptors can include Be, C, Mg, Zn, Cd, or any combination thereof, and donors can include Si, Ge, or any combination thereof.
- the composition and thickness of the layers 140 , 240 , and 350 may depend on the composition of the channel layer 340 .
- the channel layer 340 will be first described followed by the semiconductor layer 240 , the region 144 of the superlattice structure 140 , and the barrier layer 350 . While some details are specific for a GaN channel layer, after reading the specification, skilled artisans will be able to make embodiments that meet their needs or desires, even if the composition of the channel layer 340 is not GaN.
- the channel layer 340 includes a semiconductor material, such as a III-V semiconductor material or a II-VI semiconductor material.
- the channel layer 340 includes a III-V semiconductor material.
- the semiconductor material includes a single Group 13 element, or in another embodiment, includes at least two different Group 13 elements.
- the carrier impurities can be carrier traps within the channel layer 340 and may be acceptors or donors.
- a high density two dimensional electron gas (2DEG) can be formed near the interface of barrier layer 350 and the channel layer 340 , and is responsible for high mobility and lower resistivity of the transistor. Any reduction of the 2DEG electrons will increase the on-resistance of the transistor.
- the acceptors can trap the electrons in the channel layer 340 due to high electron density at the beginning. Once the device is in an off state, high electric fields from the gate edge, field plate edges, and drain edge can de-trap the electrons from the acceptor traps, and these de-trapped electrons can be driven toward the underlying layers.
- acceptors can include carbon from a source gas when metalorganic chemical vapor deposition (MOCVD) is used to form the channel layer 340 . Some carbon can become incorporated as the channel layer 340 is grown. The carbon content may be controlled by controlling the deposition conditions, such as the deposition temperature and flow rates.
- MOCVD metalorganic chemical vapor deposition
- the channel layer 340 has a carrier impurity concentration that is at least 1 ⁇ 10 13 atoms/cm 3 , less than 1 ⁇ 10 14 atoms/cm 3 , less than 1 ⁇ 10 15 atoms/cm 3 , or at less than 5 ⁇ 10 15 atoms/cm 3 , and in another embodiment, no greater than 3 ⁇ 10 16 atoms/cm 3 .
- the carrier impurity concentration is in a range of 1 ⁇ 10 13 atoms/cm 3 to 3 ⁇ 10 16 . In a particular embodiment, the lowest trap concentration is desired but may be limited by growth or deposition conditions and purity of the precursors.
- the channel layer 340 has a thickness that is at least 50 nm, at least 110 nm, or at least 200 nm. When the thickness is less than 50 nm, a DEG2 may be more difficult to generate, maintain, or both. In another embodiment, the channel layer 340 has a thickness that is no greater than 5000 nm, no greater than 2000 nm, no greater than 900 nm, no greater than 550 nm, or no greater than 300 nm. In a particular embodiment, the effectiveness of the back barrier to confine carriers may be reduced as the thickness of the channel layer is greater than 550 nm.
- the channel layer 340 has a thickness is in a range of 20 nm to 2000 nm, 50 nm to 550 nm, or 110 nm to 300 nm.
- the thickness in a range of 110 nm to 300 nm can provide sufficiently thick channel layer 340 to allow for the proper generation and maintaining of the 2DEG and still obtain a reasonable static R DSON and effectiveness of the back barrier.
- the charge barrier layer 244 of the semiconductor layer 240 can be a barrier to help keep carriers within the channel layer 340 .
- the charge barrier layer 244 can include a semiconductor material, such as a III-V semiconductor material or a II-VI semiconductor material.
- the bandgap energy, the carrier impurity concentration, or both for the charge barrier layer 244 can be selected to help keep carriers, particularly de-trapped carriers, to stay confined within the channel layer 340 .
- the semiconductor material of the channel layer 340 has a bandgap energy that can be at a lower energy as compared to the semiconductor material of the charge barrier layer 244 .
- the higher bandgap energy of the semiconductor material of the charge barrier layer 244 helps to make the transition of carriers from the channel layer 340 to the charge barrier layer 244 energetically less favored.
- the carrier impurity concentration may be used instead of or in conjunction with the adjustment of the bandgap energy.
- the channel layer 340 can have a concentration of the carrier impurities (acceptors or donors) that is the same or less than the concentration of the carrier impurity of the same type (acceptors or donors) within the charge barrier layer 244 .
- a lower carrier impurity concentration in the charge barrier layer 244 allows for fewer carrier traps, and therefore, should carriers become de-trapped from charge barrier layer 244 , there are fewer de-trapped carriers migrating into the channel layer 340 as compared to when the charge barrier layer 244 has a higher carrier impurity concentration.
- the channel layer 340 can have a carrier impurity concentration that is less than the carrier impurity concentration within the charge barrier layer 244 .
- the semiconductor material of the charge barrier layer 244 may be selected such that migration of a carrier from the channel layer 340 to the charge barrier layer 244 is energetically less favored.
- a higher carrier impurity concentration in the charge barrier layer 244 can be tolerated due to the dissimilarities in energies of the conduction or valence bands for the semiconductor materials of the charge barrier layer 244 and the channel layer 340 .
- the carrier impurity concentrations of the charge barrier layer 244 and the channel layer may be substantially equal.
- the charge barrier layer 244 can have include Al y Ga (1 ⁇ y) N, wherein 0 ⁇ y ⁇ 1.
- y is at least 0.001, at least 0.05, at least 0.08, at least 0.10, or at least 0.12, and in another embodiment, y is no greater than 0.50, no greater than 0.30, no greater than 0.20, or no greater than 0.12.
- y is in a range of 0.0001 to 0.50, 0.05 to 0.30, 0.08 to 0.20, or 0.08 to 012.
- y in a range of 0.08 to 0.12 allows for a sufficiently greater bandgap energy as compared to the channel layer 340 and keeps lattice mismatch to the channel layer 340 low.
- the charge barrier layer 244 has a concentration of a carrier impurity that is at least 1 ⁇ 10 13 atoms/cm 3 , at least 1 ⁇ 10 14 atoms/cm 3 , at least ⁇ 10 15 atoms/cm 3 , or at least 5 ⁇ 10 15 atoms/cm 3 , and in another embodiment, the charge barrier layer 244 has a concentration of a carrier impurity that is no greater than 5 ⁇ 10 18 atoms/cm 3 , no greater than 1 ⁇ 10 18 atoms/cm 3 , no greater than 1 ⁇ 10 17 atoms/cm 3 , or no greater than 5 ⁇ 10 16 atoms/cm 3 .
- the charge barrier layer 244 has a concentration of a carrier impurity in a range of 1 ⁇ 10 13 atoms/cm 3 to 5 ⁇ 10 18 atoms/cm 3 , 1 ⁇ 10 14 atoms/cm 3 to 1 ⁇ 10 18 atoms/cm 3 , 1 ⁇ 10 15 atoms/cm 3 to 1 ⁇ 10 17 atoms/cm 3 , or 5 ⁇ 10 15 atoms/cm 3 to 5 ⁇ 10 16 atoms/cm 3 .
- the charge barrier layer 244 has a thickness that is at least 50 nm, at least 110 nm, at least 200 nm, or at least 600 nm, and in another embodiment, the charge barrier layer 244 has a thickness that is no greater than 5000 nm, no greater than 2000 nm, no greater than 1500 nm, or no greater than 900 nm. In a further embodiment, the charge barrier layer 244 has a thickness is in a range of 50 nm to 5000 nm, 110 nm to 2000 nm, 200 nm to 1500 nm, or 600 nm to 900 nm. In an embodiment, the charge barrier layer 244 has a thickness greater than the thickness of the channel layer 340 .
- the charge barrier layer 244 has a thickness that is substantially the same or less than the thickness of the channel layer 340 .
- a thickness in a range of 600 nm to 900 nm can allow for a good balance between sufficiently thin, so that carriers can migrate from the channel layer 340 , but not so thin that carriers from the charge accumulation layer 242 can easily migrate into the channel layer 340 .
- the charge accumulation layer 242 of the semiconductor layer 240 can help to collect de-trapped carriers from the charge barrier layer 244 or the channel layer 340 .
- the charge accumulation layer 242 can have a different composition as compared to the charge barrier layer 244 or the channel layer 340 .
- the different compositions may include at least one different element, different content levels of one or more elements, or both.
- the charge accumulation layer 242 can include a semiconductor material, such as a III-V semiconductor material or a II-VI semiconductor material.
- the bandgap energy, the carrier impurity concentration, or both of the charge accumulation layer 242 can be selected to help keep carriers, particularly de-trapped carriers, confined within the channel layer 340 .
- Such carriers should remain with the charge accumulation layer 242 .
- such accumulated carriers may help to repel carriers within the channel layer 340 away from the charge barrier layer 244 , and therefore, can also help to confine carriers within the channel layer 340 and reduce the likelihood of carriers entering the charge barrier layer 244 .
- the semiconductor material of the charge barrier layer 244 can have a bandgap energy that is substantially the same as a bandgap energy of the semiconductor material of the charge accumulation layer 242 .
- de-trapped electrons or holes do not have to overcome an energy barrier to enter the charge accumulation layer 242 from the charge barrier layer 244 .
- the bandgap energy of the semiconductor material of the charge accumulation layer 242 can be less than the bandgap energy of the semiconductor material of the charge barrier layer 244 .
- the bandgap energy of the semiconductor material of the charge accumulation layer 242 can be higher than the bandgap energy of the semiconductor material of the charge barrier layer 244 . In either of these embodiments, the bandgap energy of the charge accumulation layer 242 should not be too far from the bandgap energy of the charge barrier layer 244 , the channel layer 340 , or both.
- carriers are energetically favored to stay within the channel layer 340 , rather than migrate into the charge barrier layer 244 .
- the semiconductor material of the charge barrier layer 244 can have a bandgap energy that is substantially the same as a bandgap energy of the channel layer 340 . De-trapped carriers from the charge barrier layer 244 are energetically more favored to enter the charge barrier layer 242 as compared to the channel layer 340 .
- the charge accumulation layer 242 can include a III-V semiconductor material having at least two different Group 13 elements.
- the charge accumulation layer 242 includes Al x Ga (1 ⁇ x) N, wherein 0 ⁇ x ⁇ 1.
- the semiconductor material includes GaN.
- x is at least 0.001, at least 0.05, at least 0.08, at least 0.10, or at least 0.12, and in another embodiment, y is no greater than 0.50, no greater than 0.30, no greater than 0.20, or no greater than 0.12.
- x is in a range of 0.0001 to 0.50, 0.05 to 0.30, 0.08 to 0.20, or 0.08 to 012.
- y in a range of 0.08 to 0.12 allows for a sufficiently greater bandgap energy as compared to the channel layer 340 and keeps lattice mismatch to the charge barrier layer 244 low.
- the charge accumulation layer 242 can have a higher carrier impurity concentration as compared to the charge barrier layer 244 .
- the charge accumulation layer 242 has a carrier impurity at a concentration of at least 1 ⁇ 10 19 atoms/cm 3 , at least 2 ⁇ 10 19 atoms/cm 3 , or at least 5 ⁇ 10 19 atoms/cm 3 , and in another embodiment, the charge accumulation layer 242 has a carrier impurity at a concentration of no greater than 1 ⁇ 10 21 atoms/cm 3 .
- the charge accumulation layer 242 has a thickness that is at least 50 nm, at least 110 nm, or at least 200 nm, and in another embodiment, the charge accumulation layer 242 has a thickness that is no greater than 1500 nm, no greater than 900 nm, no greater than 600 nm, or no greater than 300 nm. In a further embodiment, the region has a thickness is in a range of 50 nm to 1500 nm, 110 nm to 900 nm, 110 nm to 600 nm, or 200 nm to 300 nm. In a particular embodiment, the charge barrier layer 244 is thicker than the charge accumulation layer 242 .
- the charge accumulation layer 242 can have a thickness that is the same, greater than or less than the thickness of the channel layer 340 .
- a thickness in a range of 200 nm to 300 nm allows a sufficient thickness to accumulate sufficient charge and still be thin enough to have sufficient charge to repel carriers within the channel layer 340 , so that carriers are more likely at the surface of the channel layer 340 opposite the surface that abuts the carrier barrier layer 242 , which in turns helps with the generation and maintaining of the 2DEG.
- the region 144 of the superlattice structure can have a composition that aids in the functionality of the layer 240 .
- the region 144 may have some design considerations that are similar to the charge barrier layer 244 of the semiconductor layer 240 .
- the region 144 can include a semiconductor material, such as a III-V semiconductor material or a II-VI semiconductor material.
- the bandgap energy, the carrier impurity concentration, or both of the region 144 can be selected to help keep carriers, particularly de-trapped carriers, to stay confined within the semiconductor layer 240 .
- the semiconductor material of the region 144 has a bandgap energy that greater the bandgap energy of the semiconductor material of the charge barrier layer 244 .
- the greater bandgap energy of the semiconductor material of the region 144 helps to make the transition from the charge accumulation layer 242 to the region 144 energetically less favored.
- the carrier impurity concentration may be used instead of or in conjunction with the adjustment of the bandgap energy.
- the region 144 can have a concentration of the carrier impurity (acceptors or donors) that is less than the concentration of the carrier impurity of the same type (acceptors or donors) within the charge accumulation layer 242 .
- a lower carrier impurity concentration in the region 144 allows for fewer carrier traps.
- the region 144 can have a carrier impurity concentration that is greater than the carrier impurity concentration within the charge accumulation layer 242 .
- the semiconductor material of the region 144 may be selected such that migration of a carrier from the charge accumulation layer 242 to the region 144 is energetically less favored.
- a higher carrier impurity concentration in the region 144 can be tolerated due to the dissimilarities in energies of the conduction or valence bands for the semiconductor materials of the region 144 and the charge accumulation layer 242 .
- the carrier impurity concentrations of the region 144 and the charge accumulation layer 242 may be substantially equal.
- the region 144 may have a semiconductor material with a bandgap energy that is the same as or greater than the bandgap energy of the charge barrier layer 244 .
- the carrier impurity concentration and thickness of the region 144 may depend more on the design of the remainder of the superlattice structure 120 and the voltage that the superlattice structure 120 is designed to support.
- the region 144 can have any of the thicknesses as previously described with respect to the charge barrier layer 244 .
- the thicknesses of the regions 144 and 244 can be the same or different.
- the barrier layer 350 can include a III-V semiconductor material or a II-VI semiconductor material.
- the barrier layer 350 includes at least two different Group 13 elements.
- the barrier layer 350 can includes Al w Ga (1 ⁇ w) N, wherein 0 ⁇ w ⁇ 1.
- w is at least 0.009, at least 0.05, at least 0.11, or at least 0.15, and in another particular embodiment, w is no greater than 0.50, no greater than 0.40, or no greater than 0.30.
- w is in a range of 0.0009 to 0.50, 0.05 to 0.40, or 0.15 to 0.30.
- the barrier layer 350 has a carrier impurity concentration that is at least 1 ⁇ 10 13 atoms/cm 3 , at least 1 ⁇ 10 14 atoms/cm 3 , at least 1 ⁇ 10 15 atoms/cm 3 , or at least 5 ⁇ 10 15 atoms/cm 3 , and in another embodiment, the carrier impurity concentration is no greater than 5 ⁇ 10 18 atoms/cm 3 , no greater than 1 ⁇ 10 18 atoms/cm 3 , no greater than 1 ⁇ 10 17 atoms/cm 3 , or no greater than 5 ⁇ 10 16 atoms/cm 3 .
- the carrier impurity concentration is in a range of 1 ⁇ 10 13 atoms/cm 3 to 5 ⁇ 10 18 atoms/cm 3 , 1 ⁇ 10 14 atoms/cm 3 to 1 ⁇ 10 18 atoms/cm 3 , 1 ⁇ 10 15 atoms/cm 3 to 1 ⁇ 10 17 atoms/cm 3 , or 5 ⁇ 10 15 atoms/cm 3 to 5 ⁇ 10 16 atoms/cm 3 .
- the carrier impurity concentration in the barrier layer 350 can be selected to maintain the strain of the barrier layer 350 by acceptors, such as carbon, due to the higher cohesive energy of such an acceptor. In another embodiment, similar effects may be seen with other carrier impurities.
- the barrier layer 350 has a thickness that is at least 0.5 nm, at least 5 nm, at least 11 nm, or at least 20 nm, and in another embodiment, the barrier layer 350 has a thickness that is no greater than 200 nm, no greater than 150 nm, no greater than 90 nm, or no greater than 40 nm. In a further embodiment, the barrier layer 350 has a thickness is in a range of 0.5 nm to 200 nm, 5 nm to 40 nm.
- An insulating layer 420 can be formed over the barrier layer 350 and can include one or more insulating films.
- the insulating layer 420 can include a nitride compound, such as silicon nitride, aluminum nitride, or the like.
- the insulating layer 420 may include an oxide film. If oxide is incompatible or causes a processing or other issue with the channel layer 340 or an underlying layer, a film of a different composition may be formed before the oxide.
- a film within the gate dielectric layer may include a nitride and can be partly oxidized to form the oxide layer.
- Portions of the insulating layer 420 can be removed at locations to form a gate well and openings for source and drain electrodes.
- the openings for the source and drain electrodes may terminate within the insulating layer 420 (illustrated), within the barrier layer 350 or extend through both the insulating layer 420 and the barrier layer 350 .
- the gate well may terminate within the insulating layer 420 (illustrated) or extend into the barrier layer 350 .
- the gate well does not extend to the channel layer 340 .
- the source electrode 442 , the gate electrode 444 , and the drain electrode 446 are then formed.
- the barrier layer 350 is disposed between the channel layer 340 and the gate electrode 444 .
- the portions of the gate electrode 444 that are further from the channel layer 340 and closer to the drain electrode 446 act as a shield plate to reduce the gate-to-drain capacitance.
- the portions of the source electrode 442 that extend over the gate electrode and toward to the drain electrode 446 act as a shield plate to reduce the gate-to-drain capacitance.
- Interconnects 462 and 466 are formed that are electrically connected to the source electrode 442 and the drain electrode 446 , respectively.
- an interconnect to the gate electrode 444 is also formed.
- one or more additional insulating layers, conductive plugs, and interconnect levels can be formed if needed or desired.
- additional transistors may be formed. In a particular embodiment, a plurality of the transistors can be connected in parallel to provide an equivalent transistor having a sufficiently large channel width to support high current flow when the transistor is on.
- FIG. 4 includes an illustration of a depletion-mode transistor.
- an enhancement-mode transistor can be formed, as illustrated in FIG. 5 .
- a layer 544 having a carrier type that is the same as the channel layer 340 can be formed.
- the layer 544 includes Al a Ga (1 ⁇ a) N, wherein 0 ⁇ a ⁇ 1. If the carrier impurities in the channel layer 340 are acceptors, the layer 544 also includes acceptors, and if the carrier impurities in the channel layer 340 are donors, the layer 544 also includes donors.
- FIGS. 6 and 7 include embodiments in which a spacer layer 650 is disposed between the barrier layer 350 and the channel layer 340 .
- the spacer layer 650 can include a III-V semiconductor material or a II-VI semiconductor material.
- the spacer layer 350 includes at least two different Group 13 elements.
- the spacer layer 650 can includes Al b Ga (1 ⁇ b) N, wherein 0 ⁇ b ⁇ 1.
- z is at least 0.40, at least 0.50, or at least 0.60, and in another particular embodiment, b is no greater than 1.00, no greater than 0.90, or no greater than 0.80.
- b is in a range of 0.04 to 1.00, 0.50 to 0.90, or 0.60 to 0.80.
- the spacer layer 650 has a higher Al content as compared to the barrier layer 350 .
- the spacer layer 650 has a carrier impurity concentration that is at least 1 ⁇ 10 13 atoms/cm 3 , at least 1 ⁇ 10 14 atoms/cm 3 , at least 1 ⁇ 10 15 atoms/cm 3 , or at least 5 ⁇ 10 15 atoms/cm 3 , and in another embodiment, the carrier impurity concentration is no greater than 5 ⁇ 10 18 atoms/cm 3 , no greater than 1 ⁇ 10 18 atoms/cm 3 , no greater than 1 ⁇ 10 17 atoms/cm 3 , or no greater than 5 ⁇ 10 16 atoms/cm 3 .
- the carrier impurity concentration is in a range of 1 ⁇ 10 13 atoms/cm 3 to 5 ⁇ 10 18 atoms/cm 3 , 1 ⁇ 10 14 atoms/cm 3 to 1 ⁇ 10 18 atoms/cm 3 , 1 ⁇ 10 15 atoms/cm 3 to 1 ⁇ 10 17 atoms/cm 3 , or 5 ⁇ 10 15 atoms/cm 3 to 5 ⁇ 10 16 atoms/cm 3 .
- the carrier impurity concentration in the spacer layer 650 can be selected to maintain the strain of the spacer layer 650 by acceptors, such as carbon, due to the higher cohesive energy of such an acceptor. In another embodiment, similar effects may be seen with other carrier impurities.
- the spacer layer 650 is thinner than the barrier layer 350 has a thickness that is at least 2 nm, at least 5 nm, or at least 7 nm, and in another embodiment, the spacer layer 650 has a thickness that is no greater than 90 nm, no greater than 50 nm, or no greater than 20 nm. In a further embodiment, the spacer layer 650 has a thickness is in a range of 2 nm to 50 nm, 5 nm to 20 nm.
- FIG. 8 includes a plot of dynamic R DSON as a function of V DS when transistors are at 25° C. and at 150° C.
- the devices are stressed at different V DS and after each V DS stressing, the device is turned on to measure on-resistance.
- the transistors At 25° C., the transistors have an R DSON between 0.10 ohms to 0.15 ohms when V DS is in a range of 0 V to 600V.
- the difference between the different transistors becomes more apparent.
- Transistors 1 and 2 are embodiments as described herein and reach a maximum on-resistance (R DSON-max ) at a lower voltage and a lower R DSON at the same voltage as compared to a comparative transistor.
- the Transistors 1 and 2 reach R DSON -max when V DS is no higher than about 190 V. Above 190 V, R DSON decreases until about 450 V and then remains at about the same value. Thus, R DSON at 190 V is higher than R DSON when V DS is 200 V, 220 V, 240 V, or 260 V. The comparative transistor does not reach R DSON-max until V DS is about 270 V.
- R DSON-max After R DSON-max is reached, R DSON decreases more as V DS increases for the Transistors 1 and 2 as compared to the comparative transistor.
- the lower R DSON can be quantified by resistance reduction, which is calculated using the formula below. (( R DSON-max ⁇ R DSON-VDS )/( R DSON-max ))*100%,
- the resistance reduction is greater.
- embodiments as described herein have substantially better on-current properties and can allow more current to pass through the transistor when it is on.
- Transistors 1 and 2 when V DS is 300 V, Transistors 1 and 2 may have a resistance reduction that is no greater than 10%, when V DS is 400 V, the resistance reduction may be no greater than 20%, when V DS is 500 V, the resistance reduction may be no greater than 35%, when V DS is 600 V, the resistance reduction may be no greater than 35%, or any combination thereof.
- the semiconductor layer 240 can help to keep carriers within the channel layer 340 and can allow de-trapped carriers from migrating into the channel layer 340 . Accordingly, the leakage current (when the transistor is off) can be less than for a comparative device.
- the channel layer is not limited to GaN
- the semiconductor layer and the superlattice structure are not limited to Al z Ga (1 ⁇ z) N.
- Other compound semiconductor materials such as III-V (such as, III-N and Group 13-Group 15 semiconductor compounds) and II-VI semiconductor materials can be used.
- III-V such as, III-N and Group 13-Group 15 semiconductor compounds
- II-VI semiconductor materials can be used. The particular selection of materials can be guided as least in part on the considerations as described above regarding energy levels of the conduction bands (for acceptors) and valence bands (for donors) and carrier impurity concentrations for the layers, films, and regions.
- a channel layer can include a III-V semiconductor material, and any one or more of the semiconductor layer (carrier barrier region, the carrier accumulation region, or both) and the superlattice structure can include a II-VI semiconductor material.
- the channel layer can be formed as a monocrystalline layer and the superlattice structure can support the normal operating voltages.
- the carrier impurity concentration profile may be uniform or continuously graded.
- the transistor illustrated in FIG. 4 is a metal-insulator-semiconductor field-effect transistor (MISFET).
- MISFET metal-insulator-semiconductor field-effect transistor
- a gate dielectric layer is disposed between the channel layer and the gate electrode.
- the transistor can be a junction field-effect transistor (JFET) where no gate dielectric layer is present between the channel layer and the gate electrode.
- the gate electrode directly contacts the channel layer.
- An electronic device can include a substrate, a carrier accumulation layer overlying the substrate, a carrier barrier layer overlying the carrier accumulation layer, and a channel layer of a transistor overlying the carrier barrier layer, wherein the channel layer includes a compound semiconductor material and has a thickness in a range of 50 nm to 550 nm.
- the channel layer includes GaN; and the carrier accumulation layer, the carrier barrier layer, or each of the carrier accumulation layer and the carrier barrier layer includes Al x Ga (1 ⁇ x) N, wherein x is in a range of 0.01 to 0.49.
- each of the carrier accumulation layer and the carrier barrier layer includes Al x Ga (1 ⁇ x) N, wherein x is in a range of 0.08 to 0.12, and the carrier accumulation has a greater concentration of a carrier impurity as compared to the carrier barrier layer.
- the carrier accumulation layer has a first bandgap energy
- the carrier barrier layer has a second bandgap energy
- the channel layer has a third bandgap energy
- the second bandgap energy is greater than the third bandgap energy
- the carrier accumulation layer includes GaN and has a thickness no greater than 900 nm.
- each of the carrier accumulation layer, the carrier barrier layer, the channel layer, and the barrier layer includes a III-N material.
- R DSON-max is a maximum on-state resistance a drain-to-source voltage is in a range of 0 to 700 V
- R DSON-VDS is an on-state resistance at a particular drain-to-source voltage (V DS );
- the barrier layer is disposed between the channel layer and the gate electrode
- the carrier barrier layer abuts each of the carrier accumulation layer and the channel layer;
- the carrier accumulation layer includes Al x Ga (1 ⁇ x) N, wherein x is in a range of 0.08 to 0.12, has a concentration of a carrier impurity of a first carrier type that is at least 1 ⁇ 10 18 atoms/cm 3 , and has a thickness in a range of 200 nm to 300 nm;
- the carrier barrier layer includes Al x Ga (1 ⁇ x) N, wherein x is in a range of 0.08 to 0.12, has a concentration of a carrier impurity of the first carrier type that is no greater than 3 ⁇ 10 16 atoms/cm 3 , and has a thickness in a range of 600 nm to 900 nm;
- the channel layer includes GaN, has a concentration of a carrier impurity of the first carrier type that is no greater than 3 ⁇ 10 16 atoms/cm 3 , and has a thickness in a range of 110 nm to 300 nm;
- the barrier layer includes Al x Ga (1 ⁇ x) N, wherein x is in a range of 0.15 to 0.30, and has a thickness in a range of 5 nm to 40 nm.
- An electronic device can include a substrate, a carrier accumulation region overlying the substrate, a carrier barrier layer overlying the carrier accumulation layer; and a channel layer of a transistor overlying the carrier barrier layer, wherein the channel layer includes GaN, wherein the carrier accumulation layer, the carrier barrier layer, or each of the carrier accumulation layer and the carrier barrier layer includes Al x Ga (1 ⁇ x) N, wherein x is in a range of 0.08 to 0.12.
- each of the carrier accumulation layer and the carrier barrier layer includes Al x Ga (1 ⁇ x) N, wherein x is in a range of 0.08 to 0.12.
- An electronic device can include a semiconductor layer and including a II-VI semiconductor material, and a channel layer of a transistor overlying the semiconductor layer and including a III-V semiconductor material.
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Abstract
Description
((R DSON-max −R DSON-VDS)/(R DSON-max))*100%,
((R DSON-max −R DSON-VDS)/(R DSON-max))*100%,
-
- when VDS is 300 V, the resistance reduction is at least 2%;
- when VDS is 400 V, the resistance reduction is at least 3%;
- when VDS is 500 V, the resistance reduction is at least 6%;
- when VDS is 600 V, the resistance reduction is at least 6%; or any combination thereof.
-
- when VDS is 300 V, the resistance reduction is no greater than 10%;
- when VDS is 400 V, the resistance reduction is no greater than 20%;
- when VDS is 500 V, the resistance reduction is no greater than 35%;
- when VDS is 600 V, the resistance reduction is no greater than 35%; or any combination thereof.
Claims (20)
((R DSON-max −R DSON-VDS)/(R DSON-max))*100%,
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