TWI800811B - 半導體記憶裝置 - Google Patents

半導體記憶裝置 Download PDF

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Publication number
TWI800811B
TWI800811B TW110112193A TW110112193A TWI800811B TW I800811 B TWI800811 B TW I800811B TW 110112193 A TW110112193 A TW 110112193A TW 110112193 A TW110112193 A TW 110112193A TW I800811 B TWI800811 B TW I800811B
Authority
TW
Taiwan
Prior art keywords
memory device
semiconductor memory
semiconductor
memory
Prior art date
Application number
TW110112193A
Other languages
English (en)
Other versions
TW202143447A (zh
Inventor
柳平康輔
坪內洋
日岡健
Original Assignee
日商鎧俠股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商鎧俠股份有限公司 filed Critical 日商鎧俠股份有限公司
Publication of TW202143447A publication Critical patent/TW202143447A/zh
Application granted granted Critical
Publication of TWI800811B publication Critical patent/TWI800811B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5671—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge trapping in an insulator
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/32—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
TW110112193A 2020-04-28 2021-04-01 半導體記憶裝置 TWI800811B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2020-079421 2020-04-28
JP2020079421A JP2021174567A (ja) 2020-04-28 2020-04-28 半導体記憶装置

Publications (2)

Publication Number Publication Date
TW202143447A TW202143447A (zh) 2021-11-16
TWI800811B true TWI800811B (zh) 2023-05-01

Family

ID=78161294

Family Applications (1)

Application Number Title Priority Date Filing Date
TW110112193A TWI800811B (zh) 2020-04-28 2021-04-01 半導體記憶裝置

Country Status (4)

Country Link
US (2) US11527284B2 (zh)
JP (1) JP2021174567A (zh)
CN (1) CN113571112B (zh)
TW (1) TWI800811B (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230066753A1 (en) * 2021-09-01 2023-03-02 Micron Technology, Inc. Electronic devices including vertical strings of memory cells, and related memory devices, systems and methods

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060215450A1 (en) * 2005-03-28 2006-09-28 Kabushiki Kaisha Toshiba Semiconductor memory device
US20180068739A1 (en) * 2016-09-06 2018-03-08 Toshiba Memory Corporation Memory device
TW201830401A (zh) * 2016-03-02 2018-08-16 日商東芝記憶體股份有限公司 半導體記憶裝置
TW202011412A (zh) * 2018-09-14 2020-03-16 日商東芝記憶體股份有限公司 半導體記憶裝置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7274035B2 (en) * 2003-09-03 2007-09-25 The Regents Of The University Of California Memory devices based on electric field programmable films
US20160062499A1 (en) * 2014-09-02 2016-03-03 Apple Inc. Touch pixel design for reducing visual artifacts
KR102293078B1 (ko) * 2015-07-06 2021-08-26 삼성전자주식회사 불휘발성 메모리 장치
JP6875236B2 (ja) 2017-09-14 2021-05-19 キオクシア株式会社 半導体記憶装置
JP2019067474A (ja) * 2017-10-05 2019-04-25 東芝メモリ株式会社 半導体記憶装置
JP7074583B2 (ja) 2018-06-26 2022-05-24 キオクシア株式会社 半導体記憶装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060215450A1 (en) * 2005-03-28 2006-09-28 Kabushiki Kaisha Toshiba Semiconductor memory device
TW201830401A (zh) * 2016-03-02 2018-08-16 日商東芝記憶體股份有限公司 半導體記憶裝置
US20180068739A1 (en) * 2016-09-06 2018-03-08 Toshiba Memory Corporation Memory device
TW202011412A (zh) * 2018-09-14 2020-03-16 日商東芝記憶體股份有限公司 半導體記憶裝置

Also Published As

Publication number Publication date
JP2021174567A (ja) 2021-11-01
US11978508B2 (en) 2024-05-07
CN113571112B (zh) 2024-04-19
TW202143447A (zh) 2021-11-16
US11527284B2 (en) 2022-12-13
US20210335418A1 (en) 2021-10-28
CN113571112A (zh) 2021-10-29
US20230062330A1 (en) 2023-03-02

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