TWI800892B - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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Publication number
TWI800892B
TWI800892B TW110129741A TW110129741A TWI800892B TW I800892 B TWI800892 B TW I800892B TW 110129741 A TW110129741 A TW 110129741A TW 110129741 A TW110129741 A TW 110129741A TW I800892 B TWI800892 B TW I800892B
Authority
TW
Taiwan
Prior art keywords
semiconductor device
semiconductor
Prior art date
Application number
TW110129741A
Other languages
English (en)
Other versions
TW202240863A (zh
Inventor
源貴利
東海林翔
鈴木良尚
Original Assignee
日商鎧俠股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商鎧俠股份有限公司 filed Critical 日商鎧俠股份有限公司
Publication of TW202240863A publication Critical patent/TW202240863A/zh
Application granted granted Critical
Publication of TWI800892B publication Critical patent/TWI800892B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/148—Details of power up or power down circuits, standby circuits or recovery circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
TW110129741A 2021-01-12 2021-08-12 半導體裝置 TWI800892B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2021003038A JP2022108157A (ja) 2021-01-12 2021-01-12 半導体装置
JP2021-003038 2021-01-12

Publications (2)

Publication Number Publication Date
TW202240863A TW202240863A (zh) 2022-10-16
TWI800892B true TWI800892B (zh) 2023-05-01

Family

ID=82322520

Family Applications (1)

Application Number Title Priority Date Filing Date
TW110129741A TWI800892B (zh) 2021-01-12 2021-08-12 半導體裝置

Country Status (4)

Country Link
US (1) US20220223611A1 (zh)
JP (1) JP2022108157A (zh)
CN (1) CN114759036A (zh)
TW (1) TWI800892B (zh)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5524036A (en) * 1993-05-27 1996-06-04 Nec Corporation Charge transfer device having charge injection source for reset drain region
TW201618293A (zh) * 2014-10-03 2016-05-16 豪威科技股份有限公司 具有具中心接觸件之通道區域之光感測器
US20180212604A1 (en) * 2017-01-25 2018-07-26 Kabushiki Kaisha Tokai-Rika-Denki-Seisakusho Level shifter

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU2001286432A1 (en) * 2000-08-14 2002-02-25 Matrix Semiconductor, Inc. Dense arrays and charge storage devices, and methods for making same
JP2011210901A (ja) * 2010-03-29 2011-10-20 Seiko Instruments Inc デプレッション型ｍｏｓトランジスタ
KR101717587B1 (ko) * 2011-04-12 2017-03-17 삼성전자주식회사 종단 회로, 종단 회로를 포함하는 송신 장치 및 송신 장치를 포함하는 멀티미디어 소스 장치
US10038006B2 (en) * 2015-12-22 2018-07-31 Sandisk Technologies Llc Through-memory-level via structures for a three-dimensional memory device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5524036A (en) * 1993-05-27 1996-06-04 Nec Corporation Charge transfer device having charge injection source for reset drain region
TW201618293A (zh) * 2014-10-03 2016-05-16 豪威科技股份有限公司 具有具中心接觸件之通道區域之光感測器
US20180212604A1 (en) * 2017-01-25 2018-07-26 Kabushiki Kaisha Tokai-Rika-Denki-Seisakusho Level shifter

Also Published As

Publication number Publication date
TW202240863A (zh) 2022-10-16
US20220223611A1 (en) 2022-07-14
CN114759036A (zh) 2022-07-15
JP2022108157A (ja) 2022-07-25

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